874 lines
23 KiB
Diff
874 lines
23 KiB
Diff
From 16d12015c57701b08d7bbed6ec536641bcafb428 Mon Sep 17 00:00:00 2001
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From: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Mon, 17 May 2021 13:56:52 -0400
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Subject: [PATCH] x86: Optimize memcmp-avx2-movbe.S
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Content-type: text/plain; charset=UTF-8
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No bug. This commit optimizes memcmp-avx2.S. The optimizations include
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adding a new vec compare path for small sizes, reorganizing the entry
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control flow, and removing some unnecissary ALU instructions from the
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main loop. test-memcmp and test-wmemcmp are both passing.
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Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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---
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sysdeps/x86_64/multiarch/ifunc-impl-list.c | 6 +
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sysdeps/x86_64/multiarch/ifunc-memcmp.h | 1 +
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sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S | 676 +++++++++++--------
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3 files changed, 402 insertions(+), 281 deletions(-)
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diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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index ac097e8d..8be0d78a 100644
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--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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@@ -63,16 +63,19 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL (i, name, memcmp,
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IFUNC_IMPL_ADD (array, i, memcmp,
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(CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (MOVBE)),
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__memcmp_avx2_movbe)
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IFUNC_IMPL_ADD (array, i, memcmp,
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(CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (MOVBE)
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&& CPU_FEATURE_USABLE (RTM)),
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__memcmp_avx2_movbe_rtm)
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IFUNC_IMPL_ADD (array, i, memcmp,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (MOVBE)),
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__memcmp_evex_movbe)
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IFUNC_IMPL_ADD (array, i, memcmp, CPU_FEATURE_USABLE (SSE4_1),
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@@ -732,16 +735,19 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL (i, name, wmemcmp,
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IFUNC_IMPL_ADD (array, i, wmemcmp,
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(CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (MOVBE)),
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__wmemcmp_avx2_movbe)
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IFUNC_IMPL_ADD (array, i, wmemcmp,
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(CPU_FEATURE_USABLE (AVX2)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (MOVBE)
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&& CPU_FEATURE_USABLE (RTM)),
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__wmemcmp_avx2_movbe_rtm)
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IFUNC_IMPL_ADD (array, i, wmemcmp,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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+ && CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (MOVBE)),
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__wmemcmp_evex_movbe)
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IFUNC_IMPL_ADD (array, i, wmemcmp, CPU_FEATURE_USABLE (SSE4_1),
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diff --git a/sysdeps/x86_64/multiarch/ifunc-memcmp.h b/sysdeps/x86_64/multiarch/ifunc-memcmp.h
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index 8043c635..690dffe8 100644
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--- a/sysdeps/x86_64/multiarch/ifunc-memcmp.h
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+++ b/sysdeps/x86_64/multiarch/ifunc-memcmp.h
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@@ -33,6 +33,7 @@ IFUNC_SELECTOR (void)
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
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&& CPU_FEATURE_USABLE_P (cpu_features, MOVBE)
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+ && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
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&& CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
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{
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
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diff --git a/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S b/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S
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index 9d5c9c72..16fc673e 100644
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--- a/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S
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+++ b/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S
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@@ -19,17 +19,23 @@
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#if IS_IN (libc)
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/* memcmp/wmemcmp is implemented as:
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- 1. For size from 2 to 7 bytes, load as big endian with movbe and bswap
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- to avoid branches.
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- 2. Use overlapping compare to avoid branch.
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- 3. Use vector compare when size >= 4 bytes for memcmp or size >= 8
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- bytes for wmemcmp.
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- 4. If size is 8 * VEC_SIZE or less, unroll the loop.
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- 5. Compare 4 * VEC_SIZE at a time with the aligned first memory
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+ 1. Use ymm vector compares when possible. The only case where
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+ vector compares is not possible for when size < VEC_SIZE
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+ and loading from either s1 or s2 would cause a page cross.
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+ 2. For size from 2 to 7 bytes on page cross, load as big endian
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+ with movbe and bswap to avoid branches.
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+ 3. Use xmm vector compare when size >= 4 bytes for memcmp or
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+ size >= 8 bytes for wmemcmp.
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+ 4. Optimistically compare up to first 4 * VEC_SIZE one at a
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+ to check for early mismatches. Only do this if its guranteed the
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+ work is not wasted.
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+ 5. If size is 8 * VEC_SIZE or less, unroll the loop.
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+ 6. Compare 4 * VEC_SIZE at a time with the aligned first memory
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area.
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- 6. Use 2 vector compares when size is 2 * VEC_SIZE or less.
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- 7. Use 4 vector compares when size is 4 * VEC_SIZE or less.
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- 8. Use 8 vector compares when size is 8 * VEC_SIZE or less. */
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+ 7. Use 2 vector compares when size is 2 * VEC_SIZE or less.
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+ 8. Use 4 vector compares when size is 4 * VEC_SIZE or less.
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+ 9. Use 8 vector compares when size is 8 * VEC_SIZE or less. */
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+
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# include <sysdep.h>
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@@ -38,8 +44,10 @@
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# endif
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# ifdef USE_AS_WMEMCMP
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+# define CHAR_SIZE 4
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# define VPCMPEQ vpcmpeqd
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# else
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+# define CHAR_SIZE 1
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# define VPCMPEQ vpcmpeqb
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# endif
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@@ -52,7 +60,7 @@
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# endif
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# define VEC_SIZE 32
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-# define VEC_MASK ((1 << VEC_SIZE) - 1)
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+# define PAGE_SIZE 4096
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/* Warning!
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wmemcmp has to use SIGNED comparison for elements.
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@@ -71,136 +79,359 @@ ENTRY (MEMCMP)
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jb L(less_vec)
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/* From VEC to 2 * VEC. No branch when size == VEC_SIZE. */
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- vmovdqu (%rsi), %ymm2
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- VPCMPEQ (%rdi), %ymm2, %ymm2
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- vpmovmskb %ymm2, %eax
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- subl $VEC_MASK, %eax
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- jnz L(first_vec)
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+ vmovdqu (%rsi), %ymm1
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+ VPCMPEQ (%rdi), %ymm1, %ymm1
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+ vpmovmskb %ymm1, %eax
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+ /* NB: eax must be destination register if going to
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+ L(return_vec_[0,2]). For L(return_vec_3 destination register
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+ must be ecx. */
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+ incl %eax
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+ jnz L(return_vec_0)
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cmpq $(VEC_SIZE * 2), %rdx
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- jbe L(last_vec)
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-
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- VPCMPEQ %ymm0, %ymm0, %ymm0
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- /* More than 2 * VEC. */
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- cmpq $(VEC_SIZE * 8), %rdx
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- ja L(more_8x_vec)
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- cmpq $(VEC_SIZE * 4), %rdx
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- jb L(last_4x_vec)
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-
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- /* From 4 * VEC to 8 * VEC, inclusively. */
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- vmovdqu (%rsi), %ymm1
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- VPCMPEQ (%rdi), %ymm1, %ymm1
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+ jbe L(last_1x_vec)
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+ /* Check second VEC no matter what. */
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vmovdqu VEC_SIZE(%rsi), %ymm2
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- VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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+ VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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+ vpmovmskb %ymm2, %eax
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+ /* If all 4 VEC where equal eax will be all 1s so incl will
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+ overflow and set zero flag. */
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+ incl %eax
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+ jnz L(return_vec_1)
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- vmovdqu (VEC_SIZE * 2)(%rsi), %ymm3
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- VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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+ /* Less than 4 * VEC. */
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+ cmpq $(VEC_SIZE * 4), %rdx
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+ jbe L(last_2x_vec)
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+ /* Check third and fourth VEC no matter what. */
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+ vmovdqu (VEC_SIZE * 2)(%rsi), %ymm3
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+ VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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+ vpmovmskb %ymm3, %eax
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+ incl %eax
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+ jnz L(return_vec_2)
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vmovdqu (VEC_SIZE * 3)(%rsi), %ymm4
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- VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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+ VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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+ vpmovmskb %ymm4, %ecx
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+ incl %ecx
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+ jnz L(return_vec_3)
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- vpand %ymm1, %ymm2, %ymm5
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- vpand %ymm3, %ymm4, %ymm6
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- vpand %ymm5, %ymm6, %ymm5
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+ /* Go to 4x VEC loop. */
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+ cmpq $(VEC_SIZE * 8), %rdx
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+ ja L(more_8x_vec)
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- vptest %ymm0, %ymm5
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- jnc L(4x_vec_end)
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+ /* Handle remainder of size = 4 * VEC + 1 to 8 * VEC without any
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+ branches. */
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+ /* Load first two VEC from s2 before adjusting addresses. */
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+ vmovdqu -(VEC_SIZE * 4)(%rsi, %rdx), %ymm1
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+ vmovdqu -(VEC_SIZE * 3)(%rsi, %rdx), %ymm2
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leaq -(4 * VEC_SIZE)(%rdi, %rdx), %rdi
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leaq -(4 * VEC_SIZE)(%rsi, %rdx), %rsi
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- vmovdqu (%rsi), %ymm1
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- VPCMPEQ (%rdi), %ymm1, %ymm1
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- vmovdqu VEC_SIZE(%rsi), %ymm2
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- VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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- vpand %ymm2, %ymm1, %ymm5
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+ /* Wait to load from s1 until addressed adjust due to
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+ unlamination of microfusion with complex address mode. */
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+ VPCMPEQ (%rdi), %ymm1, %ymm1
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+ VPCMPEQ (VEC_SIZE)(%rdi), %ymm2, %ymm2
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vmovdqu (VEC_SIZE * 2)(%rsi), %ymm3
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- VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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- vpand %ymm3, %ymm5, %ymm5
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-
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+ VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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vmovdqu (VEC_SIZE * 3)(%rsi), %ymm4
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- VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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- vpand %ymm4, %ymm5, %ymm5
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+ VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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- vptest %ymm0, %ymm5
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- jnc L(4x_vec_end)
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- xorl %eax, %eax
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+ /* Reduce VEC0 - VEC4. */
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+ vpand %ymm1, %ymm2, %ymm5
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+ vpand %ymm3, %ymm4, %ymm6
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+ vpand %ymm5, %ymm6, %ymm7
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+ vpmovmskb %ymm7, %ecx
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+ incl %ecx
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+ jnz L(return_vec_0_1_2_3)
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+ /* NB: eax must be zero to reach here. */
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+ VZEROUPPER_RETURN
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+
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+ .p2align 4
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+L(return_vec_0):
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+ tzcntl %eax, %eax
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+# ifdef USE_AS_WMEMCMP
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+ movl (%rdi, %rax), %ecx
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+ xorl %edx, %edx
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+ cmpl (%rsi, %rax), %ecx
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+ /* NB: no partial register stall here because xorl zero idiom
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+ above. */
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+ setg %dl
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+ leal -1(%rdx, %rdx), %eax
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+# else
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+ movzbl (%rsi, %rax), %ecx
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+ movzbl (%rdi, %rax), %eax
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+ subl %ecx, %eax
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+# endif
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L(return_vzeroupper):
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ZERO_UPPER_VEC_REGISTERS_RETURN
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.p2align 4
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-L(last_2x_vec):
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- /* From VEC to 2 * VEC. No branch when size == VEC_SIZE. */
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- vmovdqu (%rsi), %ymm2
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- VPCMPEQ (%rdi), %ymm2, %ymm2
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- vpmovmskb %ymm2, %eax
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- subl $VEC_MASK, %eax
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- jnz L(first_vec)
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+L(return_vec_1):
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+ tzcntl %eax, %eax
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+# ifdef USE_AS_WMEMCMP
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+ movl VEC_SIZE(%rdi, %rax), %ecx
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+ xorl %edx, %edx
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+ cmpl VEC_SIZE(%rsi, %rax), %ecx
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+ setg %dl
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+ leal -1(%rdx, %rdx), %eax
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+# else
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+ movzbl VEC_SIZE(%rsi, %rax), %ecx
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+ movzbl VEC_SIZE(%rdi, %rax), %eax
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+ subl %ecx, %eax
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+# endif
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+ VZEROUPPER_RETURN
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+
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+ .p2align 4
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+L(return_vec_2):
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+ tzcntl %eax, %eax
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+# ifdef USE_AS_WMEMCMP
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+ movl (VEC_SIZE * 2)(%rdi, %rax), %ecx
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+ xorl %edx, %edx
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+ cmpl (VEC_SIZE * 2)(%rsi, %rax), %ecx
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+ setg %dl
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+ leal -1(%rdx, %rdx), %eax
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+# else
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+ movzbl (VEC_SIZE * 2)(%rsi, %rax), %ecx
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+ movzbl (VEC_SIZE * 2)(%rdi, %rax), %eax
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+ subl %ecx, %eax
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+# endif
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+ VZEROUPPER_RETURN
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+
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+ /* NB: p2align 5 here to ensure 4x loop is 32 byte aligned. */
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+ .p2align 5
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+L(8x_return_vec_0_1_2_3):
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+ /* Returning from L(more_8x_vec) requires restoring rsi. */
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+ addq %rdi, %rsi
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+L(return_vec_0_1_2_3):
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+ vpmovmskb %ymm1, %eax
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+ incl %eax
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+ jnz L(return_vec_0)
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-L(last_vec):
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- /* Use overlapping loads to avoid branches. */
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- leaq -VEC_SIZE(%rdi, %rdx), %rdi
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- leaq -VEC_SIZE(%rsi, %rdx), %rsi
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- vmovdqu (%rsi), %ymm2
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- VPCMPEQ (%rdi), %ymm2, %ymm2
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vpmovmskb %ymm2, %eax
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- subl $VEC_MASK, %eax
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- jnz L(first_vec)
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+ incl %eax
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+ jnz L(return_vec_1)
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+
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+ vpmovmskb %ymm3, %eax
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+ incl %eax
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+ jnz L(return_vec_2)
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+L(return_vec_3):
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+ tzcntl %ecx, %ecx
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+# ifdef USE_AS_WMEMCMP
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+ movl (VEC_SIZE * 3)(%rdi, %rcx), %eax
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+ xorl %edx, %edx
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+ cmpl (VEC_SIZE * 3)(%rsi, %rcx), %eax
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+ setg %dl
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+ leal -1(%rdx, %rdx), %eax
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+# else
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+ movzbl (VEC_SIZE * 3)(%rdi, %rcx), %eax
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+ movzbl (VEC_SIZE * 3)(%rsi, %rcx), %ecx
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+ subl %ecx, %eax
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+# endif
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+ VZEROUPPER_RETURN
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+
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+ .p2align 4
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+L(more_8x_vec):
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+ /* Set end of s1 in rdx. */
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+ leaq -(VEC_SIZE * 4)(%rdi, %rdx), %rdx
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+ /* rsi stores s2 - s1. This allows loop to only update one
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+ pointer. */
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+ subq %rdi, %rsi
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+ /* Align s1 pointer. */
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+ andq $-VEC_SIZE, %rdi
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+ /* Adjust because first 4x vec where check already. */
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+ subq $-(VEC_SIZE * 4), %rdi
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+ .p2align 4
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+L(loop_4x_vec):
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+ /* rsi has s2 - s1 so get correct address by adding s1 (in rdi).
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+ */
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+ vmovdqu (%rsi, %rdi), %ymm1
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+ VPCMPEQ (%rdi), %ymm1, %ymm1
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+
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+ vmovdqu VEC_SIZE(%rsi, %rdi), %ymm2
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+ VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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+
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+ vmovdqu (VEC_SIZE * 2)(%rsi, %rdi), %ymm3
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+ VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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+
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+ vmovdqu (VEC_SIZE * 3)(%rsi, %rdi), %ymm4
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+ VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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+
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+ vpand %ymm1, %ymm2, %ymm5
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+ vpand %ymm3, %ymm4, %ymm6
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+ vpand %ymm5, %ymm6, %ymm7
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+ vpmovmskb %ymm7, %ecx
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+ incl %ecx
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+ jnz L(8x_return_vec_0_1_2_3)
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+ subq $-(VEC_SIZE * 4), %rdi
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+ /* Check if s1 pointer at end. */
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+ cmpq %rdx, %rdi
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+ jb L(loop_4x_vec)
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+
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+ subq %rdx, %rdi
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+ /* rdi has 4 * VEC_SIZE - remaining length. */
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+ cmpl $(VEC_SIZE * 3), %edi
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+ jae L(8x_last_1x_vec)
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+ /* Load regardless of branch. */
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+ vmovdqu (VEC_SIZE * 2)(%rsi, %rdx), %ymm3
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+ cmpl $(VEC_SIZE * 2), %edi
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+ jae L(8x_last_2x_vec)
|
|
+
|
|
+ /* Check last 4 VEC. */
|
|
+ vmovdqu (%rsi, %rdx), %ymm1
|
|
+ VPCMPEQ (%rdx), %ymm1, %ymm1
|
|
+
|
|
+ vmovdqu VEC_SIZE(%rsi, %rdx), %ymm2
|
|
+ VPCMPEQ VEC_SIZE(%rdx), %ymm2, %ymm2
|
|
+
|
|
+ VPCMPEQ (VEC_SIZE * 2)(%rdx), %ymm3, %ymm3
|
|
+
|
|
+ vmovdqu (VEC_SIZE * 3)(%rsi, %rdx), %ymm4
|
|
+ VPCMPEQ (VEC_SIZE * 3)(%rdx), %ymm4, %ymm4
|
|
+
|
|
+ vpand %ymm1, %ymm2, %ymm5
|
|
+ vpand %ymm3, %ymm4, %ymm6
|
|
+ vpand %ymm5, %ymm6, %ymm7
|
|
+ vpmovmskb %ymm7, %ecx
|
|
+ /* Restore s1 pointer to rdi. */
|
|
+ movq %rdx, %rdi
|
|
+ incl %ecx
|
|
+ jnz L(8x_return_vec_0_1_2_3)
|
|
+ /* NB: eax must be zero to reach here. */
|
|
+ VZEROUPPER_RETURN
|
|
+
|
|
+ /* Only entry is from L(more_8x_vec). */
|
|
+ .p2align 4
|
|
+L(8x_last_2x_vec):
|
|
+ /* Check second to last VEC. rdx store end pointer of s1 and
|
|
+ ymm3 has already been loaded with second to last VEC from s2.
|
|
+ */
|
|
+ VPCMPEQ (VEC_SIZE * 2)(%rdx), %ymm3, %ymm3
|
|
+ vpmovmskb %ymm3, %eax
|
|
+ incl %eax
|
|
+ jnz L(8x_return_vec_2)
|
|
+ /* Check last VEC. */
|
|
+ .p2align 4
|
|
+L(8x_last_1x_vec):
|
|
+ vmovdqu (VEC_SIZE * 3)(%rsi, %rdx), %ymm4
|
|
+ VPCMPEQ (VEC_SIZE * 3)(%rdx), %ymm4, %ymm4
|
|
+ vpmovmskb %ymm4, %eax
|
|
+ incl %eax
|
|
+ jnz L(8x_return_vec_3)
|
|
VZEROUPPER_RETURN
|
|
|
|
.p2align 4
|
|
-L(first_vec):
|
|
- /* A byte or int32 is different within 16 or 32 bytes. */
|
|
- tzcntl %eax, %ecx
|
|
+L(last_2x_vec):
|
|
+ /* Check second to last VEC. */
|
|
+ vmovdqu -(VEC_SIZE * 2)(%rsi, %rdx), %ymm1
|
|
+ VPCMPEQ -(VEC_SIZE * 2)(%rdi, %rdx), %ymm1, %ymm1
|
|
+ vpmovmskb %ymm1, %eax
|
|
+ incl %eax
|
|
+ jnz L(return_vec_1_end)
|
|
+ /* Check last VEC. */
|
|
+L(last_1x_vec):
|
|
+ vmovdqu -(VEC_SIZE * 1)(%rsi, %rdx), %ymm1
|
|
+ VPCMPEQ -(VEC_SIZE * 1)(%rdi, %rdx), %ymm1, %ymm1
|
|
+ vpmovmskb %ymm1, %eax
|
|
+ incl %eax
|
|
+ jnz L(return_vec_0_end)
|
|
+ VZEROUPPER_RETURN
|
|
+
|
|
+ .p2align 4
|
|
+L(8x_return_vec_2):
|
|
+ subq $VEC_SIZE, %rdx
|
|
+L(8x_return_vec_3):
|
|
+ tzcntl %eax, %eax
|
|
+ addq %rdx, %rax
|
|
# ifdef USE_AS_WMEMCMP
|
|
- xorl %eax, %eax
|
|
- movl (%rdi, %rcx), %edx
|
|
- cmpl (%rsi, %rcx), %edx
|
|
-L(wmemcmp_return):
|
|
- setl %al
|
|
- negl %eax
|
|
- orl $1, %eax
|
|
+ movl (VEC_SIZE * 3)(%rax), %ecx
|
|
+ xorl %edx, %edx
|
|
+ cmpl (VEC_SIZE * 3)(%rsi, %rax), %ecx
|
|
+ setg %dl
|
|
+ leal -1(%rdx, %rdx), %eax
|
|
# else
|
|
- movzbl (%rdi, %rcx), %eax
|
|
- movzbl (%rsi, %rcx), %edx
|
|
- sub %edx, %eax
|
|
+ movzbl (VEC_SIZE * 3)(%rsi, %rax), %ecx
|
|
+ movzbl (VEC_SIZE * 3)(%rax), %eax
|
|
+ subl %ecx, %eax
|
|
# endif
|
|
VZEROUPPER_RETURN
|
|
|
|
-# ifdef USE_AS_WMEMCMP
|
|
.p2align 4
|
|
-L(4):
|
|
- xorl %eax, %eax
|
|
- movl (%rdi), %edx
|
|
- cmpl (%rsi), %edx
|
|
- jne L(wmemcmp_return)
|
|
- ret
|
|
+L(return_vec_1_end):
|
|
+ tzcntl %eax, %eax
|
|
+ addl %edx, %eax
|
|
+# ifdef USE_AS_WMEMCMP
|
|
+ movl -(VEC_SIZE * 2)(%rdi, %rax), %ecx
|
|
+ xorl %edx, %edx
|
|
+ cmpl -(VEC_SIZE * 2)(%rsi, %rax), %ecx
|
|
+ setg %dl
|
|
+ leal -1(%rdx, %rdx), %eax
|
|
# else
|
|
+ movzbl -(VEC_SIZE * 2)(%rsi, %rax), %ecx
|
|
+ movzbl -(VEC_SIZE * 2)(%rdi, %rax), %eax
|
|
+ subl %ecx, %eax
|
|
+# endif
|
|
+ VZEROUPPER_RETURN
|
|
+
|
|
.p2align 4
|
|
-L(between_4_7):
|
|
- /* Load as big endian with overlapping movbe to avoid branches. */
|
|
- movbe (%rdi), %eax
|
|
- movbe (%rsi), %ecx
|
|
- shlq $32, %rax
|
|
- shlq $32, %rcx
|
|
- movbe -4(%rdi, %rdx), %edi
|
|
- movbe -4(%rsi, %rdx), %esi
|
|
- orq %rdi, %rax
|
|
- orq %rsi, %rcx
|
|
- subq %rcx, %rax
|
|
- je L(exit)
|
|
- sbbl %eax, %eax
|
|
- orl $1, %eax
|
|
- ret
|
|
+L(return_vec_0_end):
|
|
+ tzcntl %eax, %eax
|
|
+ addl %edx, %eax
|
|
+# ifdef USE_AS_WMEMCMP
|
|
+ movl -VEC_SIZE(%rdi, %rax), %ecx
|
|
+ xorl %edx, %edx
|
|
+ cmpl -VEC_SIZE(%rsi, %rax), %ecx
|
|
+ setg %dl
|
|
+ leal -1(%rdx, %rdx), %eax
|
|
+# else
|
|
+ movzbl -VEC_SIZE(%rsi, %rax), %ecx
|
|
+ movzbl -VEC_SIZE(%rdi, %rax), %eax
|
|
+ subl %ecx, %eax
|
|
+# endif
|
|
+ VZEROUPPER_RETURN
|
|
|
|
.p2align 4
|
|
-L(exit):
|
|
- ret
|
|
+L(less_vec):
|
|
+ /* Check if one or less CHAR. This is necessary for size = 0 but
|
|
+ is also faster for size = CHAR_SIZE. */
|
|
+ cmpl $CHAR_SIZE, %edx
|
|
+ jbe L(one_or_less)
|
|
+
|
|
+ /* Check if loading one VEC from either s1 or s2 could cause a
|
|
+ page cross. This can have false positives but is by far the
|
|
+ fastest method. */
|
|
+ movl %edi, %eax
|
|
+ orl %esi, %eax
|
|
+ andl $(PAGE_SIZE - 1), %eax
|
|
+ cmpl $(PAGE_SIZE - VEC_SIZE), %eax
|
|
+ jg L(page_cross_less_vec)
|
|
+
|
|
+ /* No page cross possible. */
|
|
+ vmovdqu (%rsi), %ymm2
|
|
+ VPCMPEQ (%rdi), %ymm2, %ymm2
|
|
+ vpmovmskb %ymm2, %eax
|
|
+ incl %eax
|
|
+ /* Result will be zero if s1 and s2 match. Otherwise first set
|
|
+ bit will be first mismatch. */
|
|
+ bzhil %edx, %eax, %edx
|
|
+ jnz L(return_vec_0)
|
|
+ xorl %eax, %eax
|
|
+ VZEROUPPER_RETURN
|
|
|
|
.p2align 4
|
|
-L(between_2_3):
|
|
+L(page_cross_less_vec):
|
|
+ /* if USE_AS_WMEMCMP it can only be 0, 4, 8, 12, 16, 20, 24, 28
|
|
+ bytes. */
|
|
+ cmpl $16, %edx
|
|
+ jae L(between_16_31)
|
|
+# ifndef USE_AS_WMEMCMP
|
|
+ cmpl $8, %edx
|
|
+ jae L(between_8_15)
|
|
+ cmpl $4, %edx
|
|
+ jae L(between_4_7)
|
|
+
|
|
/* Load as big endian to avoid branches. */
|
|
movzwl (%rdi), %eax
|
|
movzwl (%rsi), %ecx
|
|
@@ -208,223 +439,106 @@ L(between_2_3):
|
|
shll $8, %ecx
|
|
bswap %eax
|
|
bswap %ecx
|
|
- movb -1(%rdi, %rdx), %al
|
|
- movb -1(%rsi, %rdx), %cl
|
|
+ movzbl -1(%rdi, %rdx), %edi
|
|
+ movzbl -1(%rsi, %rdx), %esi
|
|
+ orl %edi, %eax
|
|
+ orl %esi, %ecx
|
|
/* Subtraction is okay because the upper 8 bits are zero. */
|
|
subl %ecx, %eax
|
|
+ /* No ymm register was touched. */
|
|
ret
|
|
|
|
.p2align 4
|
|
-L(1):
|
|
- movzbl (%rdi), %eax
|
|
+L(one_or_less):
|
|
+ jb L(zero)
|
|
movzbl (%rsi), %ecx
|
|
+ movzbl (%rdi), %eax
|
|
subl %ecx, %eax
|
|
- ret
|
|
-# endif
|
|
-
|
|
- .p2align 4
|
|
-L(zero):
|
|
- xorl %eax, %eax
|
|
+ /* No ymm register was touched. */
|
|
ret
|
|
|
|
.p2align 4
|
|
-L(less_vec):
|
|
-# ifdef USE_AS_WMEMCMP
|
|
- /* It can only be 0, 4, 8, 12, 16, 20, 24, 28 bytes. */
|
|
- cmpb $4, %dl
|
|
- je L(4)
|
|
- jb L(zero)
|
|
-# else
|
|
- cmpb $1, %dl
|
|
- je L(1)
|
|
- jb L(zero)
|
|
- cmpb $4, %dl
|
|
- jb L(between_2_3)
|
|
- cmpb $8, %dl
|
|
- jb L(between_4_7)
|
|
+L(between_8_15):
|
|
# endif
|
|
- cmpb $16, %dl
|
|
- jae L(between_16_31)
|
|
- /* It is between 8 and 15 bytes. */
|
|
+ /* If USE_AS_WMEMCMP fall through into 8-15 byte case. */
|
|
vmovq (%rdi), %xmm1
|
|
vmovq (%rsi), %xmm2
|
|
- VPCMPEQ %xmm1, %xmm2, %xmm2
|
|
+ VPCMPEQ %xmm1, %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
- subl $0xffff, %eax
|
|
- jnz L(first_vec)
|
|
+ subl $0xffff, %eax
|
|
+ jnz L(return_vec_0)
|
|
/* Use overlapping loads to avoid branches. */
|
|
leaq -8(%rdi, %rdx), %rdi
|
|
leaq -8(%rsi, %rdx), %rsi
|
|
vmovq (%rdi), %xmm1
|
|
vmovq (%rsi), %xmm2
|
|
- VPCMPEQ %xmm1, %xmm2, %xmm2
|
|
+ VPCMPEQ %xmm1, %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
- subl $0xffff, %eax
|
|
- jnz L(first_vec)
|
|
+ subl $0xffff, %eax
|
|
+ jnz L(return_vec_0)
|
|
+ /* No ymm register was touched. */
|
|
+ ret
|
|
+
|
|
+ .p2align 4
|
|
+L(zero):
|
|
+ xorl %eax, %eax
|
|
ret
|
|
|
|
.p2align 4
|
|
L(between_16_31):
|
|
/* From 16 to 31 bytes. No branch when size == 16. */
|
|
vmovdqu (%rsi), %xmm2
|
|
- VPCMPEQ (%rdi), %xmm2, %xmm2
|
|
+ VPCMPEQ (%rdi), %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
- subl $0xffff, %eax
|
|
- jnz L(first_vec)
|
|
+ subl $0xffff, %eax
|
|
+ jnz L(return_vec_0)
|
|
|
|
/* Use overlapping loads to avoid branches. */
|
|
+
|
|
+ vmovdqu -16(%rsi, %rdx), %xmm2
|
|
leaq -16(%rdi, %rdx), %rdi
|
|
leaq -16(%rsi, %rdx), %rsi
|
|
- vmovdqu (%rsi), %xmm2
|
|
- VPCMPEQ (%rdi), %xmm2, %xmm2
|
|
+ VPCMPEQ (%rdi), %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
- subl $0xffff, %eax
|
|
- jnz L(first_vec)
|
|
+ subl $0xffff, %eax
|
|
+ jnz L(return_vec_0)
|
|
+ /* No ymm register was touched. */
|
|
ret
|
|
|
|
- .p2align 4
|
|
-L(more_8x_vec):
|
|
- /* More than 8 * VEC. Check the first VEC. */
|
|
- vmovdqu (%rsi), %ymm2
|
|
- VPCMPEQ (%rdi), %ymm2, %ymm2
|
|
- vpmovmskb %ymm2, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec)
|
|
-
|
|
- /* Align the first memory area for aligned loads in the loop.
|
|
- Compute how much the first memory area is misaligned. */
|
|
- movq %rdi, %rcx
|
|
- andl $(VEC_SIZE - 1), %ecx
|
|
- /* Get the negative of offset for alignment. */
|
|
- subq $VEC_SIZE, %rcx
|
|
- /* Adjust the second memory area. */
|
|
- subq %rcx, %rsi
|
|
- /* Adjust the first memory area which should be aligned now. */
|
|
- subq %rcx, %rdi
|
|
- /* Adjust length. */
|
|
- addq %rcx, %rdx
|
|
-
|
|
-L(loop_4x_vec):
|
|
- /* Compare 4 * VEC at a time forward. */
|
|
- vmovdqu (%rsi), %ymm1
|
|
- VPCMPEQ (%rdi), %ymm1, %ymm1
|
|
-
|
|
- vmovdqu VEC_SIZE(%rsi), %ymm2
|
|
- VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
|
|
- vpand %ymm2, %ymm1, %ymm5
|
|
-
|
|
- vmovdqu (VEC_SIZE * 2)(%rsi), %ymm3
|
|
- VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
|
|
- vpand %ymm3, %ymm5, %ymm5
|
|
-
|
|
- vmovdqu (VEC_SIZE * 3)(%rsi), %ymm4
|
|
- VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
|
|
- vpand %ymm4, %ymm5, %ymm5
|
|
-
|
|
- vptest %ymm0, %ymm5
|
|
- jnc L(4x_vec_end)
|
|
-
|
|
- addq $(VEC_SIZE * 4), %rdi
|
|
- addq $(VEC_SIZE * 4), %rsi
|
|
-
|
|
- subq $(VEC_SIZE * 4), %rdx
|
|
- cmpq $(VEC_SIZE * 4), %rdx
|
|
- jae L(loop_4x_vec)
|
|
-
|
|
- /* Less than 4 * VEC. */
|
|
- cmpq $VEC_SIZE, %rdx
|
|
- jbe L(last_vec)
|
|
- cmpq $(VEC_SIZE * 2), %rdx
|
|
- jbe L(last_2x_vec)
|
|
-
|
|
-L(last_4x_vec):
|
|
- /* From 2 * VEC to 4 * VEC. */
|
|
- vmovdqu (%rsi), %ymm2
|
|
- VPCMPEQ (%rdi), %ymm2, %ymm2
|
|
- vpmovmskb %ymm2, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec)
|
|
-
|
|
- addq $VEC_SIZE, %rdi
|
|
- addq $VEC_SIZE, %rsi
|
|
- vmovdqu (%rsi), %ymm2
|
|
- VPCMPEQ (%rdi), %ymm2, %ymm2
|
|
- vpmovmskb %ymm2, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec)
|
|
-
|
|
- /* Use overlapping loads to avoid branches. */
|
|
- leaq -(3 * VEC_SIZE)(%rdi, %rdx), %rdi
|
|
- leaq -(3 * VEC_SIZE)(%rsi, %rdx), %rsi
|
|
- vmovdqu (%rsi), %ymm2
|
|
- VPCMPEQ (%rdi), %ymm2, %ymm2
|
|
- vpmovmskb %ymm2, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec)
|
|
-
|
|
- addq $VEC_SIZE, %rdi
|
|
- addq $VEC_SIZE, %rsi
|
|
- vmovdqu (%rsi), %ymm2
|
|
- VPCMPEQ (%rdi), %ymm2, %ymm2
|
|
- vpmovmskb %ymm2, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec)
|
|
- VZEROUPPER_RETURN
|
|
-
|
|
- .p2align 4
|
|
-L(4x_vec_end):
|
|
- vpmovmskb %ymm1, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec)
|
|
- vpmovmskb %ymm2, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec_x1)
|
|
- vpmovmskb %ymm3, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- jnz L(first_vec_x2)
|
|
- vpmovmskb %ymm4, %eax
|
|
- subl $VEC_MASK, %eax
|
|
- tzcntl %eax, %ecx
|
|
# ifdef USE_AS_WMEMCMP
|
|
- xorl %eax, %eax
|
|
- movl (VEC_SIZE * 3)(%rdi, %rcx), %edx
|
|
- cmpl (VEC_SIZE * 3)(%rsi, %rcx), %edx
|
|
- jmp L(wmemcmp_return)
|
|
-# else
|
|
- movzbl (VEC_SIZE * 3)(%rdi, %rcx), %eax
|
|
- movzbl (VEC_SIZE * 3)(%rsi, %rcx), %edx
|
|
- sub %edx, %eax
|
|
-# endif
|
|
- VZEROUPPER_RETURN
|
|
-
|
|
.p2align 4
|
|
-L(first_vec_x1):
|
|
- tzcntl %eax, %ecx
|
|
-# ifdef USE_AS_WMEMCMP
|
|
- xorl %eax, %eax
|
|
- movl VEC_SIZE(%rdi, %rcx), %edx
|
|
- cmpl VEC_SIZE(%rsi, %rcx), %edx
|
|
- jmp L(wmemcmp_return)
|
|
+L(one_or_less):
|
|
+ jb L(zero)
|
|
+ movl (%rdi), %ecx
|
|
+ xorl %edx, %edx
|
|
+ cmpl (%rsi), %ecx
|
|
+ je L(zero)
|
|
+ setg %dl
|
|
+ leal -1(%rdx, %rdx), %eax
|
|
+ /* No ymm register was touched. */
|
|
+ ret
|
|
# else
|
|
- movzbl VEC_SIZE(%rdi, %rcx), %eax
|
|
- movzbl VEC_SIZE(%rsi, %rcx), %edx
|
|
- sub %edx, %eax
|
|
-# endif
|
|
- VZEROUPPER_RETURN
|
|
|
|
.p2align 4
|
|
-L(first_vec_x2):
|
|
- tzcntl %eax, %ecx
|
|
-# ifdef USE_AS_WMEMCMP
|
|
- xorl %eax, %eax
|
|
- movl (VEC_SIZE * 2)(%rdi, %rcx), %edx
|
|
- cmpl (VEC_SIZE * 2)(%rsi, %rcx), %edx
|
|
- jmp L(wmemcmp_return)
|
|
-# else
|
|
- movzbl (VEC_SIZE * 2)(%rdi, %rcx), %eax
|
|
- movzbl (VEC_SIZE * 2)(%rsi, %rcx), %edx
|
|
- sub %edx, %eax
|
|
+L(between_4_7):
|
|
+ /* Load as big endian with overlapping movbe to avoid branches.
|
|
+ */
|
|
+ movbe (%rdi), %eax
|
|
+ movbe (%rsi), %ecx
|
|
+ shlq $32, %rax
|
|
+ shlq $32, %rcx
|
|
+ movbe -4(%rdi, %rdx), %edi
|
|
+ movbe -4(%rsi, %rdx), %esi
|
|
+ orq %rdi, %rax
|
|
+ orq %rsi, %rcx
|
|
+ subq %rcx, %rax
|
|
+ jz L(zero_4_7)
|
|
+ sbbl %eax, %eax
|
|
+ orl $1, %eax
|
|
+L(zero_4_7):
|
|
+ /* No ymm register was touched. */
|
|
+ ret
|
|
# endif
|
|
- VZEROUPPER_RETURN
|
|
+
|
|
END (MEMCMP)
|
|
#endif
|
|
--
|
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GitLab
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