124 lines
4.7 KiB
Diff
124 lines
4.7 KiB
Diff
commit 81ecb0ee4970865cbe5d1da733c4879b999c528f
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Author: Paul A. Clarke <pc@us.ibm.com>
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Date: Thu Sep 19 11:58:46 2019 -0500
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[powerpc] Rename fegetenv_status to fegetenv_control
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fegetenv_status is used variously to retrieve the FPSCR exception enable
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bits, rounding mode bits, or both. These are referred to as the control
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bits in the POWER ISA. FPSCR status bits are also returned by the
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'mffs' and 'mffsl' instructions, but they are uniformly ignored by all
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uses of fegetenv_status. Change the name to be reflective of its
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current and expected use.
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Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
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diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c
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index bdf55ac62f1ffe4f..1273987459655585 100644
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--- a/sysdeps/powerpc/fpu/fedisblxcpt.c
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+++ b/sysdeps/powerpc/fpu/fedisblxcpt.c
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@@ -26,7 +26,7 @@ fedisableexcept (int excepts)
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int result, new;
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/* Get current exception mask to return. */
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- fe.fenv = curr.fenv = fegetenv_status ();
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+ fe.fenv = curr.fenv = fegetenv_control ();
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result = fenv_reg_to_exceptions (fe.l);
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if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)
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diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c
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index 78ebabed9232c0ad..fa233c305aedd5f6 100644
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--- a/sysdeps/powerpc/fpu/feenablxcpt.c
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+++ b/sysdeps/powerpc/fpu/feenablxcpt.c
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@@ -26,7 +26,7 @@ feenableexcept (int excepts)
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int result, new;
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/* Get current exception mask to return. */
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- fe.fenv = curr.fenv = fegetenv_status ();
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+ fe.fenv = curr.fenv = fegetenv_control ();
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result = fenv_reg_to_exceptions (fe.l);
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if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)
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diff --git a/sysdeps/powerpc/fpu/fegetexcept.c b/sysdeps/powerpc/fpu/fegetexcept.c
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index 9d77adea59939ece..6bbf11d9d5df61e5 100644
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--- a/sysdeps/powerpc/fpu/fegetexcept.c
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+++ b/sysdeps/powerpc/fpu/fegetexcept.c
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@@ -25,7 +25,7 @@ __fegetexcept (void)
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fenv_union_t fe;
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int result = 0;
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- fe.fenv = fegetenv_status ();
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+ fe.fenv = fegetenv_control ();
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if (fe.l & (1 << (31 - FPSCR_XE)))
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result |= FE_INEXACT;
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diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c
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index 75493e5f24c8b05b..57d6d5275485ebdc 100644
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--- a/sysdeps/powerpc/fpu/fegetmode.c
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+++ b/sysdeps/powerpc/fpu/fegetmode.c
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@@ -21,6 +21,6 @@
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int
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fegetmode (femode_t *modep)
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{
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- *modep = fegetenv_status ();
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+ *modep = fegetenv_control ();
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return 0;
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}
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diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
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index c3f541c08440b20e..b5c8da1adefe93cb 100644
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--- a/sysdeps/powerpc/fpu/fenv_libc.h
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+++ b/sysdeps/powerpc/fpu/fenv_libc.h
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@@ -61,7 +61,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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'mffs' on architectures older than "power9" because the additional
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bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset
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of 'mffsl'. */
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-#define fegetenv_status() \
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+#define fegetenv_control() \
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({register double __fr; \
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__asm__ __volatile__ ( \
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".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
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@@ -85,7 +85,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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__fr.fenv; \
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})
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-/* Like fegetenv_status, but also sets the rounding mode. */
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+/* Like fegetenv_control, but also sets the rounding mode. */
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#ifdef _ARCH_PWR9
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#define fegetenv_and_set_rn(rn) __fe_mffscrn (rn)
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#else
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@@ -116,7 +116,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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/* Set the last 2 nibbles of the FPSCR, which contain the
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exception enables and the rounding mode.
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- 'fegetenv_status' retrieves these bits by reading the FPSCR. */
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+ 'fegetenv_control' retrieves these bits by reading the FPSCR. */
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#define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env));
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/* This very handy macro:
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diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c
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index 4eab5045c48105e3..252114141cd87f8d 100644
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--- a/sysdeps/powerpc/fpu/fesetenv.c
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+++ b/sysdeps/powerpc/fpu/fesetenv.c
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@@ -26,7 +26,7 @@ __fesetenv (const fenv_t *envp)
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/* get the currently set exceptions. */
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new.fenv = *envp;
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- old.fenv = fegetenv_status ();
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+ old.fenv = fegetenv_control ();
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__TEST_AND_EXIT_NON_STOP (old.l, new.l);
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__TEST_AND_ENTER_NON_STOP (old.l, new.l);
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diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c
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index 58ba02c0a1e64c27..e5938af04cb71ca1 100644
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--- a/sysdeps/powerpc/fpu/fesetmode.c
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+++ b/sysdeps/powerpc/fpu/fesetmode.c
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@@ -27,7 +27,7 @@ fesetmode (const femode_t *modep)
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/* Logic regarding enabled exceptions as in fesetenv. */
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new.fenv = *modep;
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- old.fenv = fegetenv_status ();
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+ old.fenv = fegetenv_control ();
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new.l = (new.l & ~FPSCR_STATUS_MASK) | (old.l & FPSCR_STATUS_MASK);
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if (old.l == new.l)
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