From 1ad31173fbf190a9f47ed1e5f925800f0f3b37ec Mon Sep 17 00:00:00 2001 From: Florian Weimer Date: Wed, 3 May 2023 10:53:39 +0200 Subject: [PATCH] Fix incorrect inline feraiseexcept on i686, x86-64 (#2183081) Resolves: #2183081 --- glibc-rh2183081-1.patch | 35 +++++++++++++++++++++++++++++++++++ glibc-rh2183081-2.patch | 28 ++++++++++++++++++++++++++++ glibc.spec | 7 ++++++- 3 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 glibc-rh2183081-1.patch create mode 100644 glibc-rh2183081-2.patch diff --git a/glibc-rh2183081-1.patch b/glibc-rh2183081-1.patch new file mode 100644 index 0000000..9c3829d --- /dev/null +++ b/glibc-rh2183081-1.patch @@ -0,0 +1,35 @@ +commit 5d1ccdda7b0c625751661d50977f3dfbc73f8eae +Author: Florian Weimer +Date: Mon Apr 3 17:23:11 2023 +0200 + + x86_64: Fix asm constraints in feraiseexcept (bug 30305) + + The divss instruction clobbers its first argument, and the constraints + need to reflect that. Fortunately, with GCC 12, generated code does + not actually change, so there is no externally visible bug. + + Suggested-by: Jakub Jelinek + Reviewed-by: Noah Goldstein + +diff --git a/sysdeps/x86_64/fpu/fraiseexcpt.c b/sysdeps/x86_64/fpu/fraiseexcpt.c +index ca1c223053bf016b..fb886ed540b52100 100644 +--- a/sysdeps/x86_64/fpu/fraiseexcpt.c ++++ b/sysdeps/x86_64/fpu/fraiseexcpt.c +@@ -33,7 +33,7 @@ __feraiseexcept (int excepts) + /* One example of an invalid operation is 0.0 / 0.0. */ + float f = 0.0; + +- __asm__ __volatile__ ("divss %0, %0 " : : "x" (f)); ++ __asm__ __volatile__ ("divss %0, %0 " : "+x" (f)); + (void) &f; + } + +@@ -43,7 +43,7 @@ __feraiseexcept (int excepts) + float f = 1.0; + float g = 0.0; + +- __asm__ __volatile__ ("divss %1, %0" : : "x" (f), "x" (g)); ++ __asm__ __volatile__ ("divss %1, %0" : "+x" (f) : "x" (g)); + (void) &f; + } + diff --git a/glibc-rh2183081-2.patch b/glibc-rh2183081-2.patch new file mode 100644 index 0000000..215b47f --- /dev/null +++ b/glibc-rh2183081-2.patch @@ -0,0 +1,28 @@ +Apply a fix similar to upstream commit 5d1ccdda7b0c625751661d50977f3dfbc73f8eae +to the installed header file. Upstream, the header file has been removed +in its uncorrected state, so there is no upstream fix to backport. + +Suggested by Jakub Jelinek. + +diff --git a/sysdeps/x86/fpu/bits/fenv.h b/sysdeps/x86/fpu/bits/fenv.h +index 4103982d8c8ae014..4ae2d2a04c6754bd 100644 +--- a/sysdeps/x86/fpu/bits/fenv.h ++++ b/sysdeps/x86/fpu/bits/fenv.h +@@ -132,7 +132,7 @@ __NTH (__feraiseexcept_invalid_divbyzero (int __excepts)) + float __f = 0.0; + + # ifdef __SSE_MATH__ +- __asm__ __volatile__ ("divss %0, %0 " : : "x" (__f)); ++ __asm__ __volatile__ ("divss %0, %0 " : "+x" (__f)); + # else + __asm__ __volatile__ ("fdiv %%st, %%st(0); fwait" + : "=t" (__f) : "0" (__f)); +@@ -145,7 +145,7 @@ __NTH (__feraiseexcept_invalid_divbyzero (int __excepts)) + float __g = 0.0; + + # ifdef __SSE_MATH__ +- __asm__ __volatile__ ("divss %1, %0" : : "x" (__f), "x" (__g)); ++ __asm__ __volatile__ ("divss %1, %0" : "+x" (__f) : "x" (__g)); + # else + __asm__ __volatile__ ("fdivp %%st, %%st(1); fwait" + : "=t" (__f) : "0" (__f), "u" (__g) : "st(1)"); diff --git a/glibc.spec b/glibc.spec index c1e7d19..20c9aab 100644 --- a/glibc.spec +++ b/glibc.spec @@ -1,6 +1,6 @@ %define glibcsrcdir glibc-2.28 %define glibcversion 2.28 -%define glibcrelease 225%{?dist} +%define glibcrelease 226%{?dist} # Pre-release tarballs are pulled in from git using a command that is # effectively: # @@ -1031,6 +1031,8 @@ Patch838: glibc-rh2142937-3.patch Patch839: glibc-rh2144568.patch Patch840: glibc-rh2154914-1.patch Patch841: glibc-rh2154914-2.patch +Patch842: glibc-rh2183081-1.patch +Patch843: glibc-rh2183081-2.patch ############################################################################## # Continued list of core "glibc" package information: @@ -2861,6 +2863,9 @@ fi %files -f compat-libpthread-nonshared.filelist -n compat-libpthread-nonshared %changelog +* Wed May 3 2023 Florian Weimer - 2.28-226 +- Fix incorrect inline feraiseexcept on i686, x86-64 (#2183081) + * Fri Jan 20 2023 Florian Weimer - 2.28-225 - Enforce a specififc internal ordering for tunables (#2154914)