From 01cc656c6346ca5137a71d106cc880ba90923ed7 Mon Sep 17 00:00:00 2001 From: Florian Weimer Date: Mon, 9 Oct 2023 15:43:47 +0200 Subject: [PATCH] x86-64: Report non-zero cache sizes under TDX hypervisors (RHEL-1191) Resolves: RHEL-1191 --- glibc-RHEL-1191.patch | 69 +++++++++++++++++++++++++++++++++++++++++++ glibc.spec | 6 +++- 2 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 glibc-RHEL-1191.patch diff --git a/glibc-RHEL-1191.patch b/glibc-RHEL-1191.patch new file mode 100644 index 0000000..3cb6635 --- /dev/null +++ b/glibc-RHEL-1191.patch @@ -0,0 +1,69 @@ +commit 1493622f4f9048ffede3fbedb64695efa49d662a +Author: H.J. Lu +Date: Mon Aug 28 12:08:14 2023 -0700 + + x86: Check the lower byte of EAX of CPUID leaf 2 [BZ #30643] + + The old Intel software developer manual specified that the low byte of + EAX of CPUID leaf 2 returned 1 which indicated the number of rounds of + CPUDID leaf 2 was needed to retrieve the complete cache information. The + newer Intel manual has been changed to that it should always return 1 + and be ignored. If the lower byte isn't 1, CPUID leaf 2 can't be used. + In this case, we ignore CPUID leaf 2 and use CPUID leaf 4 instead. If + CPUID leaf 4 doesn't contain the cache information, cache information + isn't available at all. This addresses BZ #30643. + +diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h +index f950e488cfbe42dd..bd2f2b65f78056ca 100644 +--- a/sysdeps/x86/dl-cacheinfo.h ++++ b/sysdeps/x86/dl-cacheinfo.h +@@ -187,7 +187,7 @@ intel_check_word (int name, unsigned int value, bool *has_level_2, + ++round; + } + /* There is no other cache information anywhere else. */ +- break; ++ return -1; + } + else + { +@@ -257,28 +257,23 @@ handle_intel (int name, const struct cpu_features *cpu_features) + + /* OK, we can use the CPUID instruction to get all info about the + caches. */ +- unsigned int cnt = 0; +- unsigned int max = 1; + long int result = 0; + bool no_level_2_or_3 = false; + bool has_level_2 = false; ++ unsigned int eax; ++ unsigned int ebx; ++ unsigned int ecx; ++ unsigned int edx; ++ __cpuid (2, eax, ebx, ecx, edx); + +- while (cnt++ < max) ++ /* The low byte of EAX of CPUID leaf 2 should always return 1 and it ++ should be ignored. If it isn't 1, use CPUID leaf 4 instead. */ ++ if ((eax & 0xff) != 1) ++ return intel_check_word (name, 0xff, &has_level_2, &no_level_2_or_3, ++ cpu_features); ++ else + { +- unsigned int eax; +- unsigned int ebx; +- unsigned int ecx; +- unsigned int edx; +- __cpuid (2, eax, ebx, ecx, edx); +- +- /* The low byte of EAX in the first round contain the number of +- rounds we have to make. At least one, the one we are already +- doing. */ +- if (cnt == 1) +- { +- max = eax & 0xff; +- eax &= 0xffffff00; +- } ++ eax &= 0xffffff00; + + /* Process the individual registers' value. */ + result = intel_check_word (name, eax, &has_level_2, diff --git a/glibc.spec b/glibc.spec index 15f0b37..3bca7c9 100644 --- a/glibc.spec +++ b/glibc.spec @@ -155,7 +155,7 @@ end \ Summary: The GNU libc libraries Name: glibc Version: %{glibcversion} -Release: 83%{?dist}.7 +Release: 84%{?dist} # In general, GPLv2+ is used by programs, LGPLv2+ is used for # libraries. @@ -770,6 +770,7 @@ Patch533: glibc-RHEL-2426-13.patch Patch534: glibc-RHEL-3000.patch Patch535: glibc-RHEL-2426-14.patch Patch536: glibc-RHEL-2426-15.patch +Patch537: glibc-RHEL-1191.patch ############################################################################## # Continued list of core "glibc" package information: @@ -2927,6 +2928,9 @@ update_gconv_modules_cache () %endif %changelog +* Mon Oct 9 2023 Florian Weimer - 2.34-84 +- x86-64: Report non-zero cache sizes under TDX hypervisors (RHEL-1191) + * Mon Sep 25 2023 Florian Weimer - 2.34-83.7 - Fix memory leak regression in getaddrinfo (RHEL-2426)