156 lines
6.5 KiB
Diff
156 lines
6.5 KiB
Diff
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From 0c0d39fe4aeb0f69b26e76337c5dfd5530d5d44e Mon Sep 17 00:00:00 2001
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From: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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Date: Thu, 8 Feb 2024 10:08:38 -0300
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Subject: [PATCH] x86: Fix Zen3/Zen4 ERMS selection (BZ 30994)
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Content-type: text/plain; charset=UTF-8
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The REP MOVSB usage on memcpy/memmove does not show much performance
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improvement on Zen3/Zen4 cores compared to the vectorized loops. Also,
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as from BZ 30994, if the source is aligned and the destination is not
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the performance can be 20x slower.
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The performance difference is noticeable with small buffer sizes, closer
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to the lower bounds limits when memcpy/memmove starts to use ERMS. The
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performance of REP MOVSB is similar to vectorized instruction on the
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size limit (the L2 cache). Also, there is no drawback to multiple cores
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sharing the cache.
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Checked on x86_64-linux-gnu on Zen3.
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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Conflicts:
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sysdeps/x86/dl-cacheinfo.h
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(tweaked for changed context)
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---
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sysdeps/x86/dl-cacheinfo.h | 38 ++++++++++++++++++--------------------
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1 file changed, 18 insertions(+), 20 deletions(-)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index d5101615e3..f34d12846c 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -791,7 +791,6 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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long int data = -1;
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long int shared = -1;
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long int shared_per_thread = -1;
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- long int core = -1;
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unsigned int threads = 0;
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unsigned long int level1_icache_size = -1;
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unsigned long int level1_icache_linesize = -1;
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@@ -809,7 +808,6 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (cpu_features->basic.kind == arch_kind_intel)
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{
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data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
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- core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
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shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
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shared_per_thread = shared;
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@@ -822,7 +820,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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= handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features);
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level1_dcache_linesize
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= handle_intel (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features);
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- level2_cache_size = core;
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+ level2_cache_size
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+ = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
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level2_cache_assoc
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= handle_intel (_SC_LEVEL2_CACHE_ASSOC, cpu_features);
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level2_cache_linesize
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@@ -835,12 +834,12 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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level4_cache_size
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= handle_intel (_SC_LEVEL4_CACHE_SIZE, cpu_features);
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- get_common_cache_info (&shared, &shared_per_thread, &threads, core);
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+ get_common_cache_info (&shared, &shared_per_thread, &threads,
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+ level2_cache_size);
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}
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else if (cpu_features->basic.kind == arch_kind_zhaoxin)
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{
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data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE);
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- core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE);
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shared_per_thread = shared;
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@@ -849,19 +848,19 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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level1_dcache_size = data;
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level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC);
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level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE);
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- level2_cache_size = core;
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+ level2_cache_size = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE);
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level2_cache_assoc = handle_zhaoxin (_SC_LEVEL2_CACHE_ASSOC);
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level2_cache_linesize = handle_zhaoxin (_SC_LEVEL2_CACHE_LINESIZE);
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level3_cache_size = shared;
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level3_cache_assoc = handle_zhaoxin (_SC_LEVEL3_CACHE_ASSOC);
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level3_cache_linesize = handle_zhaoxin (_SC_LEVEL3_CACHE_LINESIZE);
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- get_common_cache_info (&shared, &shared_per_thread, &threads, core);
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+ get_common_cache_info (&shared, &shared_per_thread, &threads,
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+ level2_cache_size);
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}
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else if (cpu_features->basic.kind == arch_kind_amd)
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{
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data = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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- core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
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level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE);
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@@ -869,7 +868,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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level1_dcache_size = data;
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level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC);
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level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE);
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- level2_cache_size = core;
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+ level2_cache_size = handle_amd (_SC_LEVEL2_CACHE_SIZE);;
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level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC);
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level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE);
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level3_cache_size = shared;
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@@ -880,12 +879,12 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (shared <= 0)
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{
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/* No shared L3 cache. All we have is the L2 cache. */
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- shared = core;
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+ shared = level2_cache_size;
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}
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else if (cpu_features->basic.family < 0x17)
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{
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/* Account for exclusive L2 and L3 caches. */
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- shared += core;
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+ shared += level2_cache_size;
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}
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shared_per_thread = shared;
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@@ -987,6 +986,12 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (CPU_FEATURE_USABLE_P (cpu_features, FSRM))
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rep_movsb_threshold = 2112;
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+ /* For AMD CPUs that support ERMS (Zen3+), REP MOVSB is in a lot of
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+ cases slower than the vectorized path (and for some alignments,
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+ it is really slow, check BZ #30994). */
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+ if (cpu_features->basic.kind == arch_kind_amd)
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+ rep_movsb_threshold = non_temporal_threshold;
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+
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/* The default threshold to use Enhanced REP STOSB. */
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unsigned long int rep_stosb_threshold = 2048;
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@@ -1028,15 +1033,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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#endif
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unsigned long int rep_movsb_stop_threshold;
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- /* ERMS feature is implemented from AMD Zen3 architecture and it is
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- performing poorly for data above L2 cache size. Henceforth, adding
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- an upper bound threshold parameter to limit the usage of Enhanced
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- REP MOVSB operations and setting its value to L2 cache size. */
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- if (cpu_features->basic.kind == arch_kind_amd)
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- rep_movsb_stop_threshold = core;
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/* Setting the upper bound of ERMS to the computed value of
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- non-temporal threshold for architectures other than AMD. */
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- else
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- rep_movsb_stop_threshold = non_temporal_threshold;
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+ non-temporal threshold for all architectures. */
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+ rep_movsb_stop_threshold = non_temporal_threshold;
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cpu_features->data_cache_size = data;
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cpu_features->shared_cache_size = shared;
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--
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2.39.3
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