35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
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From 272708884cb750f12f5c74a00e6620c19dc6d567 Mon Sep 17 00:00:00 2001
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From: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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Date: Thu, 8 Feb 2024 10:08:39 -0300
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Subject: [PATCH] x86: Do not prefer ERMS for memset on Zen3+
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Content-type: text/plain; charset=UTF-8
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For AMD Zen3+ architecture, the performance of the vectorized loop is
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slightly better than ERMS.
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Checked on x86_64-linux-gnu on Zen3.
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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---
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sysdeps/x86/dl-cacheinfo.h | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index f34d12846c..5a98f70364 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -1021,6 +1021,11 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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minimum value is fixed. */
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rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold,
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long int, NULL);
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+ if (cpu_features->basic.kind == arch_kind_amd
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+ && !TUNABLE_IS_INITIALIZED (x86_rep_stosb_threshold))
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+ /* For AMD Zen3+ architecture, the performance of the vectorized loop is
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+ slightly better than ERMS. */
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+ rep_stosb_threshold = SIZE_MAX;
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TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX);
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TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX);
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--
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2.39.3
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