55 lines
2.7 KiB
Diff
55 lines
2.7 KiB
Diff
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commit 94b0dc9419bd038cb85b364a7556569386c31741
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Author: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Wed Jun 15 10:41:29 2022 -0700
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x86: Add bounds `x86_non_temporal_threshold`
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The lower-bound (16448) and upper-bound (SIZE_MAX / 16) are assumed
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by memmove-vec-unaligned-erms.
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The lower-bound is needed because memmove-vec-unaligned-erms unrolls
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the loop aggressively in the L(large_memset_4x) case.
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The upper-bound is needed because memmove-vec-unaligned-erms
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right-shifts the value of `x86_non_temporal_threshold` by
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LOG_4X_MEMCPY_THRESH (4) which without a bound may overflow.
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The lack of lower-bound can be a correctness issue. The lack of
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upper-bound cannot.
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(cherry picked from commit b446822b6ae4e8149902a78cdd4a886634ad6321)
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diff --git a/manual/tunables.texi b/manual/tunables.texi
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index 28ff502990c2a10f..5ab3212f34e3dc37 100644
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--- a/manual/tunables.texi
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+++ b/manual/tunables.texi
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@@ -47,7 +47,7 @@ glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0xffffffffffffffff)
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glibc.elision.skip_lock_busy: 3 (min: -2147483648, max: 2147483647)
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glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0xffffffffffffffff)
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glibc.cpu.x86_rep_stosb_threshold: 0x800 (min: 0x1, max: 0xffffffffffffffff)
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-glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x0, max: 0xffffffffffffffff)
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+glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x4040, max: 0x0fffffffffffffff)
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glibc.cpu.x86_shstk:
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glibc.cpu.hwcap_mask: 0x6 (min: 0x0, max: 0xffffffffffffffff)
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glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index 560bf260e8fbd7bf..8f85f70858413ebe 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -931,8 +931,14 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX);
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TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX);
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+ /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
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+ 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best
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+ if that operation cannot overflow. Minimum of 0x4040 (16448) because the
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+ L(large_memset_4x) loops need 64-byte to cache align and enough space for
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+ at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are
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+ reflected in the manual. */
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TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, non_temporal_threshold,
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- 0, SIZE_MAX);
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+ 0x4040, SIZE_MAX >> 4);
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TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, rep_movsb_threshold,
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minimum_rep_movsb_threshold, SIZE_MAX);
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TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, rep_stosb_threshold, 1,
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