2022-11-15 07:04:49 +00:00
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commit 4c92a1041257c0155c6aa7a182fe5f78e477b0e6
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2022-09-20 11:49:23 +00:00
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Author: Matheus Castanho <msc@linux.ibm.com>
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Date: Tue Jun 7 10:27:26 2022 -0300
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powerpc: Fix VSX register number on __strncpy_power9 [BZ #29197]
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__strncpy_power9 initializes VR 18 with zeroes to be used throughout the
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code, including when zero-padding the destination string. However, the
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v18 reference was mistakenly being used for stxv and stxvl, which take a
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VSX vector as operand. The code ended up using the uninitialized VSR 18
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register by mistake.
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Both occurrences have been changed to use the proper VSX number for VR 18
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(i.e. VSR 50).
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Tested on powerpc, powerpc64 and powerpc64le.
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Signed-off-by: Kewen Lin <linkw@gcc.gnu.org>
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2022-11-15 07:04:49 +00:00
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(cherry picked from commit 0218463dd8265ed937622f88ac68c7d984fe0cfc)
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2022-09-20 11:49:23 +00:00
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diff --git a/sysdeps/powerpc/powerpc64/le/power9/strncpy.S b/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
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index 291941c1e5c0eb4b..5421525acee3ebfe 100644
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--- a/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
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+++ b/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
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@@ -352,7 +352,7 @@ L(zero_padding_loop):
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cmpldi cr6,r5,16 /* Check if length was reached. */
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ble cr6,L(zero_padding_end)
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- stxv v18,0(r11)
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+ stxv 32+v18,0(r11)
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addi r11,r11,16
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addi r5,r5,-16
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@@ -360,7 +360,7 @@ L(zero_padding_loop):
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L(zero_padding_end):
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sldi r10,r5,56 /* stxvl wants size in top 8 bits */
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- stxvl v18,r11,r10 /* Partial store */
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+ stxvl 32+v18,r11,r10 /* Partial store */
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blr
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.align 4
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