35 lines
1.4 KiB
Diff
35 lines
1.4 KiB
Diff
From 957f778cb971d63cbbea0c71c727c94474b1b905 Mon Sep 17 00:00:00 2001
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From: Karel Gardas <karel.gardas@centrum.cz>
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Date: Tue, 14 Feb 2012 08:01:47 +0100
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Subject: [PATCH 1/2] fix ARM's StgCRun clobbered register list for both ARM and Thumb modes
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---
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rts/StgCRun.c | 16 +++++++++++++++-
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1 files changed, 15 insertions(+), 1 deletions(-)
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--- a/rts/StgCRun.c
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+++ b/rts/StgCRun.c
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@@ -672,7 +672,21 @@
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"ldmfd sp!, {r4-r11, fp, ip, lr}\n\t"
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: "=r" (r)
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: "r" (f), "r" (basereg), "i" (RESERVED_C_STACK_BYTES)
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- : "%r4", "%r5", "%r6", "%r8", "%r9", "%r10", "%r11", "%fp", "%ip", "%lr"
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+#if !defined(__thumb__)
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+ /* In ARM mode, r11/fp is frame-pointer and so we cannot mark
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+ it as clobbered. If we do so, GCC complains with error. */
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+ : "%r4", "%r5", "%r6", "%r7", "%r8", "%r9", "%r10", "%ip", "%lr"
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+#else
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+ /* In Thumb mode r7 is frame-pointer and so we cannot mark it
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+ as clobbered. On the other hand we mark as clobbered also
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+ those regs not used in Thumb mode. Hard to judge if this is
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+ needed, but certainly Haskell code is using them for
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+ placing GHC's virtual registers there. See
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+ includes/stg/MachRegs.h Please note that Haskell code is
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+ compiled by GHC/LLVM into ARM code (not Thumb!), at least
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+ as of February 2012 */
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+ : "%r4", "%r5", "%r6", "%r8", "%r9", "%r10", "%fp", "%ip", "%lr"
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+#endif
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);
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return r;
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}
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