69 lines
2.7 KiB
Diff
69 lines
2.7 KiB
Diff
Fix:
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FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly dsub
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FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly dmul
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FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly ddiv
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FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly dcmpu
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2007-10-15 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes): Fix the first two operands of
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dquaiq. to use the TE and FRT macros.
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--- ./opcodes/ppc-opc.c 16 Oct 2007 02:26:30 -0000 1.100
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+++ ./opcodes/ppc-opc.c 16 Oct 2007 02:55:30 -0000 1.101
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@@ -4680,7 +4680,7 @@ const struct powerpc_opcode powerpc_opco
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{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
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-{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
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{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
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{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
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2007-10-15 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (TE): Correct signedness.
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(powerpc_opcodes): Sort psq_st and psq_stu according to major
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opcode number.
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--- ./opcodes/ppc-opc.c 24 Aug 2007 00:56:30 -0000 1.99
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+++ ./opcodes/ppc-opc.c 16 Oct 2007 02:26:30 -0000 1.100
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@@ -492,13 +492,13 @@ const struct powerpc_operand powerpc_ope
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#define VS VD
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{ 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
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- /* The SIMM field in a VX form instruction. */
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+ /* The SIMM field in a VX form instruction, and TE in Z form. */
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#define SIMM VD + 1
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+#define TE SIMM
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{ 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
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- /* The UIMM field in a VX form instruction, and TE in Z form. */
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+ /* The UIMM field in a VX form instruction. */
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#define UIMM SIMM + 1
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-#define TE UIMM
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{ 0x1f, 16, NULL, NULL, 0 },
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/* The SHB field in a VA form instruction. */
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@@ -4495,9 +4495,6 @@ const struct powerpc_opcode powerpc_opco
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{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
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{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
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-{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
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-{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
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-
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{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
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{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
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@@ -4561,6 +4558,9 @@ const struct powerpc_opcode powerpc_opco
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{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
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+{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
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+{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
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+
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{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
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{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
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