100 lines
5.6 KiB
Diff
100 lines
5.6 KiB
Diff
From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Jens Remus <jremus@linux.ibm.com>
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Date: Mon, 28 Apr 2025 11:23:21 -0700
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Subject: gdb-rhel-86801-binutils-z17-update-2of12.patch
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;; Backkport "s390: Align optional operand definition to specs"
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;; (Jens Remus, RHEL-86801)
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The IBM z/Architecture Principle of Operation [1] specifies the last
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operand(s) of some (extended) mnemonics to be optional. Align the
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mnemonic definitions in the opcode table according to specification.
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This changes the last operand of the following (extended) mnemonics to
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be optional:
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risbg, risbgz, risbgn, risbgnz, risbhg, risblg, rnsbg, rosbg, rxsbg
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Note that efpc and sfpc actually have only one operand, but had
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erroneously been defined to have two. For backwards compatibility the
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wrong RR register format must be retained. Since the superfluous second
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operand is defined as optional the instruction can still be coded as
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specified.
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[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
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https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
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opcodes/
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* s390-opc.txt: Align optional operand definition to
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specification.
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testsuite/
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* zarch-z10.s: Add test cases for risbg, risbgz, rnsbg, rosbg,
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and rxsbg.
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* zarch-z10.d: Likewise.
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* zarch-z196.s: Add test cases for risbhg and risblg.
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* zarch-z196.d: Likewise.
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* zarch-zEC12.s: Add test cases for risbgn and risbgnz.
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* zarch-zEC12.d: Likewise.
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Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
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diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
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--- a/opcodes/s390-opc.txt
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+++ b/opcodes/s390-opc.txt
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@@ -305,6 +305,7 @@ b30d debr RRE_FF "divide short bfp" g5 esa,zarch
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ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch
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b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch
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b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch
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+# efpc and sfpc have only one operand; retain RR register format for compatibility
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b38c efpc RRE_RR "extract fpc" g5 esa,zarch optparm
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b342 ltxbr RRE_FEFE "load and test extended bfp" g5 esa,zarch
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b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch
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@@ -348,6 +349,7 @@ b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch
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ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch
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b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch
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ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch
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+# efpc and sfpc have only one operand; retain RR register format for compatibility
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b384 sfpc RRE_RR "set fpc" g5 esa,zarch optparm
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b299 srnm S_RD "set rounding mode" g5 esa,zarch
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b316 sqxbr RRE_FEFE "square root extended bfp" g5 esa,zarch
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@@ -966,11 +968,11 @@ c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch
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c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch
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e30000000036 pfd RXY_URRD "prefetch data" z10 zarch
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c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch
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-ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
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-ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
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-ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
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-ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
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-ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch
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+ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch optparm
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+ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch optparm
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+ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch optparm
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+ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch optparm
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+ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch optparm
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c40f strl RIL_RP "store relative long (32)" z10 zarch
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c40b stgrl RIL_RP "store relative long (64)" z10 zarch
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c407 sthrl RIL_RP "store halfword relative long" z10 zarch
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@@ -1014,8 +1016,8 @@ e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch
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e300000000ca lfh RXY_RRRD "load high" z196 zarch
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e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch
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e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch
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-ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch
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-ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch
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+ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch optparm
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+ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch optparm
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e300000000c3 stch RXY_RRRD "store character high" z196 zarch
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e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch
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e300000000cb stfh RXY_RRRD "store high" z196 zarch
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@@ -1153,8 +1155,8 @@ eb0000000023 clt RSY_RURD "compare logical and trap 32 bit reg-mem" zEC12 zarch
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eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zarch
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eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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-ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
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-ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch
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+ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch optparm
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+ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch optparm
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ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
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ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
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ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch
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