diff --git a/.gitignore b/.gitignore index 57c00b4..6820356 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,3 @@ -/new-fedora-release /gdb-libstdc++-v3-python-8.1.1-20180626.tar.xz /v2.0.5.tar.gz -/gdb-14.1.tar.xz +/gdb-14.2.tar.xz diff --git a/README.local-patches.md b/README.local-patches.md deleted file mode 100644 index fc2eb90..0000000 --- a/README.local-patches.md +++ /dev/null @@ -1,104 +0,0 @@ -# Fedora GDB local patches policy - -In order to make things easier for the Fedora GDB maintainer, we -choose to auto-generate the local patches by making use of an upstream -git repository. Below you can find a few instructions on how to work -using this method. - -You need to run the following commands from the directory that -contains the "gdb.spec" file. - -## Importing the GDB patches into a git repository - -1) The local patches (`*.patch`) need to be imported into an upstream -git repository. For example, let's assume you cloned the repository -by doing: - -`$ git clone git://sourceware.org/git/binutils-gdb.git` - -> TIP: if you already have the repository cloned somewhere in your -> system, you can pass a "--reference " to the "git clone" -> command and it will use your local repository as much as possible -> to make the clone, speeding up things. - -2) After cloning the upstream repository, you can import your patches -by using the script "generate-git-repo-from-patches.sh": - -`$ sh generate-git-repo-from-patches.sh ` - -The script will basically cd into the repository, checkout the -revision specified in the file `_git_upstream_commit`, iterate through -the file `_patch_order` and "git-am" every patch *in that order*. -This operation should complete without errors; if you find a problem -with `git-am`, it probably means that the revision specified in the -file `_git_upstream_commit` is wrong. - -## Rebasing the patches against a newer version/release - -1) First, cd into the upstream repository. All you have to do is -choose the revision against which you plan to rebase the patches, and -`git rebase `. git will do the rest, and you will be able -to perform conflict resolution by git's algorithm, which is smarter. - -## Creating new patches - -1) Create the new patch on top of the the others, as usual. Note that -you can use `git rebase` whenever you want to reorder patch order, or -even to delete a patch. - -2) When writing the commit log, you must obey a few rules. The -subject line *must* be the filename of the patch. This line will be -used when exporting the patches from the git repository, and -(obviously) it gives the filename that should be used for this -specific patch. - -3) You can also add comments that will go into the auto-generated -`Patch:` file (see below). To do that, use the special marker `;;` at -the beginning of the line. This way, a commit log that says: - -~~~~~~~~~~~ - test-patch.patch - - ;; This is a test patch - ;; Second line -~~~~~~~~~~~ - -Will generate the following entry in the auto-generated `Patch:` file: - -~~~~~~~~~~~ - # This is a test patch - # Second line - PatchXYZ: test-patch.patch -~~~~~~~~~~~ - -## Exporting the GDB patches from the git repository - -1) When you're done working with the patches, go back to the directory -that contains the `gdb.spec` file, and from there you run: - -`$ sh generate-patches-from-git-repo.sh ` - -This will regenerate all of the `*.patch` files (excluding the ones that -were also excluded from the git repository), and also regenerate a few -control files. These control files are: - - - `_gdb.spec.Patch.include`: This file contains the `Patch:` directives. - - - `_gdb.spec.patch.include`: This file contains the `%patch` directives. - - - `_patch_order`: This file contains the patches, in the exact order - that they must be applied. It is used when importing the patches - into the git repository. - - - `_git_upstream_commit`: This file contains the last upstream commit - against which the patches were rebased. It is used when importing - the patches into the git repository. - -NOTE: If you did a rebase against a newer upstream version, you need -to specify the commit/tag/branch against which you rebased: - -`$ sh generate-patches-from-git-repo.sh ` - -For example, if you rebased against `gdb-8.1-release`: - -`$ sh generate-patches-from-git-repo.sh gdb-8.1-release` diff --git a/_gdb.spec.Patch.include b/_gdb.spec.Patch.include index e4aaebc..f1c921d 100644 --- a/_gdb.spec.Patch.include +++ b/_gdb.spec.Patch.include @@ -189,16 +189,45 @@ Patch043: gdb-rhbz2250652-gdbpy_gil.patch Patch044: gdb-rhbz2250652-avoid-PyOS_ReadlineTState.patch -# Backport potential fix for RH BZ 2257562. -Patch045: gdb-rhbz2257562-cp-namespace-null-ptr-check.patch - -Patch046: gdb-ftbs-swapped-calloc-args.patch - -# Backport gdb: fix "list ." related crash -Patch047: gdb-rhbz2259850-list-period-crash-fix.patch +Patch045: gdb-ftbs-swapped-calloc-args.patch # Backport upstream workaround for GCC 14 problem which cause assertion # failures in GDB. -Patch048: gdb-rhbz2261580-intrusive_list-assertion-fix.patch +Patch046: gdb-rhbz2261580-intrusive_list-assertion-fix.patch + +# Backport "gdb: s390: Add arch14 record/replay support" +# (Andreas Arnez, RHEL-36225) +Patch047: gdb-rhel-36225-add-arch14-record.patch + +# Backport "PowerPC: Add support for Power11 options" +# (Peter Bergner, RHEL-36518) +Patch048: gdb-rhel-36518-add-power11-support.patch + +# Update x86 disassembler +Patch049: gdb-rhel-36527-apx-disasm.patch + +#Revert "gdb: remove unnecessary parameter wait_ptid from do_target_wait" +#(Andrew Burgess, RHEL-13298) +Patch050: gdb-rhel-13298-inferior-funcall-bp-condition-1-of-5.patch + +#gdb: fix b/p conditions with infcalls in multi-threaded inferiors +#(Andrew Burgess, RHEL-13298) +Patch051: gdb-rhel-13298-inferior-funcall-bp-condition-2-of-5.patch + +#gdb: add timeouts for inferior function calls +#(Andrew Burgess, RHEL-13298) +Patch052: gdb-rhel-13298-inferior-funcall-bp-condition-3-of-5.patch + +#gdb: introduce unwind-on-timeout setting +#(Andrew Burgess, RHEL-13298) +Patch053: gdb-rhel-13298-inferior-funcall-bp-condition-4-of-5.patch + +#gdb: rename unwindonsignal to unwind-on-signal +#(Andrew Burgess, RHEL-13298) +Patch054: gdb-rhel-13298-inferior-funcall-bp-condition-5-of-5.patch + +#gdb/unwinders: better support for $pc not saved +#(Andrew Burgess, RHEL-19390) +Patch055: gdb-rhel-19390-pc-not-saved.patch diff --git a/_gdb.spec.patch.include b/_gdb.spec.patch.include index ef55dd0..b72c412 100644 --- a/_gdb.spec.patch.include +++ b/_gdb.spec.patch.include @@ -46,3 +46,10 @@ %patch -p1 -P046 %patch -p1 -P047 %patch -p1 -P048 +%patch -p1 -P049 +%patch -p1 -P050 +%patch -p1 -P051 +%patch -p1 -P052 +%patch -p1 -P053 +%patch -p1 -P054 +%patch -p1 -P055 diff --git a/_git_upstream_commit b/_git_upstream_commit index 3d8eec6..b70cde9 100644 --- a/_git_upstream_commit +++ b/_git_upstream_commit @@ -1 +1 @@ -6bda1c19bcd16eff8488facb8a67d52a436f70e7 +02c10eaecb63e5dbb99cbfdd1c5385e53ed031ff diff --git a/_patch_order b/_patch_order index aadb6e3..fc8f938 100644 --- a/_patch_order +++ b/_patch_order @@ -42,7 +42,14 @@ gdb-rhbz-2232086-generate-gdb-index-consistently.patch gdb-rhbz-2232086-generate-dwarf-5-index-consistently.patch gdb-rhbz2250652-gdbpy_gil.patch gdb-rhbz2250652-avoid-PyOS_ReadlineTState.patch -gdb-rhbz2257562-cp-namespace-null-ptr-check.patch gdb-ftbs-swapped-calloc-args.patch -gdb-rhbz2259850-list-period-crash-fix.patch gdb-rhbz2261580-intrusive_list-assertion-fix.patch +gdb-rhel-36225-add-arch14-record.patch +gdb-rhel-36518-add-power11-support.patch +gdb-rhel-36527-apx-disasm.patch +gdb-rhel-13298-inferior-funcall-bp-condition-1-of-5.patch +gdb-rhel-13298-inferior-funcall-bp-condition-2-of-5.patch +gdb-rhel-13298-inferior-funcall-bp-condition-3-of-5.patch +gdb-rhel-13298-inferior-funcall-bp-condition-4-of-5.patch +gdb-rhel-13298-inferior-funcall-bp-condition-5-of-5.patch +gdb-rhel-19390-pc-not-saved.patch diff --git a/gdb-rhbz2042664-fix-sect_index_data-internal-error b/gdb-rhbz2042664-fix-sect_index_data-internal-error deleted file mode 100644 index 0a2a459..0000000 --- a/gdb-rhbz2042664-fix-sect_index_data-internal-error +++ /dev/null @@ -1,128 +0,0 @@ -From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 -From: Kevin Buettner -Date: Tue, 1 Feb 2022 11:32:48 -0700 -Subject: gdb-rhbz2042664-fix-sect_index_data-internal-error - -;; Backport fix which fixes internal error due to libcc_s lacking a -;; .data section. - -Fix GDB internal error by using text (instead of data) section offset - -Fedora Rawhide is now using gcc-12.0. As part of updating to the -gcc-12.0 package set, Rawhide is also now using a version of libgcc_s -which lacks a .data section. This causes gdb to fail in the following -fashion while debugging a program (such as gdb) which uses libgcc_s: - - (top-gdb) run - Starting program: rawhide-master/bld/gdb/gdb - ... - objfiles.h:467: internal-error: sect_index_data not initialized - A problem internal to GDB has been detected, - further debugging may prove unreliable. - ... - -I snipped the backtrace from the above output. Instead, here's a -portion of a backtrace obtained using GDB's backtrace command. -(Obviously, in order to obtain it, I used a GDB which has been patched -with this commit.) - - #0 internal_error ( - file=0xc6a508 "gdb/objfiles.h", line=467, - fmt=0xc6a4e8 "sect_index_data not initialized") - at gdbsupport/errors.cc:51 - #1 0x00000000005f9651 in objfile::data_section_offset (this=0x4fa48f0) - at gdb/objfiles.h:467 - #2 0x000000000097c5f8 in relocate_address (address=0x17244, objfile=0x4fa48f0) - at gdb/stap-probe.c:1333 - #3 0x000000000097c630 in stap_probe::get_relocated_address (this=0xa1a17a0, - objfile=0x4fa48f0) - at gdb/stap-probe.c:1341 - #4 0x00000000004d7025 in create_exception_master_breakpoint_probe ( - objfile=0x4fa48f0) - at gdb/breakpoint.c:3505 - #5 0x00000000004d7426 in create_exception_master_breakpoint () - at gdb/breakpoint.c:3575 - #6 0x00000000004efcc1 in breakpoint_re_set () - at gdb/breakpoint.c:13407 - #7 0x0000000000956998 in solib_add (pattern=0x0, from_tty=0, readsyms=1) - at gdb/solib.c:1001 - #8 0x00000000009576a8 in handle_solib_event () - at gdb/solib.c:1269 - ... - -The function 'relocate_address' in gdb/stap-probe.c attempts to do -its "relocation" by using objfile->data_section_offset(). That -method, data_section_offset() is defined as follows in objfiles.h: - - CORE_ADDR data_section_offset () const - { - return section_offsets[SECT_OFF_DATA (this)]; - } - -The internal error occurs when the SECT_OFF_DATA macro finds that the -'sect_index_data' field is -1: - - #define SECT_OFF_DATA(objfile) \ - ((objfile->sect_index_data == -1) \ - ? (internal_error (__FILE__, __LINE__, \ - _("sect_index_data not initialized")), -1) \ - : objfile->sect_index_data) - -relocate_address() is obtaining the section offset in order to compute -a relocated address. For some ABIs, such as the System V ABI, the -section offsets will all be the same. So for those ABIs, it doesn't -matter which offset is used. However, other ABIs, such as the FDPIC -ABI, will have different offsets for the various sections. Thus, for -those ABIs, it is vital that this and other relocation code use the -correct offset. - -In stap_probe::get_relocated_address, the address to which to add the -offset (thus forming the relocated address) is obtained via -this->get_address (); get_address is a getter for m_address in -probe.h. It's documented/defined as follows (also in probe.h): - - /* The address where the probe is inserted, relative to - SECT_OFF_TEXT. */ - CORE_ADDR m_address; - -(Thanks to Tom Tromey for this observation.) - -So, based on this, the current use of data_section_offset / -SECT_OFF_DATA is wrong. This relocation code should have been using -text_section_offset / SECT_OFF_TEXT all along. That being the -case, I've adjusted the stap-probe.c relocation code accordingly. - -Searching the sources turned up one other use of data_section_offset, -in gdb/dtrace-probe.c, so I've updated that code as well. The same -reasoning presented above applies to this case too. - -Summary: - - * gdb/dtrace-probe.c (dtrace_probe::get_relocated_address): - Use method text_section_offset instead of data_section_offset. - * gdb/stap-probe.c (relocate_address): Likewise. - -diff --git a/gdb/dtrace-probe.c b/gdb/dtrace-probe.c ---- a/gdb/dtrace-probe.c -+++ b/gdb/dtrace-probe.c -@@ -684,7 +684,7 @@ dtrace_probe::is_enabled () const - CORE_ADDR - dtrace_probe::get_relocated_address (struct objfile *objfile) - { -- return this->get_address () + objfile->data_section_offset (); -+ return this->get_address () + objfile->text_section_offset (); - } - - /* Implementation of the get_argument_count method. */ -diff --git a/gdb/stap-probe.c b/gdb/stap-probe.c ---- a/gdb/stap-probe.c -+++ b/gdb/stap-probe.c -@@ -1330,7 +1330,7 @@ stap_probe::parse_arguments (struct gdbarch *gdbarch) - static CORE_ADDR - relocate_address (CORE_ADDR address, struct objfile *objfile) - { -- return address + objfile->data_section_offset (); -+ return address + objfile->text_section_offset (); - } - - /* Implementation of the get_relocated_address method. */ diff --git a/gdb-rhbz2257562-cp-namespace-null-ptr-check.patch b/gdb-rhbz2257562-cp-namespace-null-ptr-check.patch deleted file mode 100644 index f868e6f..0000000 --- a/gdb-rhbz2257562-cp-namespace-null-ptr-check.patch +++ /dev/null @@ -1,113 +0,0 @@ -From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 -From: Kevin Buettner -Date: Tue, 16 Jan 2024 20:07:53 -0700 -Subject: gdb-rhbz2257562-cp-namespace-null-ptr-check.patch - -;; Backport potential fix for RH BZ 2257562. - -Fix printing of global variable stubs if no inferior is running - -Since 3c45e9f915ae4aeab7312d6fc55a947859057572 gdb crashes when trying -to print a global variable stub without a running inferior, because of -a missing nullptr-check (the block_scope function took care of that -check before it was converted to a method). - -With this check it works again: -``` -(gdb) print s -$1 = -``` - -Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31128 -Approved-By: Tom Tromey -(cherry picked from commit 576745e26c0ec76a53ba45b20af464628a50b3e4) - -diff --git a/gdb/cp-namespace.c b/gdb/cp-namespace.c ---- a/gdb/cp-namespace.c -+++ b/gdb/cp-namespace.c -@@ -1026,7 +1026,11 @@ cp_lookup_transparent_type (const char *name) - - /* If that doesn't work and we're within a namespace, look there - instead. */ -- scope = get_selected_block (0)->scope (); -+ const block *block = get_selected_block (0); -+ if (block == nullptr) -+ return nullptr; -+ -+ scope = block->scope (); - - if (scope[0] == '\0') - return NULL; -diff --git a/gdb/testsuite/gdb.cp/print-global-stub.cc b/gdb/testsuite/gdb.cp/print-global-stub.cc -new file mode 100644 ---- /dev/null -+++ b/gdb/testsuite/gdb.cp/print-global-stub.cc -@@ -0,0 +1,31 @@ -+/* This testcase is part of GDB, the GNU debugger. -+ -+ Copyright 2023 Free Software Foundation, Inc. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program. If not, see . */ -+ -+struct S -+{ -+ S (int); -+ virtual ~S (); -+ -+ int m_i; -+}; -+ -+S s (5); -+ -+int main () -+{ -+ return 0; -+} -diff --git a/gdb/testsuite/gdb.cp/print-global-stub.exp b/gdb/testsuite/gdb.cp/print-global-stub.exp -new file mode 100644 ---- /dev/null -+++ b/gdb/testsuite/gdb.cp/print-global-stub.exp -@@ -0,0 +1,32 @@ -+# Copyright (C) 2023 Free Software Foundation, Inc. -+ -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3 of the License, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program. If not, see . -+ -+# This file is part of the GDB testsuite. -+# It tests printing of a global stub without inferior. -+ -+require allow_cplus_tests -+ -+standard_testfile .cc -+set objfile [standard_output_file ${testfile}.o] -+ -+if { [gdb_compile $srcdir/$subdir/$srcfile $objfile object \ -+ {c++ debug}] != "" } { -+ untested "failed to compile" -+ return -1 -+} -+ -+clean_restart $objfile -+ -+gdb_test "print s" " = " diff --git a/gdb-rhbz2259850-list-period-crash-fix.patch b/gdb-rhbz2259850-list-period-crash-fix.patch deleted file mode 100644 index 0606e66..0000000 --- a/gdb-rhbz2259850-list-period-crash-fix.patch +++ /dev/null @@ -1,101 +0,0 @@ -From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 -From: Guinevere Larsen -Date: Mon, 22 Jan 2024 10:13:52 +0100 -Subject: gdb-rhbz2259850-list-period-crash-fix.patch - -;; Backport gdb: fix "list ." related crash - -When a user attempts to use the "list ." command with an inferior that -doesn't have debug symbols, GDB would crash. This was reported as PR -gdb/31256. - -The crash would happen when attempting to get the current symtab_and_line -for the stop location, because the symtab would return a null pointer -and we'd attempt to dereference it to print the line. - -This commit fixes that by checking for an empty symtab and erroring out -of the function if it happens. - -Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31256 -Approved-By: Tom Tromey - -diff --git a/gdb/cli/cli-cmds.c b/gdb/cli/cli-cmds.c ---- a/gdb/cli/cli-cmds.c -+++ b/gdb/cli/cli-cmds.c -@@ -1291,6 +1291,8 @@ list_command (const char *arg, int from_tty) - set_default_source_symtab_and_line (); - cursal = get_current_source_symtab_and_line (); - } -+ if (cursal.symtab == nullptr) -+ error (_("No debug information available to print source lines.")); - list_around_line (arg, cursal); - /* Set the repeat args so just pressing "enter" after using "list ." - will print the following lines instead of the same lines again. */ -diff --git a/gdb/testsuite/gdb.base/list-nodebug.c b/gdb/testsuite/gdb.base/list-nodebug.c -new file mode 100644 ---- /dev/null -+++ b/gdb/testsuite/gdb.base/list-nodebug.c -@@ -0,0 +1,21 @@ -+/* This testcase is part of GDB, the GNU debugger. -+ -+ Copyright 2024 Free Software Foundation, Inc. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program. If not, see . */ -+ -+int main () -+{ -+ return 0; -+} -diff --git a/gdb/testsuite/gdb.base/list-nodebug.exp b/gdb/testsuite/gdb.base/list-nodebug.exp -new file mode 100644 ---- /dev/null -+++ b/gdb/testsuite/gdb.base/list-nodebug.exp -@@ -0,0 +1,37 @@ -+# Copyright 2024 Free Software Foundation, Inc. -+ -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3 of the License, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program. If not, see . -+ -+# Test that using the command "list" in a file with no debug information -+# will not crash GDB and will give reasonable output. -+ -+standard_testfile .c -+ -+if {[prepare_for_testing "failed to prepare" ${testfile} ${srcfile} \ -+ {nodebug}]} { -+ return -1 -+} -+ -+if {![runto_main]} { -+ untested "couldn't run to main" -+ return -+} -+ -+# Check that GDB doesn't crash when we use list . on an inferior with -+# no debug information -+gdb_test "list ." "No debug.*" "first 'list .'" -+# This should be called twice because the first list invocation since -+# printing a frame may take a different codepath, which wouldn't -+# trigger the crash. -+gdb_test "list ." "No debug.*" "second 'list .'" diff --git a/gdb-rhel-13298-inferior-funcall-bp-condition-1-of-5.patch b/gdb-rhel-13298-inferior-funcall-bp-condition-1-of-5.patch new file mode 100644 index 0000000..fbecc59 --- /dev/null +++ b/gdb-rhel-13298-inferior-funcall-bp-condition-1-of-5.patch @@ -0,0 +1,70 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andrew Burgess +Date: Mon, 9 May 2022 17:51:54 +0100 +Subject: gdb-rhel-13298-inferior-funcall-bp-condition-1-of-5.patch + +;;Revert "gdb: remove unnecessary parameter wait_ptid from do_target_wait" +;;(Andrew Burgess, RHEL-13298) + +This reverts commit ac0d67ed1dcf470bad6a3bc4800c2ddc9bedecca. + +There was nothing wrong with the commit which I'm reverting here, but +it removed some functionality that will be needed for a later commit; +that is, the ability for GDB to ask for events from a specific ptid_t +via the do_target_wait function. + +In a follow up commit, this functionality will be used to implement +inferior function calls in multi-threaded inferiors. + +This is not a straight revert of the above commit. Reverting the +above commit replaces a 'nullptr' with 'NULL', I've gone in and +changed that, preserving the 'nullptr'. + +Reviewed-By: Tankut Baris Aktemur +Tested-By: Luis Machado +Tested-By: Keith Seitz + +diff --git a/gdb/infrun.c b/gdb/infrun.c +--- a/gdb/infrun.c ++++ b/gdb/infrun.c +@@ -3946,7 +3946,8 @@ do_target_wait_1 (inferior *inf, ptid_t ptid, + more events. Polls for events from all inferiors/targets. */ + + static bool +-do_target_wait (execution_control_state *ecs, target_wait_flags options) ++do_target_wait (ptid_t wait_ptid, execution_control_state *ecs, ++ target_wait_flags options) + { + int num_inferiors = 0; + int random_selector; +@@ -3956,9 +3957,10 @@ do_target_wait (execution_control_state *ecs, target_wait_flags options) + polling the rest of the inferior list starting from that one in a + circular fashion until the whole list is polled once. */ + +- auto inferior_matches = [] (inferior *inf) ++ auto inferior_matches = [&wait_ptid] (inferior *inf) + { +- return inf->process_target () != nullptr; ++ return (inf->process_target () != nullptr ++ && ptid_t (inf->pid).matches (wait_ptid)); + }; + + /* First see how many matching inferiors we have. */ +@@ -3997,7 +3999,7 @@ do_target_wait (execution_control_state *ecs, target_wait_flags options) + + auto do_wait = [&] (inferior *inf) + { +- ecs->ptid = do_target_wait_1 (inf, minus_one_ptid, &ecs->ws, options); ++ ecs->ptid = do_target_wait_1 (inf, wait_ptid, &ecs->ws, options); + ecs->target = inf->process_target (); + return (ecs->ws.kind () != TARGET_WAITKIND_IGNORE); + }; +@@ -4427,7 +4429,7 @@ fetch_inferior_event () + the event. */ + scoped_disable_commit_resumed disable_commit_resumed ("handling event"); + +- if (!do_target_wait (&ecs, TARGET_WNOHANG)) ++ if (!do_target_wait (minus_one_ptid, &ecs, TARGET_WNOHANG)) + { + infrun_debug_printf ("do_target_wait returned no event"); + disable_commit_resumed.reset_and_commit (); diff --git a/gdb-rhel-13298-inferior-funcall-bp-condition-2-of-5.patch b/gdb-rhel-13298-inferior-funcall-bp-condition-2-of-5.patch new file mode 100644 index 0000000..f582130 --- /dev/null +++ b/gdb-rhel-13298-inferior-funcall-bp-condition-2-of-5.patch @@ -0,0 +1,1274 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andrew Burgess +Date: Fri, 9 Oct 2020 13:27:13 +0200 +Subject: gdb-rhel-13298-inferior-funcall-bp-condition-2-of-5.patch + +;;gdb: fix b/p conditions with infcalls in multi-threaded inferiors +;;(Andrew Burgess, RHEL-13298) + +This commit fixes bug PR 28942, that is, creating a conditional +breakpoint in a multi-threaded inferior, where the breakpoint +condition includes an inferior function call. + +Currently, when a user tries to create such a breakpoint, then GDB +will fail with: + + (gdb) break infcall-from-bp-cond-single.c:61 if (return_true ()) + Breakpoint 2 at 0x4011fa: file /tmp/build/gdb/testsuite/../../../src/gdb/testsuite/gdb.threads/infcall-from-bp-cond-single.c, line 61. + (gdb) continue + Continuing. + [New Thread 0x7ffff7c5d700 (LWP 2460150)] + [New Thread 0x7ffff745c700 (LWP 2460151)] + [New Thread 0x7ffff6c5b700 (LWP 2460152)] + [New Thread 0x7ffff645a700 (LWP 2460153)] + [New Thread 0x7ffff5c59700 (LWP 2460154)] + Error in testing breakpoint condition: + Couldn't get registers: No such process. + An error occurred while in a function called from GDB. + Evaluation of the expression containing the function + (return_true) will be abandoned. + When the function is done executing, GDB will silently stop. + Selected thread is running. + (gdb) + +Or, in some cases, like this: + + (gdb) break infcall-from-bp-cond-simple.c:56 if (is_matching_tid (arg, 1)) + Breakpoint 2 at 0x401194: file /tmp/build/gdb/testsuite/../../../src/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.c, line 56. + (gdb) continue + Continuing. + [New Thread 0x7ffff7c5d700 (LWP 2461106)] + [New Thread 0x7ffff745c700 (LWP 2461107)] + ../../src.release/gdb/nat/x86-linux-dregs.c:146: internal-error: x86_linux_update_debug_registers: Assertion `lwp_is_stopped (lwp)' failed. + A problem internal to GDB has been detected, + further debugging may prove unreliable. + +The precise error depends on the exact thread state; so there's race +conditions depending on which threads have fully started, and which +have not. But the underlying problem is always the same; when GDB +tries to execute the inferior function call from within the breakpoint +condition, GDB will, incorrectly, try to resume threads that are +already running - GDB doesn't realise that some threads might already +be running. + +The solution proposed in this patch requires an additional member +variable thread_info::in_cond_eval. This flag is set to true (in +breakpoint.c) when GDB is evaluating a breakpoint condition. + +In user_visible_resume_ptid (infrun.c), when the in_cond_eval flag is +true, then GDB will only try to resume the current thread, that is, +the thread for which the breakpoint condition is being evaluated. +This solves the problem of GDB trying to resume threads that are +already running. + +The next problem is that inferior function calls are assumed to be +synchronous, that is, GDB doesn't expect to start an inferior function +call in thread #1, then receive a stop from thread #2 for some other, +unrelated reason. To prevent GDB responding to an event from another +thread, we update fetch_inferior_event and do_target_wait in infrun.c, +so that, when an inferior function call (on behalf of a breakpoint +condition) is in progress, we only wait for events from the current +thread (the one evaluating the condition). + +In do_target_wait I had to change the inferior_matches lambda +function, which is used to select which inferior to wait on. +Previously the logic was this: + + auto inferior_matches = [&wait_ptid] (inferior *inf) + { + return (inf->process_target () != nullptr + && ptid_t (inf->pid).matches (wait_ptid)); + }; + +This compares the pid of the inferior against the complete ptid we +want to wait on. Before this commit wait_ptid was only ever +minus_one_ptid (which is special, and means any process), and so every +inferior would match. + +After this commit though wait_ptid might represent a specific thread +in a specific inferior. If we compare the pid of the inferior to a +specific ptid then these will not match. The fix is to compare +against the pid extracted from the wait_ptid, not against the complete +wait_ptid itself. + +In fetch_inferior_event, after receiving the event, we only want to +stop all the other threads, and call inferior_event_handler with +INF_EXEC_COMPLETE, if we are not evaluating a conditional breakpoint. +If we are, then all the other threads should be left doing whatever +they were before. The inferior_event_handler call will be performed +once the breakpoint condition has finished being evaluated, and GDB +decides to stop or not. + +The final problem that needs solving relates to GDB's commit-resume +mechanism, which allows GDB to collect resume requests into a single +packet in order to reduce traffic to a remote target. + +The problem is that the commit-resume mechanism will not send any +resume requests for an inferior if there are already events pending on +the GDB side. + +Imagine an inferior with two threads. Both threads hit a breakpoint, +maybe the same conditional breakpoint. At this point there are two +pending events, one for each thread. + +GDB selects one of the events and spots that this is a conditional +breakpoint, GDB evaluates the condition. + +The condition includes an inferior function call, so GDB sets up for +the call and resumes the one thread, the resume request is added to +the commit-resume queue. + +When the commit-resume queue is committed GDB sees that there is a +pending event from another thread, and so doesn't send any resume +requests to the actual target, GDB is assuming that when we wait we +will select the event from the other thread. + +However, as this is an inferior function call for a condition +evaluation, we will not select the event from the other thread, we +only care about events from the thread that is evaluating the +condition - and the resume for this thread was never sent to the +target. + +And so, GDB hangs, waiting for an event from a thread that was never +fully resumed. + +To fix this issue I have added the concept of "forcing" the +commit-resume queue. When enabling commit resume, if the force flag +is true, then any resumes will be committed to the target, even if +there are other threads with pending events. + +A note on authorship: this patch was based on some work done by +Natalia Saiapova and Tankut Baris Aktemur from Intel[1]. I have made +some changes to their work in this version. + +Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28942 + +[1] https://sourceware.org/pipermail/gdb-patches/2020-October/172454.html + +Co-authored-by: Natalia Saiapova +Co-authored-by: Tankut Baris Aktemur +Reviewed-By: Tankut Baris Aktemur +Tested-By: Luis Machado +Tested-By: Keith Seitz + +diff --git a/gdb/breakpoint.c b/gdb/breakpoint.c +--- a/gdb/breakpoint.c ++++ b/gdb/breakpoint.c +@@ -5679,6 +5679,8 @@ bpstat_check_breakpoint_conditions (bpstat *bs, thread_info *thread) + { + try + { ++ scoped_restore reset_in_cond_eval ++ = make_scoped_restore (&thread->control.in_cond_eval, true); + condition_result = breakpoint_cond_eval (cond); + } + catch (const gdb_exception_error &ex) +diff --git a/gdb/gdbthread.h b/gdb/gdbthread.h +--- a/gdb/gdbthread.h ++++ b/gdb/gdbthread.h +@@ -171,6 +171,9 @@ struct thread_control_state + command. This is used to decide whether "set scheduler-locking + step" behaves like "on" or "off". */ + int stepping_command = 0; ++ ++ /* True if the thread is evaluating a BP condition. */ ++ bool in_cond_eval = false; + }; + + /* Inferior thread specific part of `struct infcall_suspend_state'. */ +diff --git a/gdb/infcall.c b/gdb/infcall.c +--- a/gdb/infcall.c ++++ b/gdb/infcall.c +@@ -672,6 +672,12 @@ run_inferior_call (std::unique_ptr sm, + + proceed (real_pc, GDB_SIGNAL_0); + ++ /* Enable commit resume, but pass true for the force flag. This ++ ensures any thread we set running in proceed will actually be ++ committed to the target, even if some other thread in the current ++ target has a pending event. */ ++ scoped_enable_commit_resumed enable ("infcall", true); ++ + infrun_debug_show_threads ("non-exited threads after proceed for inferior-call", + all_non_exited_threads ()); + +diff --git a/gdb/infrun.c b/gdb/infrun.c +--- a/gdb/infrun.c ++++ b/gdb/infrun.c +@@ -2292,6 +2292,14 @@ user_visible_resume_ptid (int step) + mode. */ + resume_ptid = inferior_ptid; + } ++ else if (inferior_ptid != null_ptid ++ && inferior_thread ()->control.in_cond_eval) ++ { ++ /* The inferior thread is evaluating a BP condition. Other threads ++ might be stopped or running and we do not want to change their ++ state, thus, resume only the current thread. */ ++ resume_ptid = inferior_ptid; ++ } + else if (!sched_multi && target_supports_multi_process ()) + { + /* Resume all threads of the current process (and none of other +@@ -3020,12 +3028,24 @@ schedlock_applies (struct thread_info *tp) + execution_direction))); + } + +-/* Set process_stratum_target::COMMIT_RESUMED_STATE in all target +- stacks that have threads executing and don't have threads with +- pending events. */ ++/* When FORCE_P is false, set process_stratum_target::COMMIT_RESUMED_STATE ++ in all target stacks that have threads executing and don't have threads ++ with pending events. ++ ++ When FORCE_P is true, set process_stratum_target::COMMIT_RESUMED_STATE ++ in all target stacks that have threads executing regardless of whether ++ there are pending events or not. ++ ++ Passing FORCE_P as false makes sense when GDB is going to wait for ++ events from all threads and will therefore spot the pending events. ++ However, if GDB is only going to wait for events from select threads ++ (i.e. when performing an inferior call) then a pending event on some ++ other thread will not be spotted, and if we fail to commit the resume ++ state for the thread performing the inferior call, then the inferior ++ call will never complete (or even start). */ + + static void +-maybe_set_commit_resumed_all_targets () ++maybe_set_commit_resumed_all_targets (bool force_p) + { + scoped_restore_current_thread restore_thread; + +@@ -3054,7 +3074,7 @@ maybe_set_commit_resumed_all_targets () + status to report, handle it before requiring the target to + commit its resumed threads: handling the status might lead to + resuming more threads. */ +- if (proc_target->has_resumed_with_pending_wait_status ()) ++ if (!force_p && proc_target->has_resumed_with_pending_wait_status ()) + { + infrun_debug_printf ("not requesting commit-resumed for target %s, a" + " thread has a pending waitstatus", +@@ -3064,7 +3084,7 @@ maybe_set_commit_resumed_all_targets () + + switch_to_inferior_no_thread (inf); + +- if (target_has_pending_events ()) ++ if (!force_p && target_has_pending_events ()) + { + infrun_debug_printf ("not requesting commit-resumed for target %s, " + "target has pending events", +@@ -3157,7 +3177,7 @@ scoped_disable_commit_resumed::reset () + { + /* This is the outermost instance, re-enable + COMMIT_RESUMED_STATE on the targets where it's possible. */ +- maybe_set_commit_resumed_all_targets (); ++ maybe_set_commit_resumed_all_targets (false); + } + else + { +@@ -3190,7 +3210,7 @@ scoped_disable_commit_resumed::reset_and_commit () + /* See infrun.h. */ + + scoped_enable_commit_resumed::scoped_enable_commit_resumed +- (const char *reason) ++ (const char *reason, bool force_p) + : m_reason (reason), + m_prev_enable_commit_resumed (enable_commit_resumed) + { +@@ -3202,7 +3222,7 @@ scoped_enable_commit_resumed::scoped_enable_commit_resumed + + /* Re-enable COMMIT_RESUMED_STATE on the targets where it's + possible. */ +- maybe_set_commit_resumed_all_targets (); ++ maybe_set_commit_resumed_all_targets (force_p); + + maybe_call_commit_resumed_all_targets (); + } +@@ -3957,10 +3977,11 @@ do_target_wait (ptid_t wait_ptid, execution_control_state *ecs, + polling the rest of the inferior list starting from that one in a + circular fashion until the whole list is polled once. */ + +- auto inferior_matches = [&wait_ptid] (inferior *inf) ++ ptid_t wait_ptid_pid {wait_ptid.pid ()}; ++ auto inferior_matches = [&wait_ptid_pid] (inferior *inf) + { + return (inf->process_target () != nullptr +- && ptid_t (inf->pid).matches (wait_ptid)); ++ && ptid_t (inf->pid).matches (wait_ptid_pid)); + }; + + /* First see how many matching inferiors we have. */ +@@ -4429,7 +4450,17 @@ fetch_inferior_event () + the event. */ + scoped_disable_commit_resumed disable_commit_resumed ("handling event"); + +- if (!do_target_wait (minus_one_ptid, &ecs, TARGET_WNOHANG)) ++ /* Is the current thread performing an inferior function call as part ++ of a breakpoint condition evaluation? */ ++ bool in_cond_eval = (inferior_ptid != null_ptid ++ && inferior_thread ()->control.in_cond_eval); ++ ++ /* If the thread is in the middle of the condition evaluation, wait for ++ an event from the current thread. Otherwise, wait for an event from ++ any thread. */ ++ ptid_t waiton_ptid = in_cond_eval ? inferior_ptid : minus_one_ptid; ++ ++ if (!do_target_wait (waiton_ptid, &ecs, TARGET_WNOHANG)) + { + infrun_debug_printf ("do_target_wait returned no event"); + disable_commit_resumed.reset_and_commit (); +@@ -4487,7 +4518,12 @@ fetch_inferior_event () + bool should_notify_stop = true; + bool proceeded = false; + +- stop_all_threads_if_all_stop_mode (); ++ /* If the thread that stopped just completed an inferior ++ function call as part of a condition evaluation, then we ++ don't want to stop all the other threads. */ ++ if (ecs.event_thread == nullptr ++ || !ecs.event_thread->control.in_cond_eval) ++ stop_all_threads_if_all_stop_mode (); + + clean_up_just_stopped_threads_fsms (&ecs); + +@@ -4514,7 +4550,7 @@ fetch_inferior_event () + proceeded = normal_stop (); + } + +- if (!proceeded) ++ if (!proceeded && !in_cond_eval) + { + inferior_event_handler (INF_EXEC_COMPLETE); + cmd_done = 1; +diff --git a/gdb/infrun.h b/gdb/infrun.h +--- a/gdb/infrun.h ++++ b/gdb/infrun.h +@@ -406,7 +406,8 @@ extern void maybe_call_commit_resumed_all_targets (); + + struct scoped_enable_commit_resumed + { +- explicit scoped_enable_commit_resumed (const char *reason); ++ explicit scoped_enable_commit_resumed (const char *reason, ++ bool force_p = false); + ~scoped_enable_commit_resumed (); + + DISABLE_COPY_AND_ASSIGN (scoped_enable_commit_resumed); +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-other-thread-event.c b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-other-thread-event.c +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-other-thread-event.c +@@ -0,0 +1,135 @@ ++/* Copyright 2022-2024 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include ++#include ++#include ++#include ++ ++#define NUM_THREADS 2 ++ ++pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER; ++ ++/* Some global variables to poke, just for something to do. */ ++volatile int global_var_0 = 0; ++volatile int global_var_1 = 0; ++ ++/* This flag is updated from GDB. */ ++volatile int raise_signal = 0; ++ ++/* Implement the breakpoint condition function. Release the other thread ++ and try to give the other thread a chance to run. Then return ANSWER. */ ++int ++condition_core_func (int answer) ++{ ++ /* This unlock should release the other thread. */ ++ if (pthread_mutex_unlock (&mutex) != 0) ++ abort (); ++ ++ /* And this yield and sleep should (hopefully) give the other thread a ++ chance to run. This isn't guaranteed of course, but once the other ++ thread does run it should hit a breakpoint, which GDB should ++ (temporarily) ignore, so there's no easy way for us to know the other ++ thread has done what it needs to, thus, yielding and sleeping is the ++ best we can do. */ ++ sched_yield (); ++ sleep (2); ++ ++ return answer; ++} ++ ++void ++stop_marker () ++{ ++ int a = 100; /* Final breakpoint here. */ ++} ++ ++/* A breakpoint condition function that always returns true. */ ++int ++condition_true_func () ++{ ++ return condition_core_func (1); ++} ++ ++/* A breakpoint condition function that always returns false. */ ++int ++condition_false_func () ++{ ++ return condition_core_func (0); ++} ++ ++void * ++worker_func (void *arg) ++{ ++ volatile int *ptr = 0; ++ int tid = *((int *) arg); ++ ++ switch (tid) ++ { ++ case 0: ++ global_var_0 = 11; /* First thread breakpoint. */ ++ break; ++ ++ case 1: ++ if (pthread_mutex_lock (&mutex) != 0) ++ abort (); ++ if (raise_signal) ++ global_var_1 = *ptr; /* Signal here. */ ++ else ++ global_var_1 = 99; /* Other thread breakpoint. */ ++ break; ++ ++ default: ++ abort (); ++ } ++ ++ return NULL; ++} ++ ++int ++main () ++{ ++ pthread_t threads[NUM_THREADS]; ++ int args[NUM_THREADS]; ++ ++ /* Set an alarm, just in case the test deadlocks. */ ++ alarm (300); ++ ++ /* We want the mutex to start locked. */ ++ if (pthread_mutex_lock (&mutex) != 0) ++ abort (); ++ ++ for (int i = 0; i < NUM_THREADS; i++) ++ { ++ args[i] = i; ++ pthread_create (&threads[i], NULL, worker_func, &args[i]); ++ } ++ ++ for (int i = 0; i < NUM_THREADS; i++) ++ { ++ void *retval; ++ pthread_join (threads[i], &retval); ++ } ++ ++ /* Unlock once we're done, just for cleanliness. */ ++ if (pthread_mutex_unlock (&mutex) != 0) ++ abort (); ++ ++ stop_marker (); ++ ++ return 0; ++} +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-other-thread-event.exp b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-other-thread-event.exp +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-other-thread-event.exp +@@ -0,0 +1,174 @@ ++# Copyright 2022-2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++ ++# Test for conditional breakpoints where the breakpoint condition includes ++# an inferior function call. ++# ++# The tests in this script are testing what happens when an event arrives in ++# another thread while GDB is waiting for the inferior function call (in the ++# breakpoint condition) to finish. ++# ++# The expectation is that GDB will queue events for other threads and wait ++# for the inferior function call to complete, if the condition is true, then ++# the conditional breakpoint should be reported first. The other thread ++# event should of course, not get lost, and should be reported as soon as ++# the user tries to continue the inferior. ++# ++# If the conditional breakpoint ends up not being taken (the condition is ++# false), then the other thread event should be reported immediately. ++# ++# This script tests what happens when the other thread event is (a) the ++# other thread hitting a breakpoint, and (b) the other thread taking a ++# signal (SIGSEGV in this case). ++ ++standard_testfile ++ ++if { [build_executable "failed to prepare" ${binfile} "${srcfile}" \ ++ {debug pthreads}] == -1 } { ++ return ++} ++ ++set cond_bp_line [gdb_get_line_number "First thread breakpoint"] ++set other_bp_line [gdb_get_line_number "Other thread breakpoint"] ++set final_bp_line [gdb_get_line_number "Final breakpoint here"] ++set signal_line [gdb_get_line_number "Signal here"] ++ ++# Start GDB based on TARGET_ASYNC and TARGET_NON_STOP, and then runto main. ++proc start_gdb_and_runto_main { target_async target_non_stop } { ++ save_vars { ::GDBFLAGS } { ++ append ::GDBFLAGS \ ++ " -ex \"maint set target-non-stop $target_non_stop\"" ++ append ::GDBFLAGS \ ++ " -ex \"maintenance set target-async ${target_async}\"" ++ ++ clean_restart ${::binfile} ++ } ++ ++ if { ![runto_main] } { ++ return -1 ++ } ++ ++ return 0 ++} ++ ++# Run a test of GDB's conditional breakpoints, where the conditions include ++# inferior function calls. While the inferior function call is executing ++# another thread will hit a breakpoint (when OTHER_THREAD_SIGNAL is false), ++# or receive a signal (when OTHER_THREAD_SIGNAL is true). GDB should report ++# the conditional breakpoint first (if the condition is true), and then ++# report the second thread event once the inferior is continued again. ++# ++# When STOP_AT_COND is true then the conditional breakpoint will have a ++# condition that evaluates to true (and GDB will stop at the breakpoint), ++# otherwise, the condition will evaluate to false (and GDB will not stop at ++# the breakpoint). ++proc run_condition_test { stop_at_cond other_thread_signal \ ++ target_async target_non_stop } { ++ if { [start_gdb_and_runto_main $target_async \ ++ $target_non_stop] == -1 } { ++ return ++ } ++ ++ # Setup the conditional breakpoint. ++ if { $stop_at_cond } { ++ set cond_func "condition_true_func" ++ } else { ++ set cond_func "condition_false_func" ++ } ++ gdb_breakpoint \ ++ "${::srcfile}:${::cond_bp_line} if (${cond_func} ())" ++ set cond_bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for conditional breakpoint"] ++ ++ if { $other_thread_signal } { ++ # Arrange for the other thread to raise a signal while GDB is ++ # evaluating the breakpoint condition. ++ gdb_test_no_output "set raise_signal = 1" ++ } else { ++ # And a breakpoint that will be hit by another thread only once the ++ # breakpoint condition starts to be evaluated. ++ gdb_breakpoint "${::srcfile}:${::other_bp_line}" ++ set other_bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for other breakpoint"] ++ } ++ ++ # A final breakpoint once the test has completed. ++ gdb_breakpoint "${::srcfile}:${::final_bp_line}" ++ set final_bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for final breakpoint"] ++ ++ if { $stop_at_cond } { ++ # Continue. The first breakpoint we hit should be the conditional ++ # breakpoint. The other thread will have hit its breakpoint, but ++ # that will have been deferred until the conditional breakpoint is ++ # reported. ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "" \ ++ "Thread ${::decimal} \"\[^\"\r\n\]+\" hit Breakpoint ${cond_bp_num}, worker_func \[^\r\n\]+:${::cond_bp_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+First thread breakpoint\[^\r\n\]+"] \ ++ "hit the conditional breakpoint" ++ } ++ ++ if { $other_thread_signal } { ++ # Now continue again, the other thread will now report that it ++ # received a signal. ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "Thread ${::decimal} \"\[^\"\r\n\]+\" received signal SIGSEGV, Segmentation fault\\." \ ++ "\\\[Switching to Thread \[^\r\n\]+\\\]" \ ++ "${::hex} in worker_func \[^\r\n\]+:${::signal_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Signal here\[^\r\n\]+"] \ ++ "received signal in other thread" ++ } else { ++ # Now continue again, the other thread will now report its ++ # breakpoint. ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "" \ ++ "Thread ${::decimal} \"\[^\"\r\n\]+\" hit Breakpoint ${other_bp_num}, worker_func \[^\r\n\]+:${::other_bp_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Other thread breakpoint\[^\r\n\]+"] \ ++ "hit the breakpoint in other thread" ++ ++ # Run to the stop marker. ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "" \ ++ "Thread ${::decimal} \"\[^\"\r\n\]+\" hit Breakpoint ${final_bp_num}, stop_marker \[^\r\n\]+:${::final_bp_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Final breakpoint here\[^\r\n\]+"] \ ++ "hit the final breakpoint" ++ } ++ ++ gdb_exit ++} ++ ++foreach_with_prefix target_async { "on" "off" } { ++ foreach_with_prefix target_non_stop { "on" "off" } { ++ foreach_with_prefix other_thread_signal { true false } { ++ foreach_with_prefix stop_at_cond { true false } { ++ run_condition_test $stop_at_cond $other_thread_signal \ ++ $target_async $target_non_stop ++ } ++ } ++ } ++} +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.c b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.c +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.c +@@ -0,0 +1,89 @@ ++/* Copyright 2022-2024 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include ++#include ++ ++#define NUM_THREADS 3 ++ ++int ++is_matching_tid (int *tid_ptr, int tid_value) ++{ ++ return *tid_ptr == tid_value; ++} ++ ++int ++return_true () ++{ ++ return 1; ++} ++ ++int ++return_false () ++{ ++ return 0; ++} ++ ++int ++function_that_segfaults () ++{ ++ int *p = 0; ++ *p = 1; /* Segfault happens here. */ ++} ++ ++int ++function_with_breakpoint () ++{ ++ return 1; /* Nested breakpoint. */ ++} ++ ++void * ++worker_func (void *arg) ++{ ++ int a = 42; /* Breakpoint here. */ ++} ++ ++void ++stop_marker () ++{ ++ int b = 99; /* Stop marker. */ ++} ++ ++int ++main () ++{ ++ pthread_t threads[NUM_THREADS]; ++ int args[NUM_THREADS]; ++ ++ alarm (300); ++ ++ for (int i = 0; i < NUM_THREADS; i++) ++ { ++ args[i] = i; ++ pthread_create (&threads[i], NULL, worker_func, &args[i]); ++ } ++ ++ for (int i = 0; i < NUM_THREADS; i++) ++ { ++ void *retval; ++ pthread_join (threads[i], &retval); ++ } ++ ++ stop_marker (); ++ ++ return 0; ++} +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.exp b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.exp +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.exp +@@ -0,0 +1,235 @@ ++# Copyright 2022-2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++ ++# Some simple tests of inferior function calls from breakpoint ++# conditions, in multi-threaded inferiors. ++# ++# This test sets up a multi-threaded inferior, and places a breakpoint ++# at a location that many of the threads will reach. We repeat the ++# test with different conditions, sometimes a single thread should ++# stop at the breakpoint, sometimes multiple threads should stop, and ++# sometimes no threads should stop. ++ ++standard_testfile ++ ++if { [build_executable "failed to prepare" ${binfile} "${srcfile}" \ ++ {debug pthreads}] == -1 } { ++ return ++} ++ ++set cond_bp_line [gdb_get_line_number "Breakpoint here"] ++set stop_bp_line [gdb_get_line_number "Stop marker"] ++set nested_bp_line [gdb_get_line_number "Nested breakpoint"] ++set segv_line [gdb_get_line_number "Segfault happens here"] ++ ++# Start GDB based on TARGET_ASYNC and TARGET_NON_STOP, and then runto main. ++proc start_gdb_and_runto_main { target_async target_non_stop } { ++ save_vars { ::GDBFLAGS } { ++ append ::GDBFLAGS \ ++ " -ex \"maint set target-non-stop $target_non_stop\"" ++ append ::GDBFLAGS \ ++ " -ex \"maintenance set target-async ${target_async}\"" ++ ++ clean_restart ${::binfile} ++ } ++ ++ if { ![runto_main] } { ++ return -1 ++ } ++ ++ return 0 ++} ++ ++# Run a test of GDB's conditional breakpoints, where the conditions include ++# inferior function calls. ++# ++# CONDITION is the expression to be used as the breakpoint condition. ++# ++# N_EXPECTED_HITS is the number of threads that we expect to stop due to ++# CONDITON. ++# ++# MESSAGE is used as a test name prefix. ++proc run_condition_test { message n_expected_hits condition \ ++ target_async target_non_stop } { ++ with_test_prefix $message { ++ ++ if { [start_gdb_and_runto_main $target_async \ ++ $target_non_stop] == -1 } { ++ return ++ } ++ ++ # Use this convenience variable to track how often the ++ # breakpoint condition has been evaluated. This should be ++ # once per thread. ++ gdb_test "set \$n_cond_eval = 0" ++ ++ # Setup the conditional breakpoint. ++ gdb_breakpoint \ ++ "${::srcfile}:${::cond_bp_line} if ((++\$n_cond_eval) && (${condition}))" ++ ++ # And a breakpoint that we hit when the test is over, this one is ++ # not conditional. Only the main thread gets here once all the ++ # other threads have finished. ++ gdb_breakpoint "${::srcfile}:${::stop_bp_line}" ++ ++ # The number of times we stop at the conditional breakpoint. ++ set n_hit_condition 0 ++ ++ # Now keep 'continue'-ing GDB until all the threads have finished ++ # and we reach the stop_marker breakpoint. ++ gdb_test_multiple "continue" "spot all breakpoint hits" { ++ -re " worker_func \[^\r\n\]+${::srcfile}:${::cond_bp_line}\r\n${::decimal}\\s+\[^\r\n\]+Breakpoint here\[^\r\n\]+\r\n${::gdb_prompt} $" { ++ incr n_hit_condition ++ send_gdb "continue\n" ++ exp_continue ++ } ++ ++ -re " stop_marker \[^\r\n\]+${::srcfile}:${::stop_bp_line}\r\n${::decimal}\\s+\[^\r\n\]+Stop marker\[^\r\n\]+\r\n${::gdb_prompt} $" { ++ pass $gdb_test_name ++ } ++ } ++ ++ gdb_assert { $n_hit_condition == $n_expected_hits } \ ++ "stopped at breakpoint the expected number of times" ++ ++ # Ensure the breakpoint condition was evaluated once per thread. ++ gdb_test "print \$n_cond_eval" "= 3" \ ++ "condition was evaluated in each thread" ++ } ++} ++ ++# Check that after handling a conditional breakpoint (where the condition ++# includes an inferior call), it is still possible to kill the running ++# inferior, and then restart the inferior. ++# ++# At once point doing this would result in GDB giving an assertion error. ++proc_with_prefix run_kill_and_restart_test { target_async target_non_stop } { ++ # This test relies on the 'start' command, which is not possible with ++ # the plain 'remote' target. ++ if { [target_info gdb_protocol] == "remote" } { ++ return ++ } ++ ++ if { [start_gdb_and_runto_main $target_async \ ++ $target_non_stop] == -1 } { ++ return ++ } ++ ++ # Setup the conditional breakpoint. ++ gdb_breakpoint \ ++ "${::srcfile}:${::cond_bp_line} if (is_matching_tid (arg, 1))" ++ gdb_continue_to_breakpoint "worker_func" ++ ++ # Now kill the program being debugged. ++ gdb_test "kill" "" "kill process" \ ++ "Kill the program being debugged.*y or n. $" "y" ++ ++ # Check we can restart the inferior. At one point this would trigger an ++ # assertion. ++ gdb_start_cmd ++} ++ ++# Create a conditional breakpoint which includes a call to a function that ++# segfaults. Run GDB and check what happens when the inferior segfaults ++# during the inferior call. ++proc_with_prefix run_bp_cond_segfaults { target_async target_non_stop } { ++ if { [start_gdb_and_runto_main $target_async \ ++ $target_non_stop] == -1 } { ++ return ++ } ++ ++ # This test relies on the inferior segfaulting when trying to ++ # access address zero. ++ if { [is_address_zero_readable] } { ++ return ++ } ++ ++ # Setup the conditional breakpoint, include a call to ++ # 'function_that_segfaults', which triggers the segfault. ++ gdb_breakpoint \ ++ "${::srcfile}:${::cond_bp_line} if (is_matching_tid (arg, 0) && function_that_segfaults ())" ++ set bp_1_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number of conditional breakpoint"] ++ ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "Thread ${::decimal} \"infcall-from-bp\" received signal SIGSEGV, Segmentation fault\\." \ ++ "${::hex} in function_that_segfaults \\(\\) at \[^\r\n\]+:${::segv_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Segfault happens here\[^\r\n\]+" \ ++ "Error in testing condition for breakpoint ${bp_1_num}:" \ ++ "The program being debugged was signaled while in a function called from GDB\\." \ ++ "GDB remains in the frame where the signal was received\\." \ ++ "To change this behavior use \"set unwindonsignal on\"\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(function_that_segfaults\\) will be abandoned\\." \ ++ "When the function is done executing, GDB will silently stop\\."] ++} ++ ++# Create a conditional breakpoint which includes a call to a function that ++# itself has a breakpoint set within it. Run GDB and check what happens ++# when GDB hits the nested breakpoint. ++proc_with_prefix run_bp_cond_hits_breakpoint { target_async target_non_stop } { ++ if { [start_gdb_and_runto_main $target_async \ ++ $target_non_stop] == -1 } { ++ return ++ } ++ ++ # Setup the conditional breakpoint, include a call to ++ # 'function_with_breakpoint' in which we will shortly place a ++ # breakpoint. ++ gdb_breakpoint \ ++ "${::srcfile}:${::cond_bp_line} if (is_matching_tid (arg, 0) && function_with_breakpoint ())" ++ set bp_1_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number of conditional breakpoint"] ++ ++ gdb_breakpoint "${::srcfile}:${::nested_bp_line}" ++ set bp_2_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number of nested breakpoint"] ++ ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "Thread ${::decimal} \"infcall-from-bp\" hit Breakpoint ${bp_2_num}, function_with_breakpoint \\(\\) at \[^\r\n\]+:${::nested_bp_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Nested breakpoint\[^\r\n\]+" \ ++ "Error in testing condition for breakpoint ${bp_1_num}:" \ ++ "The program being debugged stopped while in a function called from GDB\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(function_with_breakpoint\\) will be abandoned\\." \ ++ "When the function is done executing, GDB will silently stop\\."] ++} ++ ++foreach_with_prefix target_async { "on" "off" } { ++ foreach_with_prefix target_non_stop { "on" "off" } { ++ run_condition_test "exactly one thread is hit" \ ++ 1 "is_matching_tid (arg, 1)" \ ++ $target_async $target_non_stop ++ run_condition_test "exactly two threads are hit" \ ++ 2 "(is_matching_tid (arg, 0) || is_matching_tid (arg, 2))" \ ++ $target_async $target_non_stop ++ run_condition_test "all three threads are hit" \ ++ 3 "return_true ()" \ ++ $target_async $target_non_stop ++ run_condition_test "no thread is hit" \ ++ 0 "return_false ()" \ ++ $target_async $target_non_stop ++ ++ run_kill_and_restart_test $target_async $target_non_stop ++ run_bp_cond_segfaults $target_async $target_non_stop ++ run_bp_cond_hits_breakpoint $target_async $target_non_stop ++ } ++} +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-single.c b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-single.c +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-single.c +@@ -0,0 +1,139 @@ ++/* Copyright 2022-2024 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include ++#include ++#include ++#include ++ ++#define NUM_THREADS 5 ++ ++/* Semaphores, used to track when threads have started, and to control ++ when the threads finish. */ ++sem_t startup_semaphore; ++sem_t finish_semaphore; ++ ++/* Mutex to control when the first worker thread hit a breakpoint ++ location. */ ++pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER; ++ ++/* Global variable to poke, just so threads have something to do. */ ++volatile int global_var = 0; ++ ++int ++return_true () ++{ ++ return 1; ++} ++ ++int ++return_false () ++{ ++ return 0; ++} ++ ++void * ++worker_func (void *arg) ++{ ++ int tid = *((int *) arg); ++ ++ switch (tid) ++ { ++ case 0: ++ /* Wait for MUTEX to become available, then pass through the ++ conditional breakpoint location. */ ++ if (pthread_mutex_lock (&mutex) != 0) ++ abort (); ++ global_var = 99; /* Conditional breakpoint here. */ ++ if (pthread_mutex_unlock (&mutex) != 0) ++ abort (); ++ break; ++ ++ default: ++ /* Notify the main thread that the thread has started, then wait for ++ the main thread to tell us to finish. */ ++ sem_post (&startup_semaphore); ++ if (sem_wait (&finish_semaphore) != 0) ++ abort (); ++ break; ++ } ++} ++ ++void ++stop_marker () ++{ ++ global_var = 99; /* Stop marker. */ ++} ++ ++int ++main () ++{ ++ pthread_t threads[NUM_THREADS]; ++ int args[NUM_THREADS]; ++ void *retval; ++ ++ /* An alarm, just in case the thread deadlocks. */ ++ alarm (300); ++ ++ /* Semaphore initialization. */ ++ if (sem_init (&startup_semaphore, 0, 0) != 0) ++ abort (); ++ if (sem_init (&finish_semaphore, 0, 0) != 0) ++ abort (); ++ ++ /* Lock MUTEX, this prevents the first worker thread from rushing ahead. */ ++ if (pthread_mutex_lock (&mutex) != 0) ++ abort (); ++ ++ /* Worker thread creation. */ ++ for (int i = 0; i < NUM_THREADS; i++) ++ { ++ args[i] = i; ++ pthread_create (&threads[i], NULL, worker_func, &args[i]); ++ } ++ ++ /* Wait for every thread (other than the first) to tell us it has started ++ up. */ ++ for (int i = 1; i < NUM_THREADS; i++) ++ { ++ if (sem_wait (&startup_semaphore) != 0) ++ abort (); ++ } ++ ++ /* Unlock the first thread so it can proceed. */ ++ if (pthread_mutex_unlock (&mutex) != 0) ++ abort (); ++ ++ /* Wait for the first thread only. */ ++ pthread_join (threads[0], &retval); ++ ++ /* Now post FINISH_SEMAPHORE to allow all the other threads to finish. */ ++ for (int i = 1; i < NUM_THREADS; i++) ++ sem_post (&finish_semaphore); ++ ++ /* Now wait for the remaining threads to complete. */ ++ for (int i = 1; i < NUM_THREADS; i++) ++ pthread_join (threads[i], &retval); ++ ++ /* Semaphore cleanup. */ ++ sem_destroy (&finish_semaphore); ++ sem_destroy (&startup_semaphore); ++ ++ stop_marker (); ++ ++ return 0; ++} +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-single.exp b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-single.exp +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-single.exp +@@ -0,0 +1,117 @@ ++# Copyright 2022-2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++ ++# This test reprocuces bug gdb/28942, performing an inferior function ++# call from a breakpoint condition in a multi-threaded inferior. ++# ++# The important part of this test is that, when the conditional ++# breakpoint is hit, and the condition (which includes an inferior ++# function call) is evaluated, the other threads are running. ++ ++standard_testfile ++ ++if { [build_executable "failed to prepare" ${binfile} "${srcfile}" \ ++ {debug pthreads}] == -1 } { ++ return ++} ++ ++set cond_bp_line [gdb_get_line_number "Conditional breakpoint here"] ++set final_bp_line [gdb_get_line_number "Stop marker"] ++ ++# Start GDB based on TARGET_ASYNC and TARGET_NON_STOP, and then runto main. ++proc start_gdb_and_runto_main { target_async target_non_stop } { ++ save_vars { ::GDBFLAGS } { ++ append ::GDBFLAGS \ ++ " -ex \"maint set target-non-stop $target_non_stop\"" ++ append ::GDBFLAGS \ ++ " -ex \"maintenance set target-async ${target_async}\"" ++ ++ clean_restart ${::binfile} ++ } ++ ++ if { ![runto_main] } { ++ return -1 ++ } ++ ++ return 0 ++} ++ ++# Run a test of GDB's conditional breakpoints, where the conditions include ++# inferior function calls. ++# ++# TARGET_ASYNC and TARGET_NON_STOP are used when starting up GDB. ++# ++# When STOP_AT_COND is true the breakpoint condtion will evaluate to ++# true, and GDB will stop at the breakpoint. Otherwise, the ++# breakpoint condition will evaluate to false and GDB will not stop at ++# the breakpoint. ++proc run_condition_test { stop_at_cond \ ++ target_async target_non_stop } { ++ if { [start_gdb_and_runto_main $target_async \ ++ $target_non_stop] == -1 } { ++ return ++ } ++ ++ # Setup the conditional breakpoint. ++ if { $stop_at_cond } { ++ set cond_func "return_true" ++ } else { ++ set cond_func "return_false" ++ } ++ gdb_breakpoint \ ++ "${::srcfile}:${::cond_bp_line} if (${cond_func} ())" ++ set cond_bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for conditional breakpoint"] ++ ++ # And a breakpoint that we hit when the test is over, this one is ++ # not conditional. ++ gdb_breakpoint "${::srcfile}:${::final_bp_line}" ++ set final_bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for final breakpoint"] ++ ++ if { $stop_at_cond } { ++ # Continue. The first breakpoint we hit should be the conditional ++ # breakpoint. The other thread will have hit its breakpoint, but ++ # that will have been deferred until the conditional breakpoint is ++ # reported. ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "" \ ++ "Thread ${::decimal} \"\[^\"\r\n\]+\" hit Breakpoint ${cond_bp_num}, worker_func \[^\r\n\]+:${::cond_bp_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Conditional breakpoint here\[^\r\n\]+"] \ ++ "hit the conditional breakpoint" ++ } ++ ++ # Run to the stop marker. ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "" \ ++ "Thread ${::decimal} \"\[^\"\r\n\]+\" hit Breakpoint ${final_bp_num}, stop_marker \[^\r\n\]+:${::final_bp_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Stop marker\[^\r\n\]+"] \ ++ "hit the final breakpoint" ++} ++ ++foreach_with_prefix target_async { "on" "off" } { ++ foreach_with_prefix target_non_stop { "on" "off" } { ++ foreach_with_prefix stop_at_cond { true false } { ++ run_condition_test $stop_at_cond \ ++ $target_async $target_non_stop ++ } ++ } ++} diff --git a/gdb-rhel-13298-inferior-funcall-bp-condition-3-of-5.patch b/gdb-rhel-13298-inferior-funcall-bp-condition-3-of-5.patch new file mode 100644 index 0000000..3087f1d --- /dev/null +++ b/gdb-rhel-13298-inferior-funcall-bp-condition-3-of-5.patch @@ -0,0 +1,1148 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andrew Burgess +Date: Fri, 7 Oct 2022 12:39:07 +0100 +Subject: gdb-rhel-13298-inferior-funcall-bp-condition-3-of-5.patch + +;;gdb: add timeouts for inferior function calls +;;(Andrew Burgess, RHEL-13298) + +In the previous commits I have been working on improving inferior +function call support. One thing that worries me about using inferior +function calls from a conditional breakpoint is: what happens if the +inferior function call fails? + +If the failure is obvious, e.g. the thread performing the call +crashes, or hits a breakpoint, then this case is already well handled, +and the error is reported to the user. + +But what if the thread performing the inferior call just deadlocks? +If the user made the call from a 'print' or 'call' command, then the +user might have some expectation of when the function call should +complete, and, when this time limit is exceeded, the user +will (hopefully) interrupt GDB and regain control of the debug +session. + +But, when the inferior function call is from a breakpoint condition it +is much harder to understand that GDB is deadlocked within an inferior +call. Maybe the breakpoint hasn't been hit yet? Or maybe the +condition was always false? Or maybe GDB is deadlocked in an inferior +call? The only way to know for sure is for the user to periodically +interrupt the inferior, check on the state of all the threads, and +then continue. + +Additionally, the focus of the previous commit was inferior function +calls, from a conditional breakpoint, in a multi-threaded inferior. +This opens up a whole new set of potential failure conditions. For +example, what if the function called relies on interaction with some +other thread, and the other thread crashes? Or hits a breakpoint? +Given how inferior function calls work (in a synchronous manner), a +stop event in some other thread is going to be ignored while the +inferior function call is being executed as part of a breakpoint +condition, and this means that GDB could get stuck waiting for the +original condition thread, which will now never complete. + +In this commit I propose a solution to this problem. A timeout. For +targets that support async-mode we can install an event-loop timer +before starting the inferior function call. When the timer expires we +will stop the thread performing the inferior function call. With this +mechanism in place a user can be sure that any inferior call they make +will either complete, or timeout eventually. + +Adding a timer like this is obviously a change in behaviour for the +more common 'call' and 'print' uses of inferior function calls, so, in +this patch, I propose having two different timers. One I call the +'direct-call-timeout', which is used for 'call' and 'print' commands. +This timeout is by default set to unlimited, which, not surprisingly, +means there is no timeout in place. + +A second timer, which I've called 'indirect-call-timeout', is used for +inferior function calls from breakpoint conditions. This timeout has +a default value of 30 seconds. This is a reasonably long time to +wait, and hopefully should be enough in most cases to allow the +inferior call to complete. An inferior call that takes more than 30 +seconds, which is installed on a breakpoint condition is really going +to slow down the debug session, so hopefully this is not a common use +case. + +The user is, of course, free to reduce, or increase the timeout value, +and can always use Ctrl-c to interrupt an inferior function call, but +this timeout will ensure that GDB will stop at some point. + +The new commands added by this commit are: + + set direct-call-timeout SECONDS + show direct-call-timeout + set indirect-call-timeout SECONDS + show indirect-call-timeout + +These new timeouts do depend on async-mode, so, if async-mode is +disabled (maint set target-async off), or not supported (e.g. target +sim), then the timeout is treated as unlimited (that is, no timeout is +set). + +For targets that "fake" non-async mode, e.g. Linux native, where +non-async mode is really just async mode, but then we park the target +in a sissuspend, we could easily fix things so that the timeouts still +work, however, for targets that really are not async aware, like the +simulator, fixing things so that timeouts work correctly would be a +much bigger task - that effort would be better spent just making the +target async-aware. And so, I'm happy for now that this feature will +only work on async targets. + +The two new show commands will display slightly different text if the +current target is a non-async target, which should allow users to +understand what's going on. + +There's a somewhat random test adjustment needed in gdb.base/help.exp, +the test uses a regexp with the apropos command, and expects to find a +single result. Turns out the new settings I added also matched the +regexp, which broke the test. I've updated the regexp a little to +exclude my new settings. + +Reviewed-By: Tankut Baris Aktemur +Reviewed-By: Eli Zaretskii +Tested-By: Luis Machado +Tested-By: Keith Seitz + +diff --git a/gdb/NEWS b/gdb/NEWS +--- a/gdb/NEWS ++++ b/gdb/NEWS +@@ -1,6 +1,179 @@ + What has changed in GDB? + (Organized release by release) + ++*** Changes since GDB 14 ++ ++* The MPX commands "show/set mpx bound" have been deprecated, as Intel ++ listed MPX as removed in 2019. ++ ++* Building GDB and GDBserver now requires a C++17 compiler. ++ For example, GCC 9 or later. ++ ++* GDB index now contains information about the main function. This speeds up ++ startup when it is being used for some large binaries. ++ ++* On hosts where threading is available, DWARF reading is now done in ++ the background, resulting in faster startup. This can be controlled ++ using "maint set dwarf synchronous". ++ ++* Changed commands ++ ++disassemble ++ Attempting to use both the 'r' and 'b' flags with the disassemble ++ command will now give an error. Previously the 'b' flag would ++ always override the 'r' flag. ++ ++gcore ++generate-core-file ++ GDB now generates sparse core files, on systems that support it. ++ ++maintenance info line-table ++ Add an EPILOGUE-BEGIN column to the output of the command. It indicates ++ if the line is considered the start of the epilgoue, and thus a point at ++ which the frame can be considered destroyed. ++ ++* New commands ++ ++info missing-debug-handler ++ List all the registered missing debug handlers. ++ ++enable missing-debug-handler LOCUS HANDLER ++disable missing-debug-handler LOCUS HANDLER ++ Enable or disable a missing debug handler with a name matching the ++ regular expression HANDLER, in LOCUS. ++ ++ LOCUS can be 'global' to operate on global missing debug handler, ++ 'progspace' to operate on handlers within the current program space, ++ or can be a regular expression which is matched against the filename ++ of the primary executable in each program space. ++ ++maintenance info linux-lwps ++ List all LWPs under control of the linux-nat target. ++ ++set remote thread-options-packet ++show remote thread-options-packet ++ Set/show the use of the thread options packet. ++ ++set direct-call-timeout SECONDS ++show direct-call-timeout ++set indirect-call-timeout SECONDS ++show indirect-call-timeout ++ These new settings can be used to limit how long GDB will wait for ++ an inferior function call to complete. The direct timeout is used ++ for inferior function calls from e.g. 'call' and 'print' commands, ++ while the indirect timeout is used for inferior function calls from ++ within a conditional breakpoint expression. ++ ++ The default for the direct timeout is unlimited, while the default ++ for the indirect timeout is 30 seconds. ++ ++ These timeouts will only have an effect for targets that are ++ operating in async mode. For non-async targets the timeouts are ++ ignored, GDB will wait indefinitely for an inferior function to ++ complete, unless interrupted by the user using Ctrl-C. ++ ++* New features in the GDB remote stub, GDBserver ++ ++ ** The --remote-debug and --event-loop-debug command line options ++ have been removed. ++ ++ ** The --debug command line option now takes an optional comma ++ separated list of components to emit debug for. The currently ++ supported components are: all, threads, event-loop, and remote. ++ If no components are given then threads is assumed. ++ ++ ** The 'monitor set remote-debug' and 'monitor set event-loop-debug' ++ command have been removed. ++ ++ ** The 'monitor set debug 0|1' command has been extended to take a ++ component name, e.g.: 'monitor set debug COMPONENT off|on'. ++ Possible component names are: all, threads, event-loop, and ++ remote. ++ ++* Python API ++ ++ ** New function gdb.notify_mi(NAME, DATA), that emits custom ++ GDB/MI async notification. ++ ++ ** New read/write attribute gdb.Value.bytes that contains a bytes ++ object holding the contents of this value. ++ ++ ** New module gdb.missing_debug that facilitates dealing with ++ objfiles that are missing any debug information. ++ ++ ** New function gdb.missing_debug.register_handler that can register ++ an instance of a sub-class of gdb.missing_debug.MissingDebugInfo ++ as a handler for objfiles that are missing debug information. ++ ++ ** New class gdb.missing_debug.MissingDebugInfo which can be ++ sub-classed to create handlers for objfiles with missing debug ++ information. ++ ++ ** Stop events now have a "details" attribute that holds a ++ dictionary that carries the same information as an MI "*stopped" ++ event. ++ ++ ** New function gdb.interrupt(), that interrupts GDB as if the user ++ typed control-c. ++ ++ ** New gdb.InferiorThread.ptid_string attribute. This read-only ++ attribute contains the string that appears in the 'Target Id' ++ column of the 'info threads' command output. ++ ++ ** It is no longer possible to create new gdb.Progspace object using ++ 'gdb.Progspace()', this will result in a TypeError. Progspace ++ objects can still be obtained through calling other API ++ functions, for example 'gdb.current_progspace()'. ++ ++ ** User defined attributes can be added to a gdb.Inferior object, ++ these will be stored in the object's new Inferior.__dict__ ++ attribute. ++ ++ ** User defined attributes can be added to a gdb.InferiorThread ++ object, these will be stored in the object's new ++ InferiorThread.__dict__ attribute. ++ ++ ** New constants gdb.SYMBOL_TYPE_DOMAIN, gdb.SYMBOL_FUNCTION_DOMAIN, ++ and gdb.SEARCH_*_DOMAIN corresponding to all the existing symbol ++ domains. Symbol lookup can now search in multiple domains at ++ once, and can also narrowly search for just a type or function. ++ ++* Debugger Adapter Protocol changes ++ ++ ** GDB now emits the "process" event. ++ ++ ** GDB now supports the "cancel" request. ++ ++ ** The "attach" request now supports specifying the program. ++ ++ ** New command "set debug dap-log-level" controls DAP logging. ++ ++ ** The "set debug dap-log-file" command is now documented. This ++ command was available in GDB 14 but not documented. ++ ++* Guile API ++ ++ ** New constants SYMBOL_TYPE_DOMAIN, SYMBOL_FUNCTION_DOMAIN, and ++ SEARCH_*_DOMAIN corresponding to all the existing symbol domains. ++ Symbol lookup can now search in multiple domains at once, and can ++ also narrowly search for just a type or function. ++ ++* New remote packets ++ ++New stop reason: clone ++ Indicates that a clone system call was executed. ++ ++QThreadOptions ++ Enable/disable optional event reporting, on a per-thread basis. ++ Currently supported options are GDB_THREAD_OPTION_CLONE, to enable ++ clone event reporting, and GDB_THREAD_OPTION_EXIT to enable thread ++ exit event reporting. ++ ++QThreadOptions in qSupported ++ The qSupported packet allows GDB to inform the stub it supports the ++ QThreadOptions packet, and the qSupported response can contain the ++ set of thread options the remote stub supports. ++ + *** Changes in GDB 14 + + * GDB now supports the AArch64 Scalable Matrix Extension 2 (SME2), which +diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo +--- a/gdb/doc/gdb.texinfo ++++ b/gdb/doc/gdb.texinfo +@@ -20987,6 +20987,72 @@ to resume the inferior (using commands like @code{continue}, + @code{step}, etc). In this case, when the inferior finally returns to + the dummy-frame, @value{GDBN} will once again halt the inferior. + ++On targets that support asynchronous execution (@pxref{Background ++Execution}) @value{GDBN} can place a timeout on any functions called ++from @value{GDBN}. If the timeout expires and the function call is ++still ongoing, then @value{GDBN} will interrupt the program. ++ ++For targets that don't support asynchronous execution ++(@pxref{Background Execution}) then timeouts for functions called from ++@value{GDBN} are not supported, the timeout settings described below ++will be treated as @code{unlimited}, meaning @value{GDBN} will wait ++indefinitely for function call to complete, unless interrupted by the ++user using @kbd{Ctrl-C}. ++ ++@table @code ++@item set direct-call-timeout @var{seconds} ++@kindex set direct-call-timeout ++@cindex timeout for called functions ++Set the timeout used when calling functions in the program to ++@var{seconds}, which should be an integer greater than zero, or the ++special value @code{unlimited}, which indicates no timeout should be ++used. The default for this setting is @code{unlimited}. ++ ++This setting is used when the user calls a function directly from the ++command prompt, for example with a @code{call} or @code{print} ++command. ++ ++This setting only works for targets that support asynchronous ++execution (@pxref{Background Execution}), for any other target the ++setting is treated as @code{unlimited}. ++ ++@item show direct-call-timeout ++@kindex show direct-call-timeout ++@cindex timeout for called functions ++Show the timeout used when calling functions in the program with a ++@code{call} or @code{print} command. ++@end table ++ ++It is also possible to call functions within the program from the ++condition of a conditional breakpoint (@pxref{Conditions, ,Break ++Conditions}). A different setting controls the timeout used for ++function calls made from a breakpoint condition. ++ ++@table @code ++@item set indirect-call-timeout @var{seconds} ++@kindex set indirect-call-timeout ++@cindex timeout for called functions ++Set the timeout used when calling functions in the program from a ++breakpoint or watchpoint condition to @var{seconds}, which should be ++an integer greater than zero, or the special value @code{unlimited}, ++which indicates no timeout should be used. The default for this ++setting is @code{30} seconds. ++ ++This setting only works for targets that support asynchronous ++execution (@pxref{Background Execution}), for any other target the ++setting is treated as @code{unlimited}. ++ ++If a function called from a breakpoint or watchpoint condition times ++out, then @value{GDBN} will stop at the point where the timeout ++occurred. The breakpoint condition evaluation will be abandoned. ++ ++@item show indirect-call-timeout ++@kindex show indirect-call-timeout ++@cindex timeout for called functions ++Show the timeout used when calling functions in the program from a ++breakpoint or watchpoint condition. ++@end table ++ + @subsection Calling functions with no debug info + + @cindex no debug info functions +diff --git a/gdb/infcall.c b/gdb/infcall.c +--- a/gdb/infcall.c ++++ b/gdb/infcall.c +@@ -96,6 +96,53 @@ show_may_call_functions_p (struct ui_file *file, int from_tty, + value); + } + ++/* A timeout (in seconds) for direct inferior calls. A direct inferior ++ call is one the user triggers from the prompt, e.g. with a 'call' or ++ 'print' command. Compare with the definition of indirect calls below. */ ++ ++static unsigned int direct_call_timeout = UINT_MAX; ++ ++/* Implement 'show direct-call-timeout'. */ ++ ++static void ++show_direct_call_timeout (struct ui_file *file, int from_tty, ++ struct cmd_list_element *c, const char *value) ++{ ++ if (target_has_execution () && !target_can_async_p ()) ++ gdb_printf (file, _("Current target does not support async mode, timeout " ++ "for direct inferior calls is \"unlimited\".\n")); ++ else if (direct_call_timeout == UINT_MAX) ++ gdb_printf (file, _("Timeout for direct inferior function calls " ++ "is \"unlimited\".\n")); ++ else ++ gdb_printf (file, _("Timeout for direct inferior function calls " ++ "is \"%s seconds\".\n"), value); ++} ++ ++/* A timeout (in seconds) for indirect inferior calls. An indirect inferior ++ call is one that originates from within GDB, for example, when ++ evaluating an expression for a conditional breakpoint. Compare with ++ the definition of direct calls above. */ ++ ++static unsigned int indirect_call_timeout = 30; ++ ++/* Implement 'show indirect-call-timeout'. */ ++ ++static void ++show_indirect_call_timeout (struct ui_file *file, int from_tty, ++ struct cmd_list_element *c, const char *value) ++{ ++ if (target_has_execution () && !target_can_async_p ()) ++ gdb_printf (file, _("Current target does not support async mode, timeout " ++ "for indirect inferior calls is \"unlimited\".\n")); ++ else if (indirect_call_timeout == UINT_MAX) ++ gdb_printf (file, _("Timeout for indirect inferior function calls " ++ "is \"unlimited\".\n")); ++ else ++ gdb_printf (file, _("Timeout for indirect inferior function calls " ++ "is \"%s seconds\".\n"), value); ++} ++ + /* How you should pass arguments to a function depends on whether it + was defined in K&R style or prototype style. If you define a + function using the K&R syntax that takes a `float' argument, then +@@ -620,6 +667,85 @@ call_thread_fsm::should_notify_stop () + return true; + } + ++/* A class to control creation of a timer that will interrupt a thread ++ during an inferior call. */ ++struct infcall_timer_controller ++{ ++ /* Setup an event-loop timer that will interrupt PTID if the inferior ++ call takes too long. DIRECT_CALL_P is true when this inferior call is ++ a result of the user using a 'print' or 'call' command, and false when ++ this inferior call is a result of e.g. a conditional breakpoint ++ expression, this is used to select which timeout to use. */ ++ infcall_timer_controller (thread_info *thr, bool direct_call_p) ++ : m_thread (thr) ++ { ++ unsigned int timeout ++ = direct_call_p ? direct_call_timeout : indirect_call_timeout; ++ if (timeout < UINT_MAX && target_can_async_p ()) ++ { ++ int ms = timeout * 1000; ++ int id = create_timer (ms, infcall_timer_controller::timed_out, this); ++ m_timer_id.emplace (id); ++ infcall_debug_printf ("Setting up infcall timeout timer for " ++ "ptid %s: %d milliseconds", ++ m_thread->ptid.to_string ().c_str (), ms); ++ } ++ } ++ ++ /* Destructor. Ensure that the timer is removed from the event loop. */ ++ ~infcall_timer_controller () ++ { ++ /* If the timer has already triggered, then it will have already been ++ deleted from the event loop. If the timer has not triggered, then ++ delete it now. */ ++ if (m_timer_id.has_value () && !m_triggered) ++ delete_timer (*m_timer_id); ++ ++ /* Just for clarity, discard the timer id now. */ ++ m_timer_id.reset (); ++ } ++ ++ /* Return true if there was a timer in place, and the timer triggered, ++ otherwise, return false. */ ++ bool triggered_p () ++ { ++ gdb_assert (!m_triggered || m_timer_id.has_value ()); ++ return m_triggered; ++ } ++ ++private: ++ /* The thread we should interrupt. */ ++ thread_info *m_thread; ++ ++ /* Set true when the timer is triggered. */ ++ bool m_triggered = false; ++ ++ /* Given a value when a timer is in place. */ ++ gdb::optional m_timer_id; ++ ++ /* Callback for the timer, forwards to ::trigger below. */ ++ static void ++ timed_out (gdb_client_data context) ++ { ++ infcall_timer_controller *ctrl ++ = static_cast (context); ++ ctrl->trigger (); ++ } ++ ++ /* Called when the timer goes off. Stop thread M_THREAD. */ ++ void ++ trigger () ++ { ++ m_triggered = true; ++ ++ scoped_disable_commit_resumed disable_commit_resumed ("infcall timeout"); ++ ++ infcall_debug_printf ("Stopping thread %s", ++ m_thread->ptid.to_string ().c_str ()); ++ target_stop (m_thread->ptid); ++ } ++}; ++ + /* Subroutine of call_function_by_hand to simplify it. + Start up the inferior and wait for it to stop. + Return the exception if there's an error, or an exception with +@@ -630,13 +756,15 @@ call_thread_fsm::should_notify_stop () + + static struct gdb_exception + run_inferior_call (std::unique_ptr sm, +- struct thread_info *call_thread, CORE_ADDR real_pc) ++ struct thread_info *call_thread, CORE_ADDR real_pc, ++ bool *timed_out_p) + { + INFCALL_SCOPED_DEBUG_ENTER_EXIT; + + struct gdb_exception caught_error; + ptid_t call_thread_ptid = call_thread->ptid; + int was_running = call_thread->state == THREAD_RUNNING; ++ *timed_out_p = false; + + infcall_debug_printf ("call function at %s in thread %s, was_running = %d", + core_addr_to_string (real_pc), +@@ -681,11 +809,23 @@ run_inferior_call (std::unique_ptr sm, + infrun_debug_show_threads ("non-exited threads after proceed for inferior-call", + all_non_exited_threads ()); + ++ /* Setup a timer (if possible, and if the settings allow) to prevent ++ the inferior call running forever. */ ++ bool direct_call_p = !call_thread->control.in_cond_eval; ++ infcall_timer_controller infcall_timer (call_thread, direct_call_p); ++ + /* Inferior function calls are always synchronous, even if the + target supports asynchronous execution. */ + wait_sync_command_done (); + +- infcall_debug_printf ("inferior call completed successfully"); ++ /* If the timer triggered then the inferior call failed. */ ++ if (infcall_timer.triggered_p ()) ++ { ++ infcall_debug_printf ("inferior call timed out"); ++ *timed_out_p = true; ++ } ++ else ++ infcall_debug_printf ("inferior call completed successfully"); + } + catch (gdb_exception &e) + { +@@ -1357,6 +1497,10 @@ call_function_by_hand_dummy (struct value *function, + scoped_restore restore_stopped_by_random_signal + = make_scoped_restore (&stopped_by_random_signal, 0); + ++ /* Set to true by the call to run_inferior_call below if the inferior ++ call is artificially interrupted by GDB due to taking too long. */ ++ bool timed_out_p = false; ++ + /* - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP - SNIP - + If you're looking to implement asynchronous dummy-frames, then + just below is the place to chop this function in two.. */ +@@ -1383,7 +1527,8 @@ call_function_by_hand_dummy (struct value *function, + struct_addr); + { + std::unique_ptr sm_up (sm); +- e = run_inferior_call (std::move (sm_up), call_thread.get (), real_pc); ++ e = run_inferior_call (std::move (sm_up), call_thread.get (), real_pc, ++ &timed_out_p); + } + + if (e.reason < 0) +@@ -1535,7 +1680,10 @@ When the function is done executing, GDB will silently stop."), + std::string name = get_function_name (funaddr, name_buf, + sizeof (name_buf)); + +- if (stopped_by_random_signal) ++ /* If the inferior call timed out then it will have been interrupted ++ by a signal, but we want to report this differently to the user, ++ which is done later in this function. */ ++ if (stopped_by_random_signal && !timed_out_p) + { + /* We stopped inside the FUNCTION because of a random + signal. Further execution of the FUNCTION is not +@@ -1586,6 +1734,36 @@ GDB remains in the frame where the signal was received.\n\ + To change this behavior use \"set unwindonsignal on\".\n\ + Evaluation of the expression containing the function\n\ + (%s) will be abandoned.\n\ ++When the function is done executing, GDB will silently stop."), ++ name.c_str ()); ++ } ++ } ++ ++ if (timed_out_p) ++ { ++ /* A timeout results in a signal being sent to the inferior. */ ++ gdb_assert (stopped_by_random_signal); ++ ++ /* Indentation is weird here. A later patch is going to move the ++ following block into an if/else, so I'm leaving the indentation ++ here to minimise the later patch. ++ ++ Also, the error message used below refers to 'set ++ unwind-on-timeout' which doesn't exist yet. This will be added ++ in a later commit, I'm leaving this in for now to minimise the ++ churn caused by the commit that adds unwind-on-timeout. */ ++ { ++ /* The user wants to stay in the frame where we stopped ++ (default). Discard inferior status, we're not at the same ++ point we started at. */ ++ discard_infcall_control_state (inf_status.release ()); ++ ++ error (_("\ ++The program being debugged timed out while in a function called from GDB.\n\ ++GDB remains in the frame where the timeout occurred.\n\ ++To change this behavior use \"set unwind-on-timeout on\".\n\ ++Evaluation of the expression containing the function\n\ ++(%s) will be abandoned.\n\ + When the function is done executing, GDB will silently stop."), + name.c_str ()); + } +@@ -1699,6 +1877,30 @@ The default is to unwind the frame."), + show_unwind_on_terminating_exception_p, + &setlist, &showlist); + ++ add_setshow_uinteger_cmd ("direct-call-timeout", no_class, ++ &direct_call_timeout, _("\ ++Set the timeout, for direct calls to inferior function calls."), _("\ ++Show the timeout, for direct calls to inferior function calls."), _("\ ++If running on a target that supports, and is running in, async mode\n\ ++then this timeout is used for any inferior function calls triggered\n\ ++directly from the prompt, i.e. from a 'call' or 'print' command. The\n\ ++timeout is specified in seconds."), ++ nullptr, ++ show_direct_call_timeout, ++ &setlist, &showlist); ++ ++ add_setshow_uinteger_cmd ("indirect-call-timeout", no_class, ++ &indirect_call_timeout, _("\ ++Set the timeout, for indirect calls to inferior function calls."), _("\ ++Show the timeout, for indirect calls to inferior function calls."), _("\ ++If running on a target that supports, and is running in, async mode\n\ ++then this timeout is used for any inferior function calls triggered\n\ ++indirectly, i.e. being made as part of a breakpoint, or watchpoint,\n\ ++condition expression. The timeout is specified in seconds."), ++ nullptr, ++ show_indirect_call_timeout, ++ &setlist, &showlist); ++ + add_setshow_boolean_cmd + ("infcall", class_maintenance, &debug_infcall, + _("Set inferior call debugging."), +diff --git a/gdb/testsuite/gdb.base/help.exp b/gdb/testsuite/gdb.base/help.exp +--- a/gdb/testsuite/gdb.base/help.exp ++++ b/gdb/testsuite/gdb.base/help.exp +@@ -121,7 +121,7 @@ gdb_test "help info bogus-gdb-command" "Undefined info command: \"bogus-gdb-comm + gdb_test "help gotcha" "Undefined command: \"gotcha\"\. Try \"help\"\." + + # Test apropos regex. +-gdb_test "apropos \\\(print\[\^\[ bsiedf\\\".-\]\\\)" "handle -- Specify how to handle signals\." ++gdb_test "apropos \\\(print\[\^\[ bsiedf\\\"'.-\]\\\)" "handle -- Specify how to handle signals\." + # Test apropos >1 word string. + gdb_test "apropos handle signal" "handle -- Specify how to handle signals\." + # Test apropos apropos. +diff --git a/gdb/testsuite/gdb.base/infcall-timeout.c b/gdb/testsuite/gdb.base/infcall-timeout.c +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.base/infcall-timeout.c +@@ -0,0 +1,36 @@ ++/* Copyright 2022-2024 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include ++ ++/* This function is called from GDB. */ ++int ++function_that_never_returns () ++{ ++ while (1) ++ sleep (1); ++ ++ return 0; ++} ++ ++int ++main () ++{ ++ alarm (300); ++ ++ return 0; ++} +diff --git a/gdb/testsuite/gdb.base/infcall-timeout.exp b/gdb/testsuite/gdb.base/infcall-timeout.exp +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.base/infcall-timeout.exp +@@ -0,0 +1,94 @@ ++# Copyright 2022-2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++ ++# Test GDB's direct-call-timeout setting, that is, ensure that if an ++# inferior function call, invoked from e.g. a 'print' command, takes ++# too long, then GDB can interrupt it, and return control to the user. ++ ++standard_testfile ++ ++if { [build_executable "failed to prepare" ${binfile} "${srcfile}" \ ++ {debug}] == -1 } { ++ return ++} ++ ++# Start GDB according to TARGET_ASYNC, TARGET_NON_STOP, and NON_STOP, ++# then adjust the direct-call-timeout, and make an inferior function ++# call that will never return. GDB should eventually timeout and stop ++# the inferior. ++proc run_test { target_async target_non_stop non_stop } { ++ save_vars { ::GDBFLAGS } { ++ append ::GDBFLAGS \ ++ " -ex \"maint set target-non-stop $target_non_stop\"" ++ append ::GDBFLAGS \ ++ " -ex \"set non-stop $non_stop\"" ++ append ::GDBFLAGS \ ++ " -ex \"maintenance set target-async ${target_async}\"" ++ ++ clean_restart ${::binfile} ++ } ++ ++ if {![runto_main]} { ++ return ++ } ++ ++ gdb_test_no_output "set direct-call-timeout 5" ++ ++ # When non-stop mode is off we get slightly different output from GDB. ++ if { ([target_info gdb_protocol] == "remote" ++ || [target_info gdb_protocol] == "extended-remote") ++ && !$target_non_stop } { ++ set stopped_line_pattern "Program received signal SIGINT, Interrupt\\." ++ } else { ++ set stopped_line_pattern "Program stopped\\." ++ } ++ ++ gdb_test "print function_that_never_returns ()" \ ++ [multi_line \ ++ $stopped_line_pattern \ ++ ".*" \ ++ "The program being debugged timed out while in a function called from GDB\\." \ ++ "GDB remains in the frame where the timeout occurred\\." \ ++ "To change this behavior use \"set unwind-on-timeout on\"\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(function_that_never_returns\\) will be abandoned\\." \ ++ "When the function is done executing, GDB will silently stop\\."] ++ ++ gdb_test "bt" ".* function_that_never_returns .*.*" ++} ++ ++foreach_with_prefix target_async { "on" "off" } { ++ ++ if { !$target_async } { ++ # GDB can't timeout while waiting for a thread if the target ++ # runs with async-mode turned off; once the target is running ++ # GDB is effectively blocked until the target stops for some ++ # reason. ++ continue ++ } ++ ++ foreach_with_prefix target_non_stop { "on" "off" } { ++ foreach_with_prefix non_stop { "on" "off" } { ++ if { $non_stop && !$target_non_stop } { ++ # It doesn't make sense to operate GDB in non-stop ++ # mode when the target has (in theory) non-stop mode ++ # disabled. ++ continue ++ } ++ ++ run_test $target_async $target_non_stop $non_stop ++ } ++ } ++} +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.c b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.c +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.c +@@ -0,0 +1,169 @@ ++/* This testcase is part of GDB, the GNU debugger. ++ ++ Copyright 2022-2024 Free Software Foundation, Inc. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define NUM_THREADS 5 ++ ++/* Semaphores, used to track when threads have started, and to control ++ when the threads finish. */ ++sem_t startup_semaphore; ++sem_t finish_semaphore; ++sem_t thread_1_semaphore; ++sem_t thread_2_semaphore; ++ ++/* Mutex to control when the first worker thread hit a breakpoint ++ location. */ ++pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER; ++ ++/* Global variable to poke, just so threads have something to do. */ ++volatile int global_var = 0; ++ ++int ++condition_func () ++{ ++ /* Let thread 2 run. */ ++ if (sem_post (&thread_2_semaphore) != 0) ++ abort (); ++ ++ /* Wait for thread 2 to complete its actions. */ ++ if (sem_wait (&thread_1_semaphore) != 0) ++ abort (); ++ ++ return 1; ++} ++ ++void ++do_segfault () ++{ ++ volatile int *p = 0; ++ *p = 0; /* Segfault here. */ ++} ++ ++void * ++worker_func (void *arg) ++{ ++ int tid = *((int *) arg); ++ ++ /* Let the main thread know that this worker has started. */ ++ if (sem_post (&startup_semaphore) != 0) ++ abort (); ++ ++ switch (tid) ++ { ++ case 0: ++ /* Wait for MUTEX to become available, then pass through the ++ conditional breakpoint location. */ ++ if (pthread_mutex_lock (&mutex) != 0) ++ abort (); ++ global_var = 99; /* Conditional breakpoint here. */ ++ if (pthread_mutex_unlock (&mutex) != 0) ++ abort (); ++ break; ++ ++ case 1: ++ if (sem_wait (&thread_2_semaphore) != 0) ++ abort (); ++ do_segfault (); ++ if (sem_post (&thread_1_semaphore) != 0) ++ abort (); ++ ++ /* Fall through. */ ++ default: ++ /* Wait until we are allowed to finish. */ ++ if (sem_wait (&finish_semaphore) != 0) ++ abort (); ++ break; ++ } ++} ++ ++void ++stop_marker () ++{ ++ global_var = 99; /* Stop marker. */ ++} ++ ++/* The main program entry point. */ ++ ++int ++main () ++{ ++ pthread_t threads[NUM_THREADS]; ++ int args[NUM_THREADS]; ++ void *retval; ++ ++ /* An alarm, just in case the thread deadlocks. */ ++ alarm (300); ++ ++ /* Semaphore initialization. */ ++ if (sem_init (&startup_semaphore, 0, 0) != 0) ++ abort (); ++ if (sem_init (&finish_semaphore, 0, 0) != 0) ++ abort (); ++ if (sem_init (&thread_1_semaphore, 0, 0) != 0) ++ abort (); ++ if (sem_init (&thread_2_semaphore, 0, 0) != 0) ++ abort (); ++ ++ /* Lock MUTEX, this prevents the first worker thread from rushing ahead. */ ++ if (pthread_mutex_lock (&mutex) != 0) ++ abort (); ++ ++ /* Worker thread creation. */ ++ for (int i = 0; i < NUM_THREADS; i++) ++ { ++ args[i] = i; ++ pthread_create (&threads[i], NULL, worker_func, &args[i]); ++ } ++ ++ /* Wait for every thread to start. */ ++ for (int i = 0; i < NUM_THREADS; i++) ++ { ++ if (sem_wait (&startup_semaphore) != 0) ++ abort (); ++ } ++ ++ /* Unlock the first thread so it can proceed. */ ++ if (pthread_mutex_unlock (&mutex) != 0) ++ abort (); ++ ++ /* Wait for the first thread only. */ ++ pthread_join (threads[0], &retval); ++ ++ /* Now post FINISH_SEMAPHORE to allow all the other threads to finish. */ ++ for (int i = 1; i < NUM_THREADS; i++) ++ sem_post (&finish_semaphore); ++ ++ /* Now wait for the remaining threads to complete. */ ++ for (int i = 1; i < NUM_THREADS; i++) ++ pthread_join (threads[i], &retval); ++ ++ /* Semaphore cleanup. */ ++ sem_destroy (&finish_semaphore); ++ sem_destroy (&startup_semaphore); ++ sem_destroy (&thread_1_semaphore); ++ sem_destroy (&thread_2_semaphore); ++ ++ stop_marker (); ++ ++ return 0; ++} +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.exp b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.exp +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.exp +@@ -0,0 +1,166 @@ ++# Copyright 2022-2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++ ++# Tests inferior calls executed from a breakpoint condition in ++# a multi-threaded program. ++# ++# This test has the inferior function call timeout, and checks how GDB ++# handles this situation. ++ ++standard_testfile ++ ++if { [build_executable "failed to prepare" ${binfile} "${srcfile}" \ ++ {debug pthreads}] } { ++ return ++} ++ ++set cond_bp_line [gdb_get_line_number "Conditional breakpoint here"] ++set final_bp_line [gdb_get_line_number "Stop marker"] ++set segfault_line [gdb_get_line_number "Segfault here"] ++ ++# Setup GDB based on TARGET_ASYNC, TARGET_NON_STOP, and NON_STOP. ++# Setup some breakpoints in the inferior, one of which has an inferior ++# call within its condition. ++# ++# Continue GDB, the breakpoint with inferior call will be hit, but the ++# inferior call will never return. We expect GDB to timeout. ++# ++# The reason that the inferior call never completes is that a second ++# thread, on which the inferior call relies, either hits a breakpoint ++# (when OTHER_THREAD_BP is true), or crashes (when OTHER_THREAD_BP is ++# false). ++proc run_test { target_async target_non_stop non_stop other_thread_bp } { ++ save_vars { ::GDBFLAGS } { ++ append ::GDBFLAGS " -ex \"maint set target-non-stop $target_non_stop\"" ++ append ::GDBFLAGS " -ex \"maint non-stop $non_stop\"" ++ append ::GDBFLAGS " -ex \"maintenance set target-async ${target_async}\"" ++ ++ clean_restart ${::binfile} ++ } ++ ++ if {![runto_main]} { ++ return ++ } ++ ++ # The default timeout for indirect inferior calls (e.g. inferior ++ # calls for conditional breakpoint expressions) is pretty high. ++ # We don't want the test to take too long, so reduce this. ++ # ++ # However, the test relies on a second thread hitting some event ++ # (either a breakpoint or signal) before this timeout expires. ++ # ++ # There is a chance that on a really slow system this might not ++ # happen, in which case the test might fail. ++ # ++ # However, we still allocate 5 seconds, which feels like it should ++ # be enough time in most cases, but maybe we need to do something ++ # smarter here? Possibly we could have some initial run where the ++ # inferior doesn't timeout, but does perform the same interaction ++ # between threads, we could time that, and use that as the basis ++ # for this timeout. For now though, we just hope 5 seconds is ++ # enough. ++ gdb_test_no_output "set indirect-call-timeout 5" ++ ++ gdb_breakpoint \ ++ "${::srcfile}:${::cond_bp_line} if (condition_func ())" ++ set bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for conditional breakpoint"] ++ ++ gdb_breakpoint "${::srcfile}:${::final_bp_line}" ++ set final_bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for final breakpoint"] ++ ++ # The thread performing an inferior call relies on a second ++ # thread. The second thread will segfault unless it hits a ++ # breakpoint first. In either case the initial thread will not ++ # complete its inferior call. ++ if { $other_thread_bp } { ++ gdb_breakpoint "${::srcfile}:${::segfault_line}" ++ set segfault_bp_num [get_integer_valueof "\$bpnum" "*UNKNOWN*" \ ++ "get number for segfault breakpoint"] ++ } ++ ++ # When non-stop mode is off we get slightly different output from GDB. ++ if { ([target_info gdb_protocol] == "remote" ++ || [target_info gdb_protocol] == "extended-remote") ++ && !$target_non_stop} { ++ set stopped_line_pattern "Thread ${::decimal} \"\[^\r\n\"\]+\" received signal SIGINT, Interrupt\\." ++ } else { ++ set stopped_line_pattern "Thread ${::decimal} \"\[^\r\n\"\]+\" stopped\\." ++ } ++ ++ gdb_test "continue" \ ++ [multi_line \ ++ $stopped_line_pattern \ ++ ".*" \ ++ "Error in testing condition for breakpoint ${bp_num}:" \ ++ "The program being debugged timed out while in a function called from GDB\\." \ ++ "GDB remains in the frame where the timeout occurred\\." \ ++ "To change this behavior use \"set unwind-on-timeout on\"\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(condition_func\\) will be abandoned\\." \ ++ "When the function is done executing, GDB will silently stop\\."] \ ++ "expected timeout waiting for inferior call to complete" ++ ++ # Remember that other thread that either crashed (with a segfault) ++ # or hit a breakpoint? Now that the inferior call has timed out, ++ # if we try to resume then we should see the pending event from ++ # that other thread. ++ if { $other_thread_bp } { ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "" \ ++ "Thread ${::decimal} \"\[^\"\r\n\]+\" hit Breakpoint ${segfault_bp_num}, do_segfault \[^\r\n\]+:${::segfault_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Segfault here\[^\r\n\]+"] \ ++ "hit the segfault breakpoint" ++ } else { ++ gdb_test "continue" \ ++ [multi_line \ ++ "Continuing\\." \ ++ ".*" \ ++ "Thread ${::decimal} \"infcall-from-bp\" received signal SIGSEGV, Segmentation fault\\." \ ++ "\\\[Switching to Thread \[^\r\n\]+\\\]" \ ++ "${::hex} in do_segfault \\(\\) at \[^\r\n\]+:${::segfault_line}" \ ++ "${::decimal}\\s+\[^\r\n\]+Segfault here\[^\r\n\]+"] \ ++ "hit the segfault" ++ } ++} ++ ++foreach_with_prefix target_async {"on" "off" } { ++ ++ if { !$target_async } { ++ # GDB can't timeout while waiting for a thread if the target ++ # runs with async-mode turned off; once the target is running ++ # GDB is effectively blocked until the target stops for some ++ # reason. ++ continue ++ } ++ ++ foreach_with_prefix target_non_stop {"off" "on"} { ++ foreach_with_prefix non_stop {"off" "on"} { ++ if { $non_stop && !$target_non_stop } { ++ # It doesn't make sense to operate GDB in non-stop ++ # mode when the target has (in theory) non-stop mode ++ # disabled. ++ continue ++ } ++ foreach_with_prefix other_thread_bp { true false } { ++ run_test $target_async $target_non_stop $non_stop $other_thread_bp ++ } ++ } ++ } ++} diff --git a/gdb-rhel-13298-inferior-funcall-bp-condition-4-of-5.patch b/gdb-rhel-13298-inferior-funcall-bp-condition-4-of-5.patch new file mode 100644 index 0000000..27a0e11 --- /dev/null +++ b/gdb-rhel-13298-inferior-funcall-bp-condition-4-of-5.patch @@ -0,0 +1,413 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andrew Burgess +Date: Wed, 18 Jan 2023 10:17:57 +0000 +Subject: gdb-rhel-13298-inferior-funcall-bp-condition-4-of-5.patch + +;;gdb: introduce unwind-on-timeout setting +;;(Andrew Burgess, RHEL-13298) + +Now that inferior function calls can timeout (see the recent +introduction of direct-call-timeout and indirect-call-timeout), this +commit adds a new setting unwind-on-timeout. + +This new setting is just like the existing unwindonsignal and +unwind-on-terminating-exception, but the new setting will cause GDB to +unwind the stack if an inferior function call times out. + +The existing inferior function call timeout tests have been updated to +cover the new setting. + +Reviewed-By: Eli Zaretskii +Tested-By: Luis Machado +Tested-By: Keith Seitz + +diff --git a/gdb/NEWS b/gdb/NEWS +--- a/gdb/NEWS ++++ b/gdb/NEWS +@@ -72,6 +72,15 @@ show indirect-call-timeout + ignored, GDB will wait indefinitely for an inferior function to + complete, unless interrupted by the user using Ctrl-C. + ++set unwind-on-timeout on|off ++show unwind-on-timeout ++ These commands control whether GDB should unwind the stack when a ++ timeout occurs during an inferior function call. The default is ++ off, in which case the inferior will remain in the frame where the ++ timeout occurred. When on, GDB will unwind the stack removing the ++ dummy frame that was added for the inferior call, and restoring the ++ inferior state to how it was before the inferior call started. ++ + * New features in the GDB remote stub, GDBserver + + ** The --remote-debug and --event-loop-debug command line options +diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo +--- a/gdb/doc/gdb.texinfo ++++ b/gdb/doc/gdb.texinfo +@@ -20932,6 +20932,22 @@ the default C@t{++} exception handler and the inferior terminated. + Show the current setting of stack unwinding in the functions called by + @value{GDBN}. + ++@anchor{set unwind-on-timeout} ++@item set unwind-on-timeout ++@kindex set unwind-on-timeout ++@cindex unwind stack in called functions when timing out ++@cindex call dummy stack unwinding on timeout. ++Set unwinding of the stack if a function called from @value{GDBN} ++times out. If set to @code{off} (the default), @value{GDBN} stops in ++the frame where the timeout occurred. If set to @code{on}, ++@value{GDBN} unwinds the stack it created for the call and restores ++the context to what it was before the call. ++ ++@item show unwind-on-timeout ++@kindex show unwind-on-timeout ++Show whether @value{GDBN} will unwind the stack if a function called ++from @value{GDBN} times out. ++ + @item set may-call-functions + @kindex set may-call-functions + @cindex disabling calling functions in the program +@@ -20963,11 +20979,11 @@ call by typing the interrupt character (often @kbd{Ctrl-c}). + + If a called function is interrupted for any reason, including hitting + a breakpoint, or triggering a watchpoint, and the stack is not unwound +-due to @code{set unwind-on-terminating-exception on} or @code{set +-unwindonsignal on} (@pxref{stack unwind settings}), +-then the dummy-frame, created by @value{GDBN} to facilitate the call +-to the program function, will be visible in the backtrace, for example +-frame @code{#3} in the following backtrace: ++due to @code{set unwind-on-terminating-exception on}, @code{set ++unwind-on-timeout on}, or @code{set unwindonsignal on} (@pxref{stack ++unwind settings}), then the dummy-frame, created by @value{GDBN} to ++facilitate the call to the program function, will be visible in the ++backtrace, for example frame @code{#3} in the following backtrace: + + @smallexample + (@value{GDBP}) backtrace +@@ -20992,6 +21008,11 @@ Execution}) @value{GDBN} can place a timeout on any functions called + from @value{GDBN}. If the timeout expires and the function call is + still ongoing, then @value{GDBN} will interrupt the program. + ++If a function called from @value{GDBN} is interrupted by a timeout, ++then by default the inferior is left in the frame where the timeout ++occurred, this behaviour can be adjusted with @samp{set ++unwind-on-timeout} (@pxref{set unwind-on-timeout}). ++ + For targets that don't support asynchronous execution + (@pxref{Background Execution}) then timeouts for functions called from + @value{GDBN} are not supported, the timeout settings described below +diff --git a/gdb/infcall.c b/gdb/infcall.c +--- a/gdb/infcall.c ++++ b/gdb/infcall.c +@@ -218,6 +218,27 @@ show_unwind_on_terminating_exception_p (struct ui_file *file, int from_tty, + value); + } + ++/* This boolean tells GDB what to do if an inferior function, called from ++ GDB, times out. If true, GDB unwinds the stack and restores the context ++ to what it was before the call. When false, GDB leaves the thread as it ++ is at the point of the timeout. ++ ++ The default is to stop in the frame where the timeout occurred. */ ++ ++static bool unwind_on_timeout_p = false; ++ ++/* Implement 'show unwind-on-timeout'. */ ++ ++static void ++show_unwind_on_timeout_p (struct ui_file *file, int from_tty, ++ struct cmd_list_element *c, const char *value) ++{ ++ gdb_printf (file, ++ _("Unwinding of stack if a timeout occurs " ++ "while in a call dummy is %s.\n"), ++ value); ++} ++ + /* Perform the standard coercions that are specified + for arguments to be passed to C, Ada or Fortran functions. + +@@ -574,6 +595,16 @@ struct call_thread_fsm : public thread_fsm + bool should_stop (struct thread_info *thread) override; + + bool should_notify_stop () override; ++ ++ /* Record that this thread timed out while performing an infcall. */ ++ void timed_out () ++ { ++ m_timed_out = true; ++ } ++ ++private: ++ /* Set true if the thread timed out while performing an infcall. */ ++ bool m_timed_out = false; + }; + + /* Allocate a new call_thread_fsm object. */ +@@ -649,7 +680,8 @@ call_thread_fsm::should_notify_stop () + + infcall_debug_printf ("inferior call didn't complete fully"); + +- if (stopped_by_random_signal && unwind_on_signal_p) ++ if ((stopped_by_random_signal && unwind_on_signal_p) ++ || (m_timed_out && unwind_on_timeout_p)) + { + infcall_debug_printf ("unwind-on-signal is on, don't notify"); + return false; +@@ -742,6 +774,9 @@ struct infcall_timer_controller + + infcall_debug_printf ("Stopping thread %s", + m_thread->ptid.to_string ().c_str ()); ++ call_thread_fsm *fsm ++ = gdb::checked_static_cast (m_thread->thread_fsm ()); ++ fsm->timed_out (); + target_stop (m_thread->ptid); + } + }; +@@ -1744,14 +1779,27 @@ When the function is done executing, GDB will silently stop."), + /* A timeout results in a signal being sent to the inferior. */ + gdb_assert (stopped_by_random_signal); + +- /* Indentation is weird here. A later patch is going to move the +- following block into an if/else, so I'm leaving the indentation +- here to minimise the later patch. ++ if (unwind_on_timeout_p) ++ { ++ /* The user wants the context restored. */ ++ ++ /* We must get back to the frame we were before the ++ dummy call. */ ++ dummy_frame_pop (dummy_id, call_thread.get ()); + +- Also, the error message used below refers to 'set +- unwind-on-timeout' which doesn't exist yet. This will be added +- in a later commit, I'm leaving this in for now to minimise the +- churn caused by the commit that adds unwind-on-timeout. */ ++ /* We also need to restore inferior status to that before the ++ dummy call. */ ++ restore_infcall_control_state (inf_status.release ()); ++ ++ error (_("\ ++The program being debugged timed out while in a function called from GDB.\n\ ++GDB has restored the context to what it was before the call.\n\ ++To change this behavior use \"set unwind-on-timeout off\".\n\ ++Evaluation of the expression containing the function\n\ ++(%s) will be abandoned."), ++ name.c_str ()); ++ } ++ else + { + /* The user wants to stay in the frame where we stopped + (default). Discard inferior status, we're not at the same +@@ -1877,6 +1925,20 @@ The default is to unwind the frame."), + show_unwind_on_terminating_exception_p, + &setlist, &showlist); + ++ add_setshow_boolean_cmd ("unwind-on-timeout", no_class, ++ &unwind_on_timeout_p, _("\ ++Set unwinding of stack if a timeout occurs while in a call dummy."), _("\ ++Show unwinding of stack if a timeout occurs while in a call dummy."), ++ _("\ ++The unwind on timeout flag lets the user determine what gdb should do if\n\ ++gdb times out while in a function called from gdb. If set, gdb unwinds\n\ ++the stack and restores the context to what it was before the call. If\n\ ++unset, gdb leaves the inferior in the frame where the timeout occurred.\n\ ++The default is to stop in the frame where the timeout occurred."), ++ NULL, ++ show_unwind_on_timeout_p, ++ &setlist, &showlist); ++ + add_setshow_uinteger_cmd ("direct-call-timeout", no_class, + &direct_call_timeout, _("\ + Set the timeout, for direct calls to inferior function calls."), _("\ +diff --git a/gdb/testsuite/gdb.base/infcall-timeout.exp b/gdb/testsuite/gdb.base/infcall-timeout.exp +--- a/gdb/testsuite/gdb.base/infcall-timeout.exp ++++ b/gdb/testsuite/gdb.base/infcall-timeout.exp +@@ -28,7 +28,11 @@ if { [build_executable "failed to prepare" ${binfile} "${srcfile}" \ + # then adjust the direct-call-timeout, and make an inferior function + # call that will never return. GDB should eventually timeout and stop + # the inferior. +-proc run_test { target_async target_non_stop non_stop } { ++# ++# When UNWIND is "off" the inferior wil be left in the frame where the ++# timeout occurs, otherwise, when UNWIND is "on", GDB should unwind ++# back to the frame where the inferior call was made. ++proc run_test { target_async target_non_stop non_stop unwind } { + save_vars { ::GDBFLAGS } { + append ::GDBFLAGS \ + " -ex \"maint set target-non-stop $target_non_stop\"" +@@ -45,28 +49,43 @@ proc run_test { target_async target_non_stop non_stop } { + } + + gdb_test_no_output "set direct-call-timeout 5" ++ gdb_test_no_output "set unwind-on-timeout $unwind" ++ ++ if { $unwind } { ++ gdb_test "print function_that_never_returns ()" \ ++ [multi_line \ ++ "The program being debugged timed out while in a function called from GDB\\." \ ++ "GDB has restored the context to what it was before the call\\." \ ++ "To change this behavior use \"set unwind-on-timeout off\"\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(function_that_never_returns\\) will be abandoned\\."] + +- # When non-stop mode is off we get slightly different output from GDB. +- if { ([target_info gdb_protocol] == "remote" +- || [target_info gdb_protocol] == "extended-remote") +- && !$target_non_stop } { +- set stopped_line_pattern "Program received signal SIGINT, Interrupt\\." ++ gdb_test "bt" \ ++ "#0\\s+main \\(\\).*" + } else { +- set stopped_line_pattern "Program stopped\\." +- } ++ # When non-stop mode is off we get slightly different output from GDB. ++ if { ([target_info gdb_protocol] == "remote" ++ || [target_info gdb_protocol] == "extended-remote") ++ && !$target_non_stop } { ++ set stopped_line_pattern "Program received signal SIGINT, Interrupt\\." ++ } else { ++ set stopped_line_pattern "Program stopped\\." ++ } + +- gdb_test "print function_that_never_returns ()" \ +- [multi_line \ +- $stopped_line_pattern \ +- ".*" \ +- "The program being debugged timed out while in a function called from GDB\\." \ +- "GDB remains in the frame where the timeout occurred\\." \ +- "To change this behavior use \"set unwind-on-timeout on\"\\." \ +- "Evaluation of the expression containing the function" \ +- "\\(function_that_never_returns\\) will be abandoned\\." \ +- "When the function is done executing, GDB will silently stop\\."] +- +- gdb_test "bt" ".* function_that_never_returns .*.*" ++ gdb_test "print function_that_never_returns ()" \ ++ [multi_line \ ++ $stopped_line_pattern \ ++ ".*" \ ++ "The program being debugged timed out while in a function called from GDB\\." \ ++ "GDB remains in the frame where the timeout occurred\\." \ ++ "To change this behavior use \"set unwind-on-timeout on\"\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(function_that_never_returns\\) will be abandoned\\." \ ++ "When the function is done executing, GDB will silently stop\\."] ++ ++ gdb_test "bt" \ ++ ".* function_that_never_returns .*.*" ++ } + } + + foreach_with_prefix target_async { "on" "off" } { +@@ -88,7 +107,9 @@ foreach_with_prefix target_async { "on" "off" } { + continue + } + +- run_test $target_async $target_non_stop $non_stop ++ foreach_with_prefix unwind { "on" "off" } { ++ run_test $target_async $target_non_stop $non_stop $unwind ++ } + } + } + } +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.exp b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.exp +--- a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.exp ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-timeout.exp +@@ -41,7 +41,12 @@ set segfault_line [gdb_get_line_number "Segfault here"] + # thread, on which the inferior call relies, either hits a breakpoint + # (when OTHER_THREAD_BP is true), or crashes (when OTHER_THREAD_BP is + # false). +-proc run_test { target_async target_non_stop non_stop other_thread_bp } { ++# ++# When UNWIND is "on" GDB will unwind the thread which performed the ++# inferior function call back to the state where the inferior call was ++# made (when the inferior call times out). Otherwise, when UNWIND is ++# "off", the inferior is left in the frame where the timeout occurred. ++proc run_test { target_async target_non_stop non_stop other_thread_bp unwind } { + save_vars { ::GDBFLAGS } { + append ::GDBFLAGS " -ex \"maint set target-non-stop $target_non_stop\"" + append ::GDBFLAGS " -ex \"maint non-stop $non_stop\"" +@@ -72,6 +77,7 @@ proc run_test { target_async target_non_stop non_stop other_thread_bp } { + # for this timeout. For now though, we just hope 5 seconds is + # enough. + gdb_test_no_output "set indirect-call-timeout 5" ++ gdb_test_no_output "set unwind-on-timeout $unwind" + + gdb_breakpoint \ + "${::srcfile}:${::cond_bp_line} if (condition_func ())" +@@ -92,27 +98,43 @@ proc run_test { target_async target_non_stop non_stop other_thread_bp } { + "get number for segfault breakpoint"] + } + +- # When non-stop mode is off we get slightly different output from GDB. +- if { ([target_info gdb_protocol] == "remote" +- || [target_info gdb_protocol] == "extended-remote") +- && !$target_non_stop} { +- set stopped_line_pattern "Thread ${::decimal} \"\[^\r\n\"\]+\" received signal SIGINT, Interrupt\\." ++ if { $unwind } { ++ gdb_test "continue" \ ++ [multi_line \ ++ "Error in testing condition for breakpoint ${bp_num}:" \ ++ "The program being debugged timed out while in a function called from GDB\\." \ ++ "GDB has restored the context to what it was before the call\\." \ ++ "To change this behavior use \"set unwind-on-timeout off\"\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(condition_func\\) will be abandoned\\." \ ++ "" \ ++ "Thread ${::decimal}\[^\r\n\]*hit Breakpoint ${bp_num}, \[^\r\n\]+" \ ++ "\[^\r\n\]+ Conditional breakpoint here\\. \[^\r\n\]+"] \ ++ "expected timeout waiting for inferior call to complete" + } else { +- set stopped_line_pattern "Thread ${::decimal} \"\[^\r\n\"\]+\" stopped\\." +- } ++ # When non-stop mode is off we get slightly different output from GDB. ++ if { ([target_info gdb_protocol] == "remote" ++ || [target_info gdb_protocol] == "extended-remote") ++ && !$target_non_stop} { ++ set stopped_line_pattern \ ++ "Thread ${::decimal} \"\[^\r\n\"\]+\" received signal SIGINT, Interrupt\\." ++ } else { ++ set stopped_line_pattern "Thread ${::decimal} \"\[^\r\n\"\]+\" stopped\\." ++ } + +- gdb_test "continue" \ +- [multi_line \ +- $stopped_line_pattern \ +- ".*" \ +- "Error in testing condition for breakpoint ${bp_num}:" \ +- "The program being debugged timed out while in a function called from GDB\\." \ +- "GDB remains in the frame where the timeout occurred\\." \ +- "To change this behavior use \"set unwind-on-timeout on\"\\." \ +- "Evaluation of the expression containing the function" \ +- "\\(condition_func\\) will be abandoned\\." \ +- "When the function is done executing, GDB will silently stop\\."] \ +- "expected timeout waiting for inferior call to complete" ++ gdb_test "continue" \ ++ [multi_line \ ++ "$stopped_line_pattern" \ ++ ".*" \ ++ "Error in testing condition for breakpoint ${bp_num}:" \ ++ "The program being debugged timed out while in a function called from GDB\\." \ ++ "GDB remains in the frame where the timeout occurred\\." \ ++ "To change this behavior use \"set unwind-on-timeout on\"\\." \ ++ "Evaluation of the expression containing the function" \ ++ "\\(condition_func\\) will be abandoned\\." \ ++ "When the function is done executing, GDB will silently stop\\."] \ ++ "expected timeout waiting for inferior call to complete" ++ } + + # Remember that other thread that either crashed (with a segfault) + # or hit a breakpoint? Now that the inferior call has timed out, +@@ -158,8 +180,11 @@ foreach_with_prefix target_async {"on" "off" } { + # disabled. + continue + } +- foreach_with_prefix other_thread_bp { true false } { +- run_test $target_async $target_non_stop $non_stop $other_thread_bp ++ foreach_with_prefix unwind {"off" "on"} { ++ foreach_with_prefix other_thread_bp { true false } { ++ run_test $target_async $target_non_stop $non_stop \ ++ $other_thread_bp $unwind ++ } + } + } + } diff --git a/gdb-rhel-13298-inferior-funcall-bp-condition-5-of-5.patch b/gdb-rhel-13298-inferior-funcall-bp-condition-5-of-5.patch new file mode 100644 index 0000000..9dcaeac --- /dev/null +++ b/gdb-rhel-13298-inferior-funcall-bp-condition-5-of-5.patch @@ -0,0 +1,467 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andrew Burgess +Date: Wed, 18 Jan 2023 12:09:05 +0000 +Subject: gdb-rhel-13298-inferior-funcall-bp-condition-5-of-5.patch + +;;gdb: rename unwindonsignal to unwind-on-signal +;;(Andrew Burgess, RHEL-13298) + +We now have unwind-on-timeout and unwind-on-terminating-exception, and +then the odd one out unwindonsignal. + +I'm not a great fan of these squashed together command names, so in +this commit I propose renaming this to unwind-on-signal. + +Obviously I've added the hidden alias unwindonsignal so any existing +GDB scripts will keep working. + +There's one test that I've extended to test the alias works, but in +most of the other test scripts I've changed over to use the new name. + +The docs are updated to reference the new name. + +Reviewed-By: Eli Zaretskii +Tested-By: Luis Machado +Tested-By: Keith Seitz + +diff --git a/gdb/NEWS b/gdb/NEWS +--- a/gdb/NEWS ++++ b/gdb/NEWS +@@ -32,6 +32,10 @@ maintenance info line-table + if the line is considered the start of the epilgoue, and thus a point at + which the frame can be considered destroyed. + ++set unwindonsignal on|off ++show unwindonsignal ++ These commands are now aliases for the new set/show unwind-on-signal. ++ + * New commands + + info missing-debug-handler +@@ -81,6 +85,11 @@ show unwind-on-timeout + dummy frame that was added for the inferior call, and restoring the + inferior state to how it was before the inferior call started. + ++set unwind-on-signal on|off ++show unwind-on-signal ++ These new commands replaces the existing set/show unwindonsignal. The ++ old command is maintained as an alias. ++ + * New features in the GDB remote stub, GDBserver + + ** The --remote-debug and --event-loop-debug command line options +diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo +--- a/gdb/doc/gdb.texinfo ++++ b/gdb/doc/gdb.texinfo +@@ -20886,7 +20886,7 @@ value history. + It is possible for the function you call via the @code{print} or + @code{call} command to generate a signal (e.g., if there's a bug in + the function, or if you passed it incorrect arguments). What happens +-in that case is controlled by the @code{set unwindonsignal} command. ++in that case is controlled by the @code{set unwind-on-signal} command. + + Similarly, with a C@t{++} program it is possible for the function you + call via the @code{print} or @code{call} command to generate an +@@ -20900,7 +20900,8 @@ in that case is controlled by the + + @anchor{stack unwind settings} + @table @code +-@item set unwindonsignal ++@item set unwind-on-signal ++@kindex set unwind-on-signal + @kindex set unwindonsignal + @cindex unwind stack in called functions + @cindex call dummy stack unwinding +@@ -20911,11 +20912,18 @@ the context to what it was before the call. If set to off (the + default), @value{GDBN} stops in the frame where the signal was + received. + +-@item show unwindonsignal ++The command @code{set unwindonsignal} is an alias for this command, ++and is maintained for backward compatibility. ++ ++@item show unwind-on-signal ++@kindex show unwind-on-signal + @kindex show unwindonsignal + Show the current setting of stack unwinding in the functions called by + @value{GDBN}. + ++The command @code{show unwindonsignal} is an alias for this command, ++and is maintained for backward compatibility. ++ + @item set unwind-on-terminating-exception + @kindex set unwind-on-terminating-exception + @cindex unwind stack in called functions with unhandled exceptions +@@ -20980,7 +20988,7 @@ call by typing the interrupt character (often @kbd{Ctrl-c}). + If a called function is interrupted for any reason, including hitting + a breakpoint, or triggering a watchpoint, and the stack is not unwound + due to @code{set unwind-on-terminating-exception on}, @code{set +-unwind-on-timeout on}, or @code{set unwindonsignal on} (@pxref{stack ++unwind-on-timeout on}, or @code{set unwind-on-signal on} (@pxref{stack + unwind settings}), then the dummy-frame, created by @value{GDBN} to + facilitate the call to the program function, will be visible in the + backtrace, for example frame @code{#3} in the following backtrace: +diff --git a/gdb/infcall.c b/gdb/infcall.c +--- a/gdb/infcall.c ++++ b/gdb/infcall.c +@@ -1747,7 +1747,7 @@ When the function is done executing, GDB will silently stop."), + The program being debugged received signal %s, %s\n\ + while in a function called from GDB. GDB has restored the context\n\ + to what it was before the call. To change this behavior use\n\ +-\"set unwindonsignal off\". Evaluation of the expression containing\n\ ++\"set unwind-on-signal off\". Evaluation of the expression containing\n\ + the function (%s) will be abandoned."), + gdb_signal_to_name (stop_signal), + gdb_signal_to_string (stop_signal), +@@ -1766,7 +1766,7 @@ the function (%s) will be abandoned."), + error (_("\ + The program being debugged was signaled while in a function called from GDB.\n\ + GDB remains in the frame where the signal was received.\n\ +-To change this behavior use \"set unwindonsignal on\".\n\ ++To change this behavior use \"set unwind-on-signal on\".\n\ + Evaluation of the expression containing the function\n\ + (%s) will be abandoned.\n\ + When the function is done executing, GDB will silently stop."), +@@ -1898,17 +1898,22 @@ The default is to perform the conversion."), + show_coerce_float_to_double_p, + &setlist, &showlist); + +- add_setshow_boolean_cmd ("unwindonsignal", no_class, +- &unwind_on_signal_p, _("\ ++ set_show_commands setshow_unwind_on_signal_cmds ++ = add_setshow_boolean_cmd ("unwind-on-signal", no_class, ++ &unwind_on_signal_p, _("\ + Set unwinding of stack if a signal is received while in a call dummy."), _("\ + Show unwinding of stack if a signal is received while in a call dummy."), _("\ +-The unwindonsignal lets the user determine what gdb should do if a signal\n\ ++The unwind-on-signal lets the user determine what gdb should do if a signal\n\ + is received while in a function called from gdb (call dummy). If set, gdb\n\ + unwinds the stack and restore the context to what as it was before the call.\n\ + The default is to stop in the frame where the signal was received."), +- NULL, +- show_unwind_on_signal_p, +- &setlist, &showlist); ++ NULL, ++ show_unwind_on_signal_p, ++ &setlist, &showlist); ++ add_alias_cmd ("unwindonsignal", setshow_unwind_on_signal_cmds.set, ++ no_class, 1, &setlist); ++ add_alias_cmd ("unwindonsignal", setshow_unwind_on_signal_cmds.show, ++ no_class, 1, &showlist); + + add_setshow_boolean_cmd ("unwind-on-terminating-exception", no_class, + &unwind_on_terminating_exception_p, _("\ +diff --git a/gdb/testsuite/gdb.base/callfuncs.exp b/gdb/testsuite/gdb.base/callfuncs.exp +--- a/gdb/testsuite/gdb.base/callfuncs.exp ++++ b/gdb/testsuite/gdb.base/callfuncs.exp +@@ -46,7 +46,7 @@ proc do_function_calls {prototypes} { + + # If any of these calls segv we don't want to affect subsequent tests. + # E.g., we want to ensure register values are restored. +- gdb_test_no_output "set unwindonsignal on" ++ gdb_test_no_output "set unwind-on-signal on" + + gdb_test "p t_char_values(0,0)" " = 0" + gdb_test "p t_char_values('a','b')" " = 1" +@@ -237,7 +237,7 @@ proc do_function_calls {prototypes} { + "call inferior func with struct - returns char *" + + # Restore default value. +- gdb_test_no_output "set unwindonsignal off" ++ gdb_test_no_output "set unwind-on-signal off" + } + + # Procedure to get current content of all registers. +diff --git a/gdb/testsuite/gdb.base/infcall-failure.exp b/gdb/testsuite/gdb.base/infcall-failure.exp +--- a/gdb/testsuite/gdb.base/infcall-failure.exp ++++ b/gdb/testsuite/gdb.base/infcall-failure.exp +@@ -137,7 +137,7 @@ proc_with_prefix run_cond_hits_segfault_test { async_p non_stop_p } { + "Error in testing condition for breakpoint ${bp_1_num}:" \ + "The program being debugged was signaled while in a function called from GDB\\." \ + "GDB remains in the frame where the signal was received\\." \ +- "To change this behavior use \"set unwindonsignal on\"\\." \ ++ "To change this behavior use \"set unwind-on-signal on\"\\." \ + "Evaluation of the expression containing the function" \ + "\\(func_segfault\\) will be abandoned\\." \ + "When the function is done executing, GDB will silently stop\\."] +@@ -166,7 +166,7 @@ proc_with_prefix run_call_hits_segfault_test { async_p non_stop_p } { + "${::decimal}\\s+\[^\r\n\]+Segfault here\[^\r\n\]+" \ + "The program being debugged was signaled while in a function called from GDB\\." \ + "GDB remains in the frame where the signal was received\\." \ +- "To change this behavior use \"set unwindonsignal on\"\\." \ ++ "To change this behavior use \"set unwind-on-signal on\"\\." \ + "Evaluation of the expression containing the function" \ + "\\(func_segfault\\) will be abandoned\\." \ + "When the function is done executing, GDB will silently stop\\."] +diff --git a/gdb/testsuite/gdb.base/unwindonsignal.exp b/gdb/testsuite/gdb.base/unwindonsignal.exp +--- a/gdb/testsuite/gdb.base/unwindonsignal.exp ++++ b/gdb/testsuite/gdb.base/unwindonsignal.exp +@@ -34,13 +34,29 @@ gdb_test "break stop_here" "Breakpoint \[0-9\]* at .*" + gdb_test "continue" "Continuing.*Breakpoint \[0-9\]*, stop_here.*" \ + "continue to breakpoint at stop_here" + +-# Turn on unwindonsignal. +-gdb_test_no_output "set unwindonsignal on" \ +- "setting unwindonsignal" ++# Turn on unwind-on-signal. ++gdb_test_no_output "set unwind-on-signal on" \ ++ "setting unwind-on-signal" + +-gdb_test "show unwindonsignal" \ ++gdb_test "show unwind-on-signal" \ + "Unwinding of stack .* is on." \ +- "showing unwindonsignal" ++ "showing unwind-on-signal" ++ ++# For backward compatibility we maintain a 'unwindonsignal' alias for ++# 'unwind-on-signal', check it now. ++gdb_test "show unwindonsignal" \ ++ "Unwinding of stack .* is on\\." \ ++ "showing unwindonsignal alias" ++ ++gdb_test_no_output "set unwindonsignal off" \ ++ "setting unwindonsignal alias to off" ++ ++gdb_test "show unwind-on-signal" \ ++ "Unwinding of stack .* is off\\." \ ++ "showing unwind-on-signal after setting via alias" ++ ++gdb_test_no_output "set unwindonsignal on" \ ++ "setting unwindonsignal alias to on" + + # Call function (causing the program to get a signal), and see if gdb handles + # it properly. +@@ -49,7 +65,7 @@ if {[gdb_test "call gen_signal ()" \ + "The program being debugged received signal SIGABRT, Aborted" \ + "while in a function called from GDB\\. GDB has restored the context" \ + "to what it was before the call\\. To change this behavior use" \ +- "\"set unwindonsignal off\"\\. Evaluation of the expression containing" \ ++ "\"set unwind-on-signal off\"\\. Evaluation of the expression containing" \ + "the function \\(gen_signal\\) will be abandoned\\."] \ + "unwindonsignal, inferior function call signaled"] != 0} { + return 0 +@@ -58,15 +74,15 @@ if {[gdb_test "call gen_signal ()" \ + # Verify the stack got unwound. + gdb_test "bt" \ + "#0 *\[x0-9a-f in\]*stop_here \\(.*\\) at .*#1 *\[x0-9a-f in\]*main \\(.*\\) at .*" \ +- "unwindonsignal, stack unwound" ++ "stack unwound" + + # Verify the dummy frame got removed from dummy_frame_stack. + gdb_test_multiple "maint print dummy-frames" \ +- "unwindonsignal, dummy frame removed" { ++ "unwind-on-signal, dummy frame removed" { + -re "\[\r\n\]*.*stack=.*code=.*\[\r\n\]+$gdb_prompt $" { +- fail "unwindonsignal, dummy frame removed" ++ fail $gdb_test_name + } + -re "\[\r\n\]+$gdb_prompt $" { +- pass "unwindonsignal, dummy frame removed" ++ pass $gdb_test_name + } + } +diff --git a/gdb/testsuite/gdb.compile/compile-cplus.exp b/gdb/testsuite/gdb.compile/compile-cplus.exp +--- a/gdb/testsuite/gdb.compile/compile-cplus.exp ++++ b/gdb/testsuite/gdb.compile/compile-cplus.exp +@@ -131,13 +131,13 @@ gdb_test "return" "\r\n#0 main .*" "return" \ + "Make _gdb_expr\\(__gdb_regs\\*\\) return now\\? \\(y or n\\) " "y" + gdb_test "info sym $infcall_pc" "\r\nNo symbol matches .*" "info sym not found" + +-gdb_test_no_output "set unwindonsignal on" ++gdb_test_no_output "set unwind-on-signal on" + gdb_test "compile code *(volatile int *) 0 = 0;" \ + [multi_line \ + "The program being debugged received signal SIGSEGV, Segmentation fault" \ + "while in a function called from GDB\\. GDB has restored the context" \ + "to what it was before the call\\. To change this behavior use" \ +- "\"set unwindonsignal off\"\\. Evaluation of the expression containing" \ ++ "\"set unwind-on-signal off\"\\. Evaluation of the expression containing" \ + "the function \\(_gdb_expr\\(__gdb_regs\\*\\)\\) will be abandoned\\."] \ + "compile code segfault second" + +@@ -313,7 +313,7 @@ gdb_test "compile code static const int readonly = 1; *(int *) &readonly = 2;" \ + "The program being debugged received signal SIGSEGV, Segmentation fault" \ + "while in a function called from GDB\\. GDB has restored the context" \ + "to what it was before the call\\. To change this behavior use" \ +- "\"set unwindonsignal off\"\\. Evaluation of the expression containing" \ ++ "\"set unwind-on-signal off\"\\. Evaluation of the expression containing" \ + "the function \\(_gdb_expr\\(__gdb_regs\\*\\)\\) will be abandoned\\."] + gdb_test_no_output "set debug compile off" + +diff --git a/gdb/testsuite/gdb.compile/compile.exp b/gdb/testsuite/gdb.compile/compile.exp +--- a/gdb/testsuite/gdb.compile/compile.exp ++++ b/gdb/testsuite/gdb.compile/compile.exp +@@ -157,13 +157,13 @@ gdb_test "return" "\r\n#0 main .*" "return" \ + "Make _gdb_expr return now\\? \\(y or n\\) " "y" + gdb_test "info sym $infcall_pc" "\r\nNo symbol matches .*" "info sym not found" + +-gdb_test_no_output "set unwindonsignal on" ++gdb_test_no_output "set unwind-on-signal on" + gdb_test "compile code *(volatile int *) 0 = 0;" \ + [multi_line \ + "The program being debugged received signal SIGSEGV, Segmentation fault" \ + "while in a function called from GDB\\. GDB has restored the context" \ + "to what it was before the call\\. To change this behavior use" \ +- "\"set unwindonsignal off\"\\. Evaluation of the expression containing" \ ++ "\"set unwind-on-signal off\"\\. Evaluation of the expression containing" \ + "the function \\(_gdb_expr\\) will be abandoned\\."] \ + "compile code segfault second" + +@@ -321,7 +321,7 @@ gdb_test "compile code static const int readonly = 1; *(int *) &readonly = 2;" \ + "The program being debugged received signal SIGSEGV, Segmentation fault" \ + "while in a function called from GDB\\. GDB has restored the context" \ + "to what it was before the call\\. To change this behavior use" \ +- "\"set unwindonsignal off\"\\. Evaluation of the expression containing" \ ++ "\"set unwind-on-signal off\"\\. Evaluation of the expression containing" \ + "the function \\(_gdb_expr\\) will be abandoned\\."] + gdb_test_no_output "set debug compile off" + +diff --git a/gdb/testsuite/gdb.cp/gdb2495.exp b/gdb/testsuite/gdb.cp/gdb2495.exp +--- a/gdb/testsuite/gdb.cp/gdb2495.exp ++++ b/gdb/testsuite/gdb.cp/gdb2495.exp +@@ -98,10 +98,10 @@ if {![runto_main]} { + # behaviour; it should not. Test both on and off states. + + # Turn on unwind on signal behaviour. +-gdb_test_no_output "set unwindonsignal on" ++gdb_test_no_output "set unwind-on-signal on" + + # Check that it is turned on. +-gdb_test "show unwindonsignal" \ ++gdb_test "show unwind-on-signal" \ + "signal is received while in a call dummy is on.*" \ + "turn on unwind on signal" + +@@ -112,20 +112,20 @@ gdb_test "p exceptions.raise_signal(1)" \ + "The program being debugged received signal SIGABRT, Aborted" \ + "while in a function called from GDB\\. GDB has restored the context" \ + "to what it was before the call\\. To change this behavior use" \ +- "\"set unwindonsignal off\"\\. Evaluation of the expression containing" \ ++ "\"set unwind-on-signal off\"\\. Evaluation of the expression containing" \ + "the function \\(SimpleException::raise_signal\\(int\\)\\) will be abandoned\\."]\ +- "check for unwindonsignal off message" ++ "check for unwind-on-signal off message" + + # And reverse - turn off again. +-gdb_test_no_output "set unwindonsignal off" ++gdb_test_no_output "set unwind-on-signal off" + + # Check that it is actually turned off. +-gdb_test "show unwindonsignal" \ ++gdb_test "show unwind-on-signal" \ + "signal is received while in a call dummy is off.*" \ + "turn off unwind on signal" + + # Check to see if new behaviour interferes with + # normal signal handling in inferior function calls. + gdb_test "p exceptions.raise_signal(1)" \ +- "To change this behavior use \"set unwindonsignal on\".*" \ +- "check for unwindonsignal on message" ++ "To change this behavior use \"set unwind-on-signal on\".*" \ ++ "check for unwind-on-signal on message" +diff --git a/gdb/testsuite/gdb.fortran/function-calls.exp b/gdb/testsuite/gdb.fortran/function-calls.exp +--- a/gdb/testsuite/gdb.fortran/function-calls.exp ++++ b/gdb/testsuite/gdb.fortran/function-calls.exp +@@ -44,7 +44,7 @@ if {![runto [gdb_get_line_number "post_init"]]} { + } + + # Use inspired by gdb.base/callfuncs.exp. +-gdb_test_no_output "set unwindonsignal on" ++gdb_test_no_output "set unwind-on-signal on" + + # Baseline: function and subroutine call with no arguments. + gdb_test "p no_arg()" " = .TRUE." +diff --git a/gdb/testsuite/gdb.mi/mi-condbreak-fail.exp b/gdb/testsuite/gdb.mi/mi-condbreak-fail.exp +--- a/gdb/testsuite/gdb.mi/mi-condbreak-fail.exp ++++ b/gdb/testsuite/gdb.mi/mi-condbreak-fail.exp +@@ -43,7 +43,7 @@ proc run_test { unwind_on_signal } { + return + } + +- mi_gdb_test "-gdb-set unwindonsignal ${unwind_on_signal}" {\^done} \ ++ mi_gdb_test "-gdb-set unwind-on-signal ${unwind_on_signal}" {\^done} \ + "set unwind-on-signal" + + # Create the conditional breakpoint. +@@ -70,7 +70,7 @@ proc run_test { unwind_on_signal } { + "&\"The program being debugged received signal SIGSEGV, Segmentation fault\\\\n\"" \ + "&\"while in a function called from GDB\\. GDB has restored the context\\\\n\"" \ + "&\"to what it was before the call\\. To change this behavior use\\\\n\"" \ +- "&\"\\\\\"set unwindonsignal off\\\\\"\\. Evaluation of the expression containing\\\\n\"" \ ++ "&\"\\\\\"set unwind-on-signal off\\\\\"\\. Evaluation of the expression containing\\\\n\"" \ + "&\"the function \\(cond_fail\\) will be abandoned\\.\\\\n\"" \ + "=breakpoint-modified,bkpt={number=\"$bpnum\",type=\"breakpoint\",\[^\r\n\]+times=\"1\",\[^\r\n\]+}" \ + "~\"\\\\n\"" \ +@@ -92,7 +92,7 @@ proc run_test { unwind_on_signal } { + "&\"Error in testing condition for breakpoint $bpnum:\\\\n\"" \ + "&\"The program being debugged was signaled while in a function called from GDB\\.\\\\n\"" \ + "&\"GDB remains in the frame where the signal was received\\.\\\\n\"" \ +- "&\"To change this behavior use \\\\\"set unwindonsignal on\\\\\"\\.\\\\n\"" \ ++ "&\"To change this behavior use \\\\\"set unwind-on-signal on\\\\\"\\.\\\\n\"" \ + "&\"Evaluation of the expression containing the function\\\\n\"" \ + "&\"\\(cond_fail\\) will be abandoned\\.\\\\n\"" \ + "&\"When the function is done executing, GDB will silently stop\\.\\\\n\"" \ +diff --git a/gdb/testsuite/gdb.mi/mi-condbreak-throw.exp b/gdb/testsuite/gdb.mi/mi-condbreak-throw.exp +--- a/gdb/testsuite/gdb.mi/mi-condbreak-throw.exp ++++ b/gdb/testsuite/gdb.mi/mi-condbreak-throw.exp +@@ -103,7 +103,7 @@ proc run_test { unwind_on_exception } { + "&\"Error in testing condition for breakpoint $bpnum:\\\\n\"" \ + "&\"The program being debugged was signaled while in a function called from GDB\\.\\\\n\"" \ + "&\"GDB remains in the frame where the signal was received\\.\\\\n\"" \ +- "&\"To change this behavior use \\\\\"set unwindonsignal on\\\\\"\\.\\\\n\"" \ ++ "&\"To change this behavior use \\\\\"set unwind-on-signal on\\\\\"\\.\\\\n\"" \ + "&\"Evaluation of the expression containing the function\\\\n\"" \ + "&\"\\(cond_throw\\(\\)\\) will be abandoned\\.\\\\n\"" \ + "&\"When the function is done executing, GDB will silently stop\\.\\\\n\"" \ +diff --git a/gdb/testsuite/gdb.mi/mi-syn-frame.exp b/gdb/testsuite/gdb.mi/mi-syn-frame.exp +--- a/gdb/testsuite/gdb.mi/mi-syn-frame.exp ++++ b/gdb/testsuite/gdb.mi/mi-syn-frame.exp +@@ -94,7 +94,7 @@ mi_gdb_test "409-stack-list-frames 0 0" \ + # + + mi_gdb_test "410-data-evaluate-expression bar()" \ +- ".*410\\^error,msg=\"The program being debugged was signaled while in a function called from GDB.\\\\nGDB remains in the frame where the signal was received.\\\\nTo change this behavior use \\\\\"set unwindonsignal on\\\\\".\\\\nEvaluation of the expression containing the function\\\\n\\(bar\\) will be abandoned.\\\\nWhen the function is done executing, GDB will silently stop.\"" \ ++ ".*410\\^error,msg=\"The program being debugged was signaled while in a function called from GDB.\\\\nGDB remains in the frame where the signal was received.\\\\nTo change this behavior use \\\\\"set unwind-on-signal on\\\\\".\\\\nEvaluation of the expression containing the function\\\\n\\(bar\\) will be abandoned.\\\\nWhen the function is done executing, GDB will silently stop.\"" \ + "call inferior function which raises exception" + + mi_gdb_test "411-stack-list-frames" "411\\^done,stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"bar\",file=\".*mi-syn-frame.c\",fullname=\"${fullname_syntax}${srcfile}\",line=\"$decimal\",arch=\"$any\"},frame=\{level=\"1\",addr=\"$hex\",func=\"\"\},frame=\{level=\"2\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",fullname=\"${fullname_syntax}${srcfile}\",line=\"$decimal\",arch=\"$any\"}.*\\\]" "backtrace from inferior function at exception" +diff --git a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.exp b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.exp +--- a/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.exp ++++ b/gdb/testsuite/gdb.threads/infcall-from-bp-cond-simple.exp +@@ -173,7 +173,7 @@ proc_with_prefix run_bp_cond_segfaults { target_async target_non_stop } { + "Error in testing condition for breakpoint ${bp_1_num}:" \ + "The program being debugged was signaled while in a function called from GDB\\." \ + "GDB remains in the frame where the signal was received\\." \ +- "To change this behavior use \"set unwindonsignal on\"\\." \ ++ "To change this behavior use \"set unwind-on-signal on\"\\." \ + "Evaluation of the expression containing the function" \ + "\\(function_that_segfaults\\) will be abandoned\\." \ + "When the function is done executing, GDB will silently stop\\."] +diff --git a/gdb/testsuite/gdb.threads/thread-unwindonsignal.exp b/gdb/testsuite/gdb.threads/thread-unwindonsignal.exp +--- a/gdb/testsuite/gdb.threads/thread-unwindonsignal.exp ++++ b/gdb/testsuite/gdb.threads/thread-unwindonsignal.exp +@@ -13,7 +13,7 @@ + # You should have received a copy of the GNU General Public License + # along with this program. If not, see . + +-# Test use of unwindonsignal when a hand function call that gets interrupted ++# Test use of unwind-on-signal when a hand function call that gets interrupted + # by a signal in another thread. + + set NR_THREADS 4 +@@ -49,12 +49,12 @@ gdb_test "continue" \ + # We want the main thread (hand_call_with_signal) and + # thread 1 (sigabrt_handler) to both run. + +-# Do turn on unwindonsignal. ++# Do turn on unwind-on-signal. + # We want to test gdb handling of the current thread changing when + # unwindonsignal is in effect. +-gdb_test_no_output "set unwindonsignal on" \ ++gdb_test_no_output "set unwind-on-signal on" \ + "setting unwindonsignal" +-gdb_test "show unwindonsignal" \ ++gdb_test "show unwind-on-signal" \ + "Unwinding of stack .* is on." \ + "showing unwindonsignal" + diff --git a/gdb-rhel-19390-pc-not-saved.patch b/gdb-rhel-19390-pc-not-saved.patch new file mode 100644 index 0000000..3bfd212 --- /dev/null +++ b/gdb-rhel-19390-pc-not-saved.patch @@ -0,0 +1,379 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andrew Burgess +Date: Wed, 24 Jan 2024 13:52:59 +0000 +Subject: gdb-rhel-19390-pc-not-saved.patch + +;;gdb/unwinders: better support for $pc not saved +;;(Andrew Burgess, RHEL-19390) + +This started with a Red Hat bug report which can be seen here: + + https://bugzilla.redhat.com/show_bug.cgi?id=1850710 + +The problem reported here was using GDB on GNU/Linux for S390, the +user stepped into JIT generated code. As they enter the JIT code GDB +would report 'PC not saved', and this same message would be reported +after each step/stepi. + +Additionally, the user had 'set disassemble-next-line on', and once +they entered the JIT code this output was not displayed, nor were any +'display' directives displayed. + +The user is not making use of the JIT plugin API to provide debug +information. But that's OK, they aren't expecting any source level +debug here, they are happy to use 'stepi', but the missing 'display' +directives are a problem, as is the constant 'PC not saved' (error) +message. + +What is happening here is that as GDB is failing to find any debug +information for the JIT generated code, it is falling back on to the +S390 prologue unwinder to try and unwind frame #0. Unfortunately, +without being able to identify the function boundaries, the S390 +prologue scanner can't help much, in fact, it doesn't even suggest an +arbitrary previous $pc value (some targets that use a link-register +will, by default, assume the link-register contains the previous $pc), +instead the S390 will just say, "sorry, I have no previous $pc value". + +The result of this is that when GDB tries to find frame #1 we end +throwing an error from frame_unwind_pc (the 'PC not saved' error). +This error is not caught anywhere except at the top-level interpreter +loop, and so we end up skipping all the 'display' directive handling. + +While thinking about this, I wondered, could I trigger the same error +using the Python Unwinder API? What happens if a Python unwinder +claims a frame, but then fails to provide a previous $pc value? + +Turns out that exactly the same thing happens, which is great, as that +means we now have a way to reproduce this bug on any target. And so +the test included with this patch does just this. I have a Python +unwinder that claims a frame, but doesn't provide any previous +register values. + +I then do two tests, first I stop in the claimed frame (i.e. frame #0 +is the frame that can't be unwound), I perform a few steps, and check +the backtrace. And second, I stop in a child of the problem +frame (i.e. frame #1 is the frame that can't be unwound), and from +here I check the backtrace. + +While all this is going on I have a 'display' directive in place, and +each time GDB stops I check that the display directive triggers. + +Additionally, when checking the backtrace, I am checking that the +backtrace finishes with the message 'Backtrace stopped: frame did not +save the PC'. + +As for the fix I chose to add a call to frame_unwind_pc directly to +get_prev_frame_always_1. Calling frame_unwind_pc will cache the +unwound $pc value, so this doesn't add much additional work as +immediately after the new frame_unwind_pc call, we call +get_prev_frame_maybe_check_cycle, which actually generates the +previous frame, which will always (I think) require a call to +frame_unwind_pc anyway. + +The reason for adding the frame_unwind_pc call into +get_prev_frame_always_1, is that if the frame_unwind_pc call fails we +want to set the frames 'stop_reason', and get_prev_frame_always_1 +seems to be the place where this is done, so I wanted to keep the new +stop_reason setting code next to all the existing stop_reason setting +code. + +Additionally, once we enter get_prev_frame_maybe_check_cycle we +actually create the previous frame, then, if it turns out that the +previous frame can't be created we need to remove the frame .. this +seemed more complex than just making the check in +get_prev_frame_always_1. + +With this fix in place the original S390 bug is fixed, and also the +test added in this commit, that uses the Python API, is also fixed. + +Reviewed-By: Kevin Buettner + +diff --git a/gdb/frame.c b/gdb/frame.c +--- a/gdb/frame.c ++++ b/gdb/frame.c +@@ -2422,6 +2422,38 @@ get_prev_frame_always_1 (frame_info_ptr this_frame) + } + } + ++ /* Ensure we can unwind the program counter of THIS_FRAME. */ ++ try ++ { ++ /* Calling frame_unwind_pc for the sentinel frame relies on the ++ current_frame being set, which at this point it might not be if we ++ are in the process of setting the current_frame after a stop (see ++ get_current_frame). ++ ++ The point of this check is to ensure that the unwinder for ++ THIS_FRAME can actually unwind the $pc, which we assume the ++ sentinel frame unwinder can always do (it's just a read from the ++ machine state), so we only call frame_unwind_pc for frames other ++ than the sentinel (level -1) frame. ++ ++ Additionally, we don't actually care about the value of the ++ unwound $pc, just that the call completed successfully. */ ++ if (this_frame->level >= 0) ++ frame_unwind_pc (this_frame); ++ } ++ catch (const gdb_exception_error &ex) ++ { ++ if (ex.error == NOT_AVAILABLE_ERROR || ex.error == OPTIMIZED_OUT_ERROR) ++ { ++ frame_debug_printf (" -> nullptr // no saved PC"); ++ this_frame->stop_reason = UNWIND_NO_SAVED_PC; ++ this_frame->prev = nullptr; ++ return nullptr; ++ } ++ ++ throw; ++ } ++ + return get_prev_frame_maybe_check_cycle (this_frame); + } + +diff --git a/gdb/testsuite/gdb.base/pc-not-saved.c b/gdb/testsuite/gdb.base/pc-not-saved.c +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.base/pc-not-saved.c +@@ -0,0 +1,48 @@ ++/* This testcase is part of GDB, the GNU debugger. ++ ++ Copyright 2024 Free Software Foundation, Inc. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++volatile int global_var = 0; ++ ++void ++other_func (void) ++{ ++ /* Nothing. */ ++} ++ ++void ++break_bt_here (void) ++{ ++ /* This is all nonsense; just filler so this function has a body. */ ++ if (global_var != 99) ++ global_var++; ++ if (global_var != 98) ++ global_var++; ++ if (global_var != 97) ++ global_var++; ++ if (global_var != 96) ++ global_var++; ++ other_func (); ++ if (global_var != 95) ++ global_var++; ++} ++ ++int ++main (void) ++{ ++ break_bt_here (); ++ return 0; ++} +diff --git a/gdb/testsuite/gdb.base/pc-not-saved.exp b/gdb/testsuite/gdb.base/pc-not-saved.exp +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.base/pc-not-saved.exp +@@ -0,0 +1,113 @@ ++# Copyright 2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++ ++# Test how GDB handles a frame in which the previous-pc value is not ++# available. Specifically, check that the backtrace correctly reports ++# why the backtrace is truncated, and ensure that 'display' directives ++# still work when 'stepi'-ing through the frame. ++# ++# We do this by registering a Python unwinder which doesn't provide ++# any previous register values. ++ ++require allow_python_tests ++ ++standard_testfile ++ ++if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile}] } { ++ return ++} ++ ++set remote_python_file \ ++ [gdb_remote_download host "${srcdir}/${subdir}/${testfile}.py"] ++ ++if { ![runto "break_bt_here"] } { ++ return ++} ++ ++# Figuring out the correct frame-id from a Python unwinder is hard. ++# We need to know the function's start address (not too hard), and the ++# stack address on entry to the function, which is much harder to ++# figure out in a cross-target way. ++# ++# So instead we run without any Python unwinder in place and use ++# 'maint print frame-id' to record the frame-id. We then restart GDB, ++# load the Python unwinder, and tell it to use the frame-id we ++# recorded here. ++set pc unknown ++set cfa unknown ++gdb_test_multiple "maintenance print frame-id" "store break_bt_here frame-id" { ++ -re -wrap "frame-id for frame #0: \\{stack=($hex),code=($hex),\[^\}\]+\\}" { ++ set cfa $expect_out(1,string) ++ set pc $expect_out(1,string) ++ } ++} ++gdb_assert { ![string equal $cfa unknown] } \ ++ "check we read the frame's CFA" ++ ++gdb_assert { ![string equal $pc unknown] } \ ++ "check we read the frame's PC" ++ ++# Restart and load the Python unwinder script. ++clean_restart $binfile ++gdb_test_no_output "source ${remote_python_file}" "load python file" ++ ++# Tell the Python unwinder to use the frame-id we cached above. ++gdb_test_no_output "python set_break_bt_here_frame_id($pc, $cfa)" ++ ++# Run up to the function which the unwinder will claim. ++if { ![runto "break_bt_here"] } { ++ return ++} ++ ++# Print the backtrace. Check that the reason for stopping the ++# backtrace is that the previous $pc is not available. ++gdb_test "bt" \ ++ [multi_line \ ++ "^#0 break_bt_here \\(\\) at \[^\r\n\]+" \ ++ "Backtrace stopped: frame did not save the PC"] \ ++ "backtrace from break_bt_here function" ++ ++# Ensure we can stepi. ++gdb_test "stepi" \ ++ "(:?$hex\\s+)?$decimal\\s+\[^\r\n\]+" \ ++ "stepi without a display in place" ++ ++# Setup a 'display' directive. ++gdb_test "display/i \$pc" \ ++ [multi_line \ ++ "^1: x/i \\\$pc" \ ++ "=> $hex :\\s+\[^\r\n\]+"] ++ ++# Step again, check the 'display' directive is shown. ++gdb_test "stepi" \ ++ [multi_line \ ++ "(:?$hex\\s+)?$decimal\\s+\[^\r\n\]+" \ ++ "1: x/i \\\$pc" \ ++ "=> $hex :\\s+\[^\r\n\]+"] \ ++ "stepi with a display in place" ++ ++# Continue to a function that is called from within break_bt_here. ++# The Python unwinder will then be claiming frame #1. ++gdb_breakpoint other_func ++gdb_continue_to_breakpoint "continue to other_func" ++ ++# Print the backtrace and check that the reason for stopping the ++# backtrace is that the previous $pc is not available. ++gdb_test "bt" \ ++ [multi_line \ ++ "#0 other_func \\(\\) at \[^\r\n\]+" \ ++ "#1 (:?$hex in )?break_bt_here \\(\\) at \[^\r\n\]+" \ ++ "Backtrace stopped: frame did not save the PC"] \ ++ "backtrace from other_func function" +diff --git a/gdb/testsuite/gdb.base/pc-not-saved.py b/gdb/testsuite/gdb.base/pc-not-saved.py +new file mode 100644 +--- /dev/null ++++ b/gdb/testsuite/gdb.base/pc-not-saved.py +@@ -0,0 +1,71 @@ ++# Copyright (C) 2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++ ++import gdb ++from gdb.unwinder import Unwinder, FrameId ++ ++# Cached FrameId. See set_break_bt_here_frame_id for details. ++break_bt_here_frame_id = None ++ ++ ++def set_break_bt_here_frame_id(pc, cfa): ++ """Call this to pre-calculate the FrameId for the frame our unwinder ++ is going to claim, this avoids us having to actually figure out a ++ frame-id within the unwinder, something which is going to be hard ++ to do in a cross-target way. ++ ++ Instead we first run the test without the Python unwinder in ++ place, use 'maint print frame-id' to record the frame-id, then, ++ after loading this Python script, we all this function to record ++ the frame-id that the unwinder should use.""" ++ global break_bt_here_frame_id ++ break_bt_here_frame_id = FrameId(cfa, pc) ++ ++ ++class break_unwinding(Unwinder): ++ ++ """An unwinder for the function 'break_bt_here'. This unwinder will ++ claim any frame for the function in question, but doesn't provide ++ any unwound register values. Importantly, we don't provide a ++ previous $pc value, this means that if we are stopped in ++ 'break_bt_here' then we should fail to unwind beyond frame #0.""" ++ ++ def __init__(self): ++ Unwinder.__init__(self, "break unwinding") ++ ++ def __call__(self, pending_frame): ++ pc_desc = pending_frame.architecture().registers().find("pc") ++ pc = pending_frame.read_register(pc_desc) ++ ++ if pc.is_optimized_out: ++ return None ++ ++ block = gdb.block_for_pc(pc) ++ if block == None: ++ return None ++ func = block.function ++ if func == None: ++ return None ++ if str(func) != "break_bt_here": ++ return None ++ ++ global break_bt_here_frame_id ++ if break_bt_here_frame_id is None: ++ return None ++ ++ return pending_frame.create_unwind_info(break_bt_here_frame_id) ++ ++ ++gdb.unwinder.register_unwinder(None, break_unwinding(), True) diff --git a/gdb-rhel-36225-add-arch14-record.patch b/gdb-rhel-36225-add-arch14-record.patch new file mode 100644 index 0000000..31c15f9 --- /dev/null +++ b/gdb-rhel-36225-add-arch14-record.patch @@ -0,0 +1,46 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andreas Arnez +Date: Tue, 13 Feb 2024 18:55:29 +0100 +Subject: gdb-rhel-36225-add-arch14-record.patch + +;; Backport "gdb: s390: Add arch14 record/replay support" +;; (Andreas Arnez, RHEL-36225) + +Enable recording of the new "arch14" instructions on z/Architecture +targets, except for the specialized-function-assist instruction NNPA. + +diff --git a/gdb/s390-tdep.c b/gdb/s390-tdep.c +--- a/gdb/s390-tdep.c ++++ b/gdb/s390-tdep.c +@@ -5534,6 +5534,14 @@ s390_process_record (struct gdbarch *gdbarch, struct regcache *regcache, + case 0xe635: /* VLRL - vector load rightmost with immed. length */ + case 0xe637: /* VLRLR - vector load rightmost with length */ + case 0xe649: /* VLIP - vector load immediate decimal */ ++ case 0xe656: /* VCLFNH - vector fp convert and lengthen from NNP high */ ++ case 0xe65e: /* VCLFNL - vector fp convert and lengthen from NNP low */ ++ case 0xe655: /* VCNF - vector fp convert to NNP */ ++ case 0xe65d: /* VCFN - vector fp convert from NNP */ ++ case 0xe674: /* VSCHP - decimal scale and convert to HFP */ ++ case 0xe675: /* VCRNF - vector fp convert and round to NNP */ ++ case 0xe67c: /* VSCSHP - decimal scale and convert and split to HFP */ ++ case 0xe67d: /* VCSPH - vector convert HFP to scaled decimal */ + case 0xe700: /* VLEB - vector load element */ + case 0xe701: /* VLEH - vector load element */ + case 0xe702: /* VLEG - vector load element */ +@@ -5791,11 +5799,16 @@ s390_process_record (struct gdbarch *gdbarch, struct regcache *regcache, + + /* 0xe747-0xe749 undefined */ + ++ case 0xe651: /* VCLZDP - vector count leading zero digits */ ++ case 0xe654: /* VUPKZH - vector unpack zoned high */ + case 0xe658: /* VCVD - vector convert to decimal 32 bit */ + case 0xe659: /* VSRP - vector shift and round decimal */ + case 0xe65a: /* VCVDG - vector convert to decimal 64 bit*/ + case 0xe65b: /* VPSOP - vector perform sign operation decimal */ ++ case 0xe65c: /* VUPKZL - vector unpack zoned low */ ++ case 0xe670: /* VPKZR - vector pack zoned register */ + case 0xe671: /* VAP - vector add decimal */ ++ case 0xe672: /* VSRPR - vector shift and round decimal register */ + case 0xe673: /* VSP - vector subtract decimal */ + case 0xe678: /* VMP - vector multiply decimal */ + case 0xe679: /* VMSP - vector multiply decimal */ diff --git a/gdb-rhel-36518-add-power11-support.patch b/gdb-rhel-36518-add-power11-support.patch new file mode 100644 index 0000000..805a868 --- /dev/null +++ b/gdb-rhel-36518-add-power11-support.patch @@ -0,0 +1,48 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Peter Bergner +Date: Fri, 9 Feb 2024 10:51:30 -0600 +Subject: gdb-rhel-36518-add-power11-support.patch + +;; Backport "PowerPC: Add support for Power11 options" +;; (Peter Bergner, RHEL-36518) + +opcodes/ + * ppc-dis.c (ppc_opts): Add "power11" and "pwr11" entries. + (powerpc_init_dialect): Default to "power11". + +diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c +--- a/opcodes/ppc-dis.c ++++ b/opcodes/ppc-dis.c +@@ -208,6 +208,11 @@ struct ppc_mopt ppc_opts[] = { + | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 + | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), + 0 }, ++ { "power11", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 ++ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 ++ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 ++ | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), ++ 0 }, + { "libresoc",(PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 + | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 +@@ -267,6 +272,11 @@ struct ppc_mopt ppc_opts[] = { + | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 + | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), + 0 }, ++ { "pwr11", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 ++ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 ++ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 ++ | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), ++ 0 }, + { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, + 0 }, + { "raw", PPC_OPCODE_PPC, +@@ -396,7 +406,7 @@ powerpc_init_dialect (struct disassemble_info *info) + break; + default: + if (info->arch == bfd_arch_powerpc) +- dialect = ppc_parse_cpu (dialect, &sticky, "power10") | PPC_OPCODE_ANY; ++ dialect = ppc_parse_cpu (dialect, &sticky, "power11") | PPC_OPCODE_ANY; + else + dialect = ppc_parse_cpu (dialect, &sticky, "pwr"); + break; diff --git a/gdb-rhel-36527-apx-disasm.patch b/gdb-rhel-36527-apx-disasm.patch new file mode 100644 index 0000000..e143e99 --- /dev/null +++ b/gdb-rhel-36527-apx-disasm.patch @@ -0,0 +1,7834 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Keith Seitz +Date: Wed, 15 May 2024 09:59:51 -0700 +Subject: gdb-rhel-36527-apx-disasm.patch + +;; Update x86 disassembler + +Update x86 disassembler with APX improvements by syncing +with gdb-15.1 release candidate. + +Resolves: RHEL-36527 + +diff --git a/include/opcode/i386.h b/include/opcode/i386.h +--- a/include/opcode/i386.h ++++ b/include/opcode/i386.h +@@ -1,5 +1,5 @@ + /* opcode/i386.h -- Intel 80386 opcode macros +- Copyright (C) 1989-2023 Free Software Foundation, Inc. ++ Copyright (C) 1989-2024 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. + +@@ -112,9 +112,13 @@ + /* x86-64 extension prefix. */ + #define REX_OPCODE 0x40 + ++#define REX2_OPCODE 0xd5 ++ + /* Non-zero if OPCODE is the rex prefix. */ + #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) + ++/* M0 in rex2 prefix represents map0 or map1. */ ++#define REX2_M 0x8 + /* Indicates 64 bit operand size. */ + #define REX_W 8 + /* High extension to reg field of modrm byte. */ +diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h +--- a/opcodes/i386-dis-evex-mod.h ++++ b/opcodes/i386-dis-evex-mod.h +@@ -1 +1,10 @@ +-/* Nothing at present. */ ++ /* MOD_EVEX_MAP4_F8_P1 */ ++ { ++ { "enqcmds", { Gva, M }, 0 }, ++ { VEX_W_TABLE (EVEX_W_MAP4_F8_P1_M_1) }, ++ }, ++ /* MOD_EVEX_MAP4_F8_P3 */ ++ { ++ { "enqcmd", { Gva, M }, 0 }, ++ { VEX_W_TABLE (EVEX_W_MAP4_F8_P3_M_1) }, ++ }, +diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h +--- a/opcodes/i386-dis-evex-prefix.h ++++ b/opcodes/i386-dis-evex-prefix.h +@@ -338,6 +338,29 @@ + { "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 }, + { "vcmps%XH", { MaskG, VexScalar, EXw, EXxEVexS, CMP }, 0 }, + }, ++ /* PREFIX_EVEX_MAP4_F0 */ ++ { ++ { "crc32A", { Gdq, Eb }, 0 }, ++ { "invept", { Gm, Mo }, 0 }, ++ }, ++ /* PREFIX_EVEX_MAP4_F1 */ ++ { ++ { "crc32Q", { Gdq, Ev }, 0 }, ++ { "invvpid", { Gm, Mo }, 0 }, ++ { "crc32Q", { Gdq, Ev }, 0 }, ++ }, ++ /* PREFIX_EVEX_MAP4_F2 */ ++ { ++ { Bad_Opcode }, ++ { "invpcid", { Gm, M }, 0 }, ++ }, ++ /* PREFIX_EVEX_MAP4_F8 */ ++ { ++ { Bad_Opcode }, ++ { MOD_TABLE (MOD_EVEX_MAP4_F8_P_1) }, ++ { "movdir64b", { Gva, M }, 0 }, ++ { MOD_TABLE (MOD_EVEX_MAP4_F8_P_3) }, ++ }, + /* PREFIX_EVEX_MAP5_10 */ + { + { Bad_Opcode }, +diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h +--- a/opcodes/i386-dis-evex-reg.h ++++ b/opcodes/i386-dis-evex-reg.h +@@ -49,3 +49,74 @@ + { "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, + { "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, + }, ++ /* REG_EVEX_MAP4_80 */ ++ { ++ { "%NFaddA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NForA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "adcA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "sbbA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFandA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFsubA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFxorA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ }, ++ /* REG_EVEX_MAP4_81 */ ++ { ++ { "%NFaddQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ { "%NForQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ { "adcQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ { "sbbQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ { "%NFandQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ { "%NFsubQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ { "%NFxorQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ }, ++ /* REG_EVEX_MAP4_83 */ ++ { ++ { "%NFaddQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ { "%NForQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ { "adcQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ { "sbbQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ { "%NFandQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ { "%NFsubQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ { "%NFxorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ }, ++ /* REG_EVEX_MAP4_8F */ ++ { ++ { VEX_W_TABLE (EVEX_W_MAP4_8F_R_0) }, ++ }, ++ /* REG_EVEX_MAP4_F6 */ ++ { ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { "notA", { VexGb, Eb }, NO_PREFIX }, ++ { "%NFnegA", { VexGb, Eb }, NO_PREFIX }, ++ { "%NFmulA", { Eb }, NO_PREFIX }, ++ { "%NFimulA", { Eb }, NO_PREFIX }, ++ { "%NFdivA", { Eb }, NO_PREFIX }, ++ { "%NFidivA", { Eb }, NO_PREFIX }, ++ }, ++ /* REG_EVEX_MAP4_F7 */ ++ { ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { "notQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%NFnegQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%NFmulQ", { Ev }, PREFIX_NP_OR_DATA }, ++ { "%NFimulQ", { Ev }, PREFIX_NP_OR_DATA }, ++ { "%NFdivQ", { Ev }, PREFIX_NP_OR_DATA }, ++ { "%NFidivQ", { Ev }, PREFIX_NP_OR_DATA }, ++ }, ++ /* REG_EVEX_MAP4_FE */ ++ { ++ { "%NFincA", { VexGb, Eb }, NO_PREFIX }, ++ { "%NFdecA", { VexGb, Eb }, NO_PREFIX }, ++ }, ++ /* REG_EVEX_MAP4_FF */ ++ { ++ { "%NFincQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%NFdecQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { VEX_W_TABLE (EVEX_W_MAP4_FF_R_6) }, ++ }, +diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h +--- a/opcodes/i386-dis-evex-w.h ++++ b/opcodes/i386-dis-evex-w.h +@@ -442,6 +442,24 @@ + { Bad_Opcode }, + { "vpshrdw", { XM, Vex, EXx, Ib }, 0 }, + }, ++ /* EVEX_W_MAP4_8F_R_0 */ ++ { ++ { "pop2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX }, ++ { "pop2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX }, ++ }, ++ /* EVEX_W_MAP4_F8_P1_M_1 */ ++ { ++ { "uwrmsr", { Gq, Eq }, 0 }, ++ }, ++ /* EVEX_W_MAP4_F8_P3_M_1 */ ++ { ++ { "urdmsr", { Eq, Gq }, 0 }, ++ }, ++ /* EVEX_W_MAP4_FF_R_6 */ ++ { ++ { "push2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 }, ++ { "push2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 }, ++ }, + /* EVEX_W_MAP5_5B_P_0 */ + { + { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, +diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h +--- a/opcodes/i386-dis-evex.h ++++ b/opcodes/i386-dis-evex.h +@@ -164,10 +164,10 @@ static const struct dis386 evex_table[][256] = { + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, ++ { X86_64_EVEX_W_TABLE (VEX_W_0F90_L_0) }, ++ { X86_64_EVEX_W_TABLE (VEX_W_0F91_L_0) }, ++ { X86_64_EVEX_W_TABLE (VEX_W_0F92_L_0) }, ++ { X86_64_EVEX_W_TABLE (VEX_W_0F93_L_0) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, +@@ -375,9 +375,9 @@ static const struct dis386 evex_table[][256] = { + { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, + /* 48 */ + { Bad_Opcode }, ++ { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) }, + { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, ++ { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) }, + { "vrcp14p%XW", { XM, EXx }, PREFIX_DATA }, + { "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, + { "vrsqrt14p%XW", { XM, EXx }, 0 }, +@@ -545,32 +545,32 @@ static const struct dis386 evex_table[][256] = { + { "%XEvaesdecY", { XM, Vex, EXx }, PREFIX_DATA }, + { "%XEvaesdeclastY", { XM, Vex, EXx }, PREFIX_DATA }, + /* E0 */ +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E0) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E1) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E2) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E3) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E4) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E5) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E6) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E7) }, + /* E8 */ +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E8) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E9) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EA) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EB) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EC) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38ED) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EE) }, ++ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EF) }, + /* F0 */ + { Bad_Opcode }, + { Bad_Opcode }, ++ { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F2_L_0) }, ++ { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F3_L_0) }, + { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, +- { Bad_Opcode }, ++ { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F5_L_0) }, ++ { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F6_L_0) }, ++ { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F7_L_0) }, + /* F8 */ + { Bad_Opcode }, + { Bad_Opcode }, +@@ -854,7 +854,7 @@ static const struct dis386 evex_table[][256] = { + { Bad_Opcode }, + { Bad_Opcode }, + /* F0 */ +- { Bad_Opcode }, ++ { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, +@@ -872,6 +872,297 @@ static const struct dis386 evex_table[][256] = { + { Bad_Opcode }, + { Bad_Opcode }, + }, ++ /* EVEX_MAP4_ */ ++ { ++ /* 00 */ ++ { "%NFaddB", { VexGb, Eb, Gb }, NO_PREFIX }, ++ { "%NFaddS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { "%NFaddB", { VexGb, Gb, EbS }, NO_PREFIX }, ++ { "%NFaddS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 08 */ ++ { "%NForB", { VexGb, Eb, Gb }, NO_PREFIX }, ++ { "%NForS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { "%NForB", { VexGb, Gb, EbS }, NO_PREFIX }, ++ { "%NForS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 10 */ ++ { "adcB", { VexGb, Eb, Gb }, NO_PREFIX }, ++ { "adcS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { "adcB", { VexGb, Gb, EbS }, NO_PREFIX }, ++ { "adcS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 18 */ ++ { "sbbB", { VexGb, Eb, Gb }, NO_PREFIX }, ++ { "sbbS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { "sbbB", { VexGb, Gb, EbS }, NO_PREFIX }, ++ { "sbbS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 20 */ ++ { "%NFandB", { VexGb, Eb, Gb }, NO_PREFIX }, ++ { "%NFandS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { "%NFandB", { VexGb, Gb, EbS }, NO_PREFIX }, ++ { "%NFandS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA }, ++ { "%NFshldS", { VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 28 */ ++ { "%NFsubB", { VexGb, Eb, Gb }, NO_PREFIX }, ++ { "%NFsubS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { "%NFsubB", { VexGb, Gb, EbS }, NO_PREFIX }, ++ { "%NFsubS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA }, ++ { "%NFshrdS", { VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 30 */ ++ { "%NFxorB", { VexGb, Eb, Gb }, NO_PREFIX }, ++ { "%NFxorS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { "%NFxorB", { VexGb, Gb, EbS }, NO_PREFIX }, ++ { "%NFxorS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 38 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 40 */ ++ { "%CFcmovoS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovnoS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovbS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovaeS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmoveS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovneS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovbeS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovaS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ /* 48 */ ++ { "%CFcmovsS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovnsS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovpS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovnpS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovlS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovgeS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovleS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%CFcmovgS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ /* 50 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 58 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 60 */ ++ { "%MEmovbeS", { Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%MEmovbeS", { Ev, Gv }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { "wrussK", { M, Gdq }, PREFIX_DATA }, ++ { PREFIX_TABLE (PREFIX_0F38F6) }, ++ { Bad_Opcode }, ++ /* 68 */ ++ { Bad_Opcode }, ++ { "%NFimulS", { Gv, Ev, Iv }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { "%NFimulS", { Gv, Ev, sIb }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 70 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 78 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 80 */ ++ { REG_TABLE (REG_EVEX_MAP4_80) }, ++ { REG_TABLE (REG_EVEX_MAP4_81) }, ++ { Bad_Opcode }, ++ { REG_TABLE (REG_EVEX_MAP4_83) }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 88 */ ++ { "%NFpopcntS", { Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { REG_TABLE (REG_EVEX_MAP4_8F) }, ++ /* 90 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* 98 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* A0 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { "%NFshldS", { VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* A8 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { "%NFshrdS", { VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA }, ++ { Bad_Opcode }, ++ { "%NFimulS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA }, ++ /* B0 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* B8 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* C0 */ ++ { REG_TABLE (REG_C0) }, ++ { REG_TABLE (REG_C1) }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* C8 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* D0 */ ++ { REG_TABLE (REG_D0) }, ++ { REG_TABLE (REG_D1) }, ++ { REG_TABLE (REG_D2) }, ++ { REG_TABLE (REG_D3) }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* D8 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* E0 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* E8 */ ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ /* F0 */ ++ { PREFIX_TABLE (PREFIX_EVEX_MAP4_F0) }, ++ { PREFIX_TABLE (PREFIX_EVEX_MAP4_F1) }, ++ { PREFIX_TABLE (PREFIX_EVEX_MAP4_F2) }, ++ { Bad_Opcode }, ++ { "%NFtzcntS", { Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { "%NFlzcntS", { Gv, Ev }, PREFIX_NP_OR_DATA }, ++ { REG_TABLE (REG_EVEX_MAP4_F6) }, ++ { REG_TABLE (REG_EVEX_MAP4_F7) }, ++ /* F8 */ ++ { PREFIX_TABLE (PREFIX_EVEX_MAP4_F8) }, ++ { "movdiri", { Mdq, Gdq }, NO_PREFIX }, ++ { Bad_Opcode }, ++ { Bad_Opcode }, ++ { PREFIX_TABLE (PREFIX_0F38FC) }, ++ { Bad_Opcode }, ++ { REG_TABLE (REG_EVEX_MAP4_FE) }, ++ { REG_TABLE (REG_EVEX_MAP4_FF) }, ++ }, + /* EVEX_MAP5_ */ + { + /* 00 */ +diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c +--- a/opcodes/i386-dis.c ++++ b/opcodes/i386-dis.c +@@ -1,5 +1,5 @@ + /* Print i386 instructions for GDB, the GNU debugger. +- Copyright (C) 1988-2023 Free Software Foundation, Inc. ++ Copyright (C) 1988-2024 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + +@@ -105,6 +105,8 @@ static bool FXSAVE_Fixup (instr_info *, int, int); + static bool MOVSXD_Fixup (instr_info *, int, int); + static bool DistinctDest_Fixup (instr_info *, int, int); + static bool PREFETCHI_Fixup (instr_info *, int, int); ++static bool PUSH2_POP2_Fixup (instr_info *, int, int); ++static bool JMPABS_Fixup (instr_info *, int, int); + + static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, + enum disassembler_style, +@@ -132,6 +134,13 @@ enum x86_64_isa + intel64 + }; + ++enum evex_type ++{ ++ evex_default = 0, ++ evex_from_legacy, ++ evex_from_vex, ++}; ++ + struct instr_info + { + enum address_mode address_mode; +@@ -144,6 +153,12 @@ struct instr_info + /* Bits of REX we've already used. */ + uint8_t rex_used; + ++ /* Record W R4 X4 B4 bits for rex2. */ ++ unsigned char rex2; ++ /* Bits of rex2 we've already used. */ ++ unsigned char rex2_used; ++ unsigned char rex2_payload; ++ + bool need_modrm; + unsigned char need_vex; + bool has_sib; +@@ -169,6 +184,7 @@ struct instr_info + signed char last_data_prefix; + signed char last_addr_prefix; + signed char last_rex_prefix; ++ signed char last_rex2_prefix; + signed char last_seg_prefix; + signed char fwait_prefix; + /* The active segment register prefix. */ +@@ -205,14 +221,19 @@ struct instr_info + int ll; + bool w; + bool evex; +- bool r; + bool v; + bool zeroing; + bool b; + bool no_broadcast; ++ bool nf; + } + vex; + ++/* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */ ++#define nd b ++ ++ enum evex_type evex_type; ++ + /* Remember if the current op is a jump instruction. */ + bool op_is_jump; + +@@ -221,6 +242,9 @@ struct instr_info + /* Record whether EVEX masking is used incorrectly. */ + bool illegal_masking; + ++ /* Record whether the modrm byte has been skipped. */ ++ bool has_skipped_modrm; ++ + unsigned char op_ad; + signed char op_index[MAX_OPERANDS]; + bool op_riprel[MAX_OPERANDS]; +@@ -262,8 +286,13 @@ struct dis_private { + { \ + if (value) \ + { \ +- if ((ins->rex & value)) \ ++ if (ins->rex & value) \ + ins->rex_used |= (value) | REX_OPCODE; \ ++ if (ins->rex2 & value) \ ++ { \ ++ ins->rex2_used |= (value); \ ++ ins->rex_used |= REX_OPCODE; \ ++ } \ + } \ + else \ + ins->rex_used |= REX_OPCODE; \ +@@ -273,6 +302,10 @@ struct dis_private { + #define EVEX_b_used 1 + #define EVEX_len_used 2 + ++ ++/* {rex2} is not printed when the REX2_SPECIAL is set. */ ++#define REX2_SPECIAL 16 ++ + /* Flags stored in PREFIXES. */ + #define PREFIX_REPZ 1 + #define PREFIX_REPNZ 2 +@@ -286,6 +319,9 @@ struct dis_private { + #define PREFIX_DATA 0x200 + #define PREFIX_ADDR 0x400 + #define PREFIX_FWAIT 0x800 ++#define PREFIX_REX2 0x1000 ++#define PREFIX_NP_OR_DATA 0x2000 ++#define NO_PREFIX 0x4000 + + /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns true for success, false +@@ -367,6 +403,7 @@ fetch_error (const instr_info *ins) + #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) + #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) + #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) ++#define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT) + + /* Opcode prefixes. */ + #define PREFIX_OPCODE (PREFIX_REPZ \ +@@ -418,6 +455,7 @@ fetch_error (const instr_info *ins) + #define Gv { OP_G, v_mode } + #define Gd { OP_G, d_mode } + #define Gdq { OP_G, dq_mode } ++#define Gq { OP_G, q_mode } + #define Gm { OP_G, m_mode } + #define Gva { OP_G, va_mode } + #define Gw { OP_G, w_mode } +@@ -527,7 +565,8 @@ fetch_error (const instr_info *ins) + #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } + #define Rd { OP_R, d_mode } + #define Rdq { OP_R, dq_mode } +-#define Nq { OP_R, q_mode } ++#define Rq { OP_R, q_mode } ++#define Nq { OP_R, q_mm_mode } + #define Ux { OP_R, x_mode } + #define Uxmm { OP_R, xmm_mode } + #define Rxmmq { OP_R, xmmq_mode } +@@ -548,6 +587,8 @@ fetch_error (const instr_info *ins) + #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode } + #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } + #define VexGdq { OP_VEX, dq_mode } ++#define VexGb { OP_VEX, b_mode } ++#define VexGv { OP_VEX, v_mode } + #define VexTmm { OP_VEX, tmm_mode } + #define XMVexI4 { OP_REG_VexI4, x_mode } + #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } +@@ -624,6 +665,8 @@ enum + d_swap_mode, + /* quad word operand */ + q_mode, ++ /* 8-byte MM operand */ ++ q_mm_mode, + /* quad word operand with operand swapped */ + q_swap_mode, + /* ten-byte operand */ +@@ -778,6 +821,10 @@ enum + USE_RM_TABLE, + USE_PREFIX_TABLE, + USE_X86_64_TABLE, ++ USE_X86_64_EVEX_FROM_VEX_TABLE, ++ USE_X86_64_EVEX_PFX_TABLE, ++ USE_X86_64_EVEX_W_TABLE, ++ USE_X86_64_EVEX_MEM_W_TABLE, + USE_3BYTE_TABLE, + USE_XOP_8F_TABLE, + USE_VEX_C4_TABLE, +@@ -796,6 +843,11 @@ enum + #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) + #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) + #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) ++#define X86_64_EVEX_FROM_VEX_TABLE(I) \ ++ DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I)) ++#define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I)) ++#define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I)) ++#define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I)) + #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) + #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0) + #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0) +@@ -844,7 +896,8 @@ enum + REG_VEX_0F73, + REG_VEX_0FAE, + REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, +- REG_VEX_0F38F3_L_0, ++ REG_VEX_0F38F3_L_0_P_0, ++ REG_VEX_MAP7_F8_L_0_W_0, + + REG_XOP_09_01_L_0, + REG_XOP_09_02_L_0, +@@ -855,7 +908,15 @@ enum + REG_EVEX_0F72, + REG_EVEX_0F73, + REG_EVEX_0F38C6_L_2, +- REG_EVEX_0F38C7_L_2 ++ REG_EVEX_0F38C7_L_2, ++ REG_EVEX_MAP4_80, ++ REG_EVEX_MAP4_81, ++ REG_EVEX_MAP4_83, ++ REG_EVEX_MAP4_8F, ++ REG_EVEX_MAP4_F6, ++ REG_EVEX_MAP4_F7, ++ REG_EVEX_MAP4_FE, ++ REG_EVEX_MAP4_FF, + }; + + enum +@@ -893,8 +954,12 @@ enum + MOD_0FC7_REG_6, + MOD_0FC7_REG_7, + MOD_0F38DC_PREFIX_1, ++ MOD_0F38F8, + + MOD_VEX_0F3849_X86_64_L_0_W_0, ++ ++ MOD_EVEX_MAP4_F8_P_1, ++ MOD_EVEX_MAP4_F8_P_3, + }; + + enum +@@ -1010,7 +1075,8 @@ enum + PREFIX_0F38F0, + PREFIX_0F38F1, + PREFIX_0F38F6, +- PREFIX_0F38F8, ++ PREFIX_0F38F8_M_0, ++ PREFIX_0F38F8_M_1_X86_64, + PREFIX_0F38FA, + PREFIX_0F38FB, + PREFIX_0F38FC, +@@ -1069,10 +1135,13 @@ enum + PREFIX_VEX_0F38CC, + PREFIX_VEX_0F38CD, + PREFIX_VEX_0F38DA_W_0, ++ PREFIX_VEX_0F38F2_L_0, ++ PREFIX_VEX_0F38F3_L_0, + PREFIX_VEX_0F38F5_L_0, + PREFIX_VEX_0F38F6_L_0, + PREFIX_VEX_0F38F7_L_0, + PREFIX_VEX_0F3AF0_L_0, ++ PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, + + PREFIX_EVEX_0F5B, + PREFIX_EVEX_0F6F, +@@ -1130,6 +1199,11 @@ enum + PREFIX_EVEX_0F3A67, + PREFIX_EVEX_0F3AC2, + ++ PREFIX_EVEX_MAP4_F0, ++ PREFIX_EVEX_MAP4_F1, ++ PREFIX_EVEX_MAP4_F2, ++ PREFIX_EVEX_MAP4_F8, ++ + PREFIX_EVEX_MAP5_10, + PREFIX_EVEX_MAP5_11, + PREFIX_EVEX_MAP5_1D, +@@ -1217,6 +1291,7 @@ enum + X86_64_0F18_REG_7_MOD_0, + X86_64_0F24, + X86_64_0F26, ++ X86_64_0F38F8_M_1, + X86_64_0FC7_REG_6_MOD_3_PREFIX_1, + + X86_64_VEX_0F3849, +@@ -1240,6 +1315,8 @@ enum + X86_64_VEX_0F38ED, + X86_64_VEX_0F38EE, + X86_64_VEX_0F38EF, ++ ++ X86_64_VEX_MAP7_F8_L_0_W_0_R_0, + }; + + enum +@@ -1259,7 +1336,8 @@ enum + { + VEX_0F = 0, + VEX_0F38, +- VEX_0F3A ++ VEX_0F3A, ++ VEX_MAP7, + }; + + enum +@@ -1267,8 +1345,10 @@ enum + EVEX_0F = 0, + EVEX_0F38, + EVEX_0F3A, ++ EVEX_MAP4, + EVEX_MAP5, + EVEX_MAP6, ++ EVEX_MAP7, + }; + + enum +@@ -1350,6 +1430,7 @@ enum + VEX_LEN_0F3ADE_W_0, + VEX_LEN_0F3ADF, + VEX_LEN_0F3AF0, ++ VEX_LEN_MAP7_F8, + VEX_LEN_XOP_08_85, + VEX_LEN_XOP_08_86, + VEX_LEN_XOP_08_87, +@@ -1510,6 +1591,7 @@ enum + VEX_W_0F3ACE, + VEX_W_0F3ACF, + VEX_W_0F3ADE, ++ VEX_W_MAP7_F8_L_0, + + VEX_W_XOP_08_85_L_0, + VEX_W_XOP_08_86_L_0, +@@ -1656,6 +1738,11 @@ enum + EVEX_W_0F3A70, + EVEX_W_0F3A72, + ++ EVEX_W_MAP4_8F_R_0, ++ EVEX_W_MAP4_F8_P1_M_1, ++ EVEX_W_MAP4_F8_P3_M_1, ++ EVEX_W_MAP4_FF_R_6, ++ + EVEX_W_MAP5_5B_P_0, + EVEX_W_MAP5_7A_P_3, + }; +@@ -1673,7 +1760,7 @@ struct dis386 { + }; + + /* Upper case letters in the instruction names here are macros. +- 'A' => print 'b' if no register operands or suffix_always is true ++ 'A' => print 'b' if no (suitable) register operand or suffix_always is true + 'B' => print 'b' if suffix_always is true + 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand + size prefix +@@ -1686,14 +1773,14 @@ struct dis386 { + 'I' unused. + 'J' unused. + 'K' => print 'd' or 'q' if rex prefix is present. +- 'L' unused. ++ 'L' => print 'l' or 'q' if suffix_always is true + 'M' => print 'r' if intel_mnemonic is false. + 'N' => print 'n' if instruction has no wait "prefix" + 'O' => print 'd' or 'o' (or 'q' in Intel mode) + 'P' => behave as 'T' except with register operand outside of suffix_always + mode +- 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always +- is true ++ 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or ++ suffix_always is true + 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) + 'S' => print 'w', 'l' or 'q' if suffix_always is true + 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size +@@ -1724,6 +1811,11 @@ struct dis386 { + "XV" => print "{vex} " pseudo prefix + "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is + is used by an EVEX-encoded (AVX512VL) instruction. ++ "ME" => print "{evex} " pseudo prefix for ins->modrm.mod != 3,if no ++ EVEX-specific functionality is used by an EVEX-encoded (AVX512VL) ++ instruction. ++ "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} " ++ pseudo prefix when instructions without NF, EGPR and VVVV, + "YK" keep unused, to avoid ambiguity with the combined use of Y and K. + "YX" keep unused, to avoid ambiguity with the combined use of Y and X. + "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond +@@ -1836,23 +1928,23 @@ static const struct dis386 dis386[] = { + { "dec{S|}", { RMeSI }, 0 }, + { "dec{S|}", { RMeDI }, 0 }, + /* 50 */ +- { "push{!P|}", { RMrAX }, 0 }, +- { "push{!P|}", { RMrCX }, 0 }, +- { "push{!P|}", { RMrDX }, 0 }, +- { "push{!P|}", { RMrBX }, 0 }, +- { "push{!P|}", { RMrSP }, 0 }, +- { "push{!P|}", { RMrBP }, 0 }, +- { "push{!P|}", { RMrSI }, 0 }, +- { "push{!P|}", { RMrDI }, 0 }, ++ { "push!P", { RMrAX }, 0 }, ++ { "push!P", { RMrCX }, 0 }, ++ { "push!P", { RMrDX }, 0 }, ++ { "push!P", { RMrBX }, 0 }, ++ { "push!P", { RMrSP }, 0 }, ++ { "push!P", { RMrBP }, 0 }, ++ { "push!P", { RMrSI }, 0 }, ++ { "push!P", { RMrDI }, 0 }, + /* 58 */ +- { "pop{!P|}", { RMrAX }, 0 }, +- { "pop{!P|}", { RMrCX }, 0 }, +- { "pop{!P|}", { RMrDX }, 0 }, +- { "pop{!P|}", { RMrBX }, 0 }, +- { "pop{!P|}", { RMrSP }, 0 }, +- { "pop{!P|}", { RMrBP }, 0 }, +- { "pop{!P|}", { RMrSI }, 0 }, +- { "pop{!P|}", { RMrDI }, 0 }, ++ { "pop!P", { RMrAX }, 0 }, ++ { "pop!P", { RMrCX }, 0 }, ++ { "pop!P", { RMrDX }, 0 }, ++ { "pop!P", { RMrBX }, 0 }, ++ { "pop!P", { RMrSP }, 0 }, ++ { "pop!P", { RMrBP }, 0 }, ++ { "pop!P", { RMrSI }, 0 }, ++ { "pop!P", { RMrDI }, 0 }, + /* 60 */ + { X86_64_TABLE (X86_64_60) }, + { X86_64_TABLE (X86_64_61) }, +@@ -1872,23 +1964,23 @@ static const struct dis386 dis386[] = { + { "outs{b|}", { indirDXr, Xb }, 0 }, + { X86_64_TABLE (X86_64_6F) }, + /* 70 */ +- { "joH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jbH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jeH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jneH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jaH", { Jb, BND, cond_jump_flag }, 0 }, ++ { "joH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jnoH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jbH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jaeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jneH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jbeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jaH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, + /* 78 */ +- { "jsH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jpH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jlH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jleH", { Jb, BND, cond_jump_flag }, 0 }, +- { "jgH", { Jb, BND, cond_jump_flag }, 0 }, ++ { "jsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jnsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jnpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jlH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jgeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jleH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jgH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, + /* 80 */ + { REG_TABLE (REG_80) }, + { REG_TABLE (REG_81) }, +@@ -1926,23 +2018,23 @@ static const struct dis386 dis386[] = { + { "sahf", { XX }, 0 }, + { "lahf", { XX }, 0 }, + /* a0 */ +- { "mov%LB", { AL, Ob }, 0 }, +- { "mov%LS", { eAX, Ov }, 0 }, +- { "mov%LB", { Ob, AL }, 0 }, +- { "mov%LS", { Ov, eAX }, 0 }, +- { "movs{b|}", { Ybr, Xb }, 0 }, +- { "movs{R|}", { Yvr, Xv }, 0 }, +- { "cmps{b|}", { Xb, Yb }, 0 }, +- { "cmps{R|}", { Xv, Yv }, 0 }, ++ { "mov%LB", { AL, Ob }, PREFIX_REX2_ILLEGAL }, ++ { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL }, ++ { "mov%LB", { Ob, AL }, PREFIX_REX2_ILLEGAL }, ++ { "mov%LS", { Ov, eAX }, PREFIX_REX2_ILLEGAL }, ++ { "movs{b|}", { Ybr, Xb }, PREFIX_REX2_ILLEGAL }, ++ { "movs{R|}", { Yvr, Xv }, PREFIX_REX2_ILLEGAL }, ++ { "cmps{b|}", { Xb, Yb }, PREFIX_REX2_ILLEGAL }, ++ { "cmps{R|}", { Xv, Yv }, PREFIX_REX2_ILLEGAL }, + /* a8 */ +- { "testB", { AL, Ib }, 0 }, +- { "testS", { eAX, Iv }, 0 }, +- { "stosB", { Ybr, AL }, 0 }, +- { "stosS", { Yvr, eAX }, 0 }, +- { "lodsB", { ALr, Xb }, 0 }, +- { "lodsS", { eAXr, Xv }, 0 }, +- { "scasB", { AL, Yb }, 0 }, +- { "scasS", { eAX, Yv }, 0 }, ++ { "testB", { AL, Ib }, PREFIX_REX2_ILLEGAL }, ++ { "testS", { eAX, Iv }, PREFIX_REX2_ILLEGAL }, ++ { "stosB", { Ybr, AL }, PREFIX_REX2_ILLEGAL }, ++ { "stosS", { Yvr, eAX }, PREFIX_REX2_ILLEGAL }, ++ { "lodsB", { ALr, Xb }, PREFIX_REX2_ILLEGAL }, ++ { "lodsS", { eAXr, Xv }, PREFIX_REX2_ILLEGAL }, ++ { "scasB", { AL, Yb }, PREFIX_REX2_ILLEGAL }, ++ { "scasS", { eAX, Yv }, PREFIX_REX2_ILLEGAL }, + /* b0 */ + { "movB", { RMAL, Ib }, 0 }, + { "movB", { RMCL, Ib }, 0 }, +@@ -1998,23 +2090,23 @@ static const struct dis386 dis386[] = { + { FLOAT }, + { FLOAT }, + /* e0 */ +- { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, +- { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, +- { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, +- { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, +- { "inB", { AL, Ib }, 0 }, +- { "inG", { zAX, Ib }, 0 }, +- { "outB", { Ib, AL }, 0 }, +- { "outG", { Ib, zAX }, 0 }, ++ { "loopneFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, ++ { "loopeFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, ++ { "loopFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jEcxzH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, ++ { "inB", { AL, Ib }, PREFIX_REX2_ILLEGAL }, ++ { "inG", { zAX, Ib }, PREFIX_REX2_ILLEGAL }, ++ { "outB", { Ib, AL }, PREFIX_REX2_ILLEGAL }, ++ { "outG", { Ib, zAX }, PREFIX_REX2_ILLEGAL }, + /* e8 */ + { X86_64_TABLE (X86_64_E8) }, + { X86_64_TABLE (X86_64_E9) }, + { X86_64_TABLE (X86_64_EA) }, +- { "jmp", { Jb, BND }, 0 }, +- { "inB", { AL, indirDX }, 0 }, +- { "inG", { zAX, indirDX }, 0 }, +- { "outB", { indirDX, AL }, 0 }, +- { "outG", { indirDX, zAX }, 0 }, ++ { "jmp", { Jb, BND }, PREFIX_REX2_ILLEGAL }, ++ { "inB", { AL, indirDX }, PREFIX_REX2_ILLEGAL }, ++ { "inG", { zAX, indirDX }, PREFIX_REX2_ILLEGAL }, ++ { "outB", { indirDX, AL }, PREFIX_REX2_ILLEGAL }, ++ { "outG", { indirDX, zAX }, PREFIX_REX2_ILLEGAL }, + /* f0 */ + { Bad_Opcode }, /* lock prefix */ + { "int1", { XX }, 0 }, +@@ -2091,12 +2183,12 @@ static const struct dis386 dis386_twobyte[] = { + { PREFIX_TABLE (PREFIX_0F2E) }, + { PREFIX_TABLE (PREFIX_0F2F) }, + /* 30 */ +- { "wrmsr", { XX }, 0 }, +- { "rdtsc", { XX }, 0 }, +- { "rdmsr", { XX }, 0 }, +- { "rdpmc", { XX }, 0 }, +- { "sysenter", { SEP }, 0 }, +- { "sysexit%LQ", { SEP }, 0 }, ++ { "wrmsr", { XX }, PREFIX_REX2_ILLEGAL }, ++ { "rdtsc", { XX }, PREFIX_REX2_ILLEGAL }, ++ { "rdmsr", { XX }, PREFIX_REX2_ILLEGAL }, ++ { "rdpmc", { XX }, PREFIX_REX2_ILLEGAL }, ++ { "sysenter", { SEP }, PREFIX_REX2_ILLEGAL }, ++ { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL }, + { Bad_Opcode }, + { "getsec", { XX }, 0 }, + /* 38 */ +@@ -2181,23 +2273,23 @@ static const struct dis386 dis386_twobyte[] = { + { PREFIX_TABLE (PREFIX_0F7E) }, + { PREFIX_TABLE (PREFIX_0F7F) }, + /* 80 */ +- { "joH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jbH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jeH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jneH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jaH", { Jv, BND, cond_jump_flag }, 0 }, ++ { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, + /* 88 */ +- { "jsH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jpH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jlH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jleH", { Jv, BND, cond_jump_flag }, 0 }, +- { "jgH", { Jv, BND, cond_jump_flag }, 0 }, ++ { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, ++ { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, + /* 90 */ + { "seto", { Eb }, 0 }, + { "setno", { Eb }, 0 }, +@@ -2390,22 +2482,30 @@ static const char intel_index16[][6] = { + + static const char att_names64[][8] = { + "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", +- "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" ++ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", ++ "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", ++ "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", + }; + static const char att_names32[][8] = { + "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", +- "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" ++ "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d", ++ "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d", ++ "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d", + }; + static const char att_names16[][8] = { + "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", +- "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" ++ "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w", ++ "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w", ++ "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w", + }; + static const char att_names8[][8] = { + "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", + }; + static const char att_names8rex[][8] = { + "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", +- "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" ++ "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b", ++ "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b", ++ "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b", + }; + static const char att_names_seg[][4] = { + "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", +@@ -2520,25 +2620,25 @@ static const struct dis386 reg_table[][8] = { + }, + /* REG_C0 */ + { +- { "rolA", { Eb, Ib }, 0 }, +- { "rorA", { Eb, Ib }, 0 }, +- { "rclA", { Eb, Ib }, 0 }, +- { "rcrA", { Eb, Ib }, 0 }, +- { "shlA", { Eb, Ib }, 0 }, +- { "shrA", { Eb, Ib }, 0 }, +- { "shlA", { Eb, Ib }, 0 }, +- { "sarA", { Eb, Ib }, 0 }, ++ { "%NFrolA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFrorA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "rclA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFshrA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX }, ++ { "%NFsarA", { VexGb, Eb, Ib }, NO_PREFIX }, + }, + /* REG_C1 */ + { +- { "rolQ", { Ev, Ib }, 0 }, +- { "rorQ", { Ev, Ib }, 0 }, +- { "rclQ", { Ev, Ib }, 0 }, +- { "rcrQ", { Ev, Ib }, 0 }, +- { "shlQ", { Ev, Ib }, 0 }, +- { "shrQ", { Ev, Ib }, 0 }, +- { "shlQ", { Ev, Ib }, 0 }, +- { "sarQ", { Ev, Ib }, 0 }, ++ { "%NFrolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, ++ { "%NFrorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, ++ { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, ++ { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, ++ { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, ++ { "%NFshrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, ++ { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, ++ { "%NFsarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, + }, + /* REG_C6 */ + { +@@ -2564,47 +2664,47 @@ static const struct dis386 reg_table[][8] = { + }, + /* REG_D0 */ + { +- { "rolA", { Eb, I1 }, 0 }, +- { "rorA", { Eb, I1 }, 0 }, +- { "rclA", { Eb, I1 }, 0 }, +- { "rcrA", { Eb, I1 }, 0 }, +- { "shlA", { Eb, I1 }, 0 }, +- { "shrA", { Eb, I1 }, 0 }, +- { "shlA", { Eb, I1 }, 0 }, +- { "sarA", { Eb, I1 }, 0 }, ++ { "%NFrolA", { VexGb, Eb, I1 }, NO_PREFIX }, ++ { "%NFrorA", { VexGb, Eb, I1 }, NO_PREFIX }, ++ { "rclA", { VexGb, Eb, I1 }, NO_PREFIX }, ++ { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX }, ++ { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX }, ++ { "%NFshrA", { VexGb, Eb, I1 }, NO_PREFIX }, ++ { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX }, ++ { "%NFsarA", { VexGb, Eb, I1 }, NO_PREFIX }, + }, + /* REG_D1 */ + { +- { "rolQ", { Ev, I1 }, 0 }, +- { "rorQ", { Ev, I1 }, 0 }, +- { "rclQ", { Ev, I1 }, 0 }, +- { "rcrQ", { Ev, I1 }, 0 }, +- { "shlQ", { Ev, I1 }, 0 }, +- { "shrQ", { Ev, I1 }, 0 }, +- { "shlQ", { Ev, I1 }, 0 }, +- { "sarQ", { Ev, I1 }, 0 }, ++ { "%NFrolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, ++ { "%NFrorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, ++ { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, ++ { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, ++ { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, ++ { "%NFshrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, ++ { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, ++ { "%NFsarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, + }, + /* REG_D2 */ + { +- { "rolA", { Eb, CL }, 0 }, +- { "rorA", { Eb, CL }, 0 }, +- { "rclA", { Eb, CL }, 0 }, +- { "rcrA", { Eb, CL }, 0 }, +- { "shlA", { Eb, CL }, 0 }, +- { "shrA", { Eb, CL }, 0 }, +- { "shlA", { Eb, CL }, 0 }, +- { "sarA", { Eb, CL }, 0 }, ++ { "%NFrolA", { VexGb, Eb, CL }, NO_PREFIX }, ++ { "%NFrorA", { VexGb, Eb, CL }, NO_PREFIX }, ++ { "rclA", { VexGb, Eb, CL }, NO_PREFIX }, ++ { "rcrA", { VexGb, Eb, CL }, NO_PREFIX }, ++ { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX }, ++ { "%NFshrA", { VexGb, Eb, CL }, NO_PREFIX }, ++ { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX }, ++ { "%NFsarA", { VexGb, Eb, CL }, NO_PREFIX }, + }, + /* REG_D3 */ + { +- { "rolQ", { Ev, CL }, 0 }, +- { "rorQ", { Ev, CL }, 0 }, +- { "rclQ", { Ev, CL }, 0 }, +- { "rcrQ", { Ev, CL }, 0 }, +- { "shlQ", { Ev, CL }, 0 }, +- { "shrQ", { Ev, CL }, 0 }, +- { "shlQ", { Ev, CL }, 0 }, +- { "sarQ", { Ev, CL }, 0 }, ++ { "%NFrolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, ++ { "%NFrorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, ++ { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, ++ { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, ++ { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, ++ { "%NFshrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, ++ { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, ++ { "%NFsarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, + }, + /* REG_F6 */ + { +@@ -2794,9 +2894,9 @@ static const struct dis386 reg_table[][8] = { + { Bad_Opcode }, + { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, + { Bad_Opcode }, +- { "xrstors", { FXSAVE }, 0 }, +- { "xsavec", { FXSAVE }, 0 }, +- { "xsaves", { FXSAVE }, 0 }, ++ { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL }, ++ { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL }, ++ { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL }, + { MOD_TABLE (MOD_0FC7_REG_6) }, + { MOD_TABLE (MOD_0FC7_REG_7) }, + }, +@@ -2842,12 +2942,16 @@ static const struct dis386 reg_table[][8] = { + { + { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) }, + }, +- /* REG_VEX_0F38F3_L_0 */ ++ /* REG_VEX_0F38F3_L_0_P_0 */ + { + { Bad_Opcode }, +- { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE }, +- { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, +- { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, ++ { "%NFblsrS", { VexGdq, Edq }, 0 }, ++ { "%NFblsmskS", { VexGdq, Edq }, 0 }, ++ { "%NFblsiS", { VexGdq, Edq }, 0 }, ++ }, ++ /* REG_VEX_MAP7_F8_L_0_W_0 */ ++ { ++ { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, + }, + /* REG_XOP_09_01_L_0 */ + { +@@ -3364,7 +3468,7 @@ static const struct dis386 prefix_table[][4] = { + + /* PREFIX_0FAE_REG_4_MOD_0 */ + { +- { "xsave", { FXSAVE }, 0 }, ++ { "xsave", { FXSAVE }, PREFIX_REX2_ILLEGAL }, + { "ptwrite{%LQ|}", { Edq }, 0 }, + }, + +@@ -3382,7 +3486,7 @@ static const struct dis386 prefix_table[][4] = { + + /* PREFIX_0FAE_REG_6_MOD_0 */ + { +- { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, ++ { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL }, + { "clrssbsy", { Mq }, PREFIX_OPCODE }, + { "clwb", { Mb }, PREFIX_OPCODE }, + }, +@@ -3550,18 +3654,27 @@ static const struct dis386 prefix_table[][4] = { + /* PREFIX_0F38F6 */ + { + { "wrssK", { M, Gdq }, 0 }, +- { "adoxS", { Gdq, Edq}, 0 }, +- { "adcxS", { Gdq, Edq}, 0 }, ++ { "adoxL", { VexGdq, Gdq, Edq }, 0 }, ++ { "adcxL", { VexGdq, Gdq, Edq }, 0 }, + { Bad_Opcode }, + }, + +- /* PREFIX_0F38F8 */ ++ /* PREFIX_0F38F8_M_0 */ + { + { Bad_Opcode }, + { "enqcmds", { Gva, M }, 0 }, + { "movdir64b", { Gva, M }, 0 }, + { "enqcmd", { Gva, M }, 0 }, + }, ++ ++ /* PREFIX_0F38F8_M_1_X86_64 */ ++ { ++ { Bad_Opcode }, ++ { "uwrmsr", { Gq, Rq }, 0 }, ++ { Bad_Opcode }, ++ { "urdmsr", { Rq, Gq }, 0 }, ++ }, ++ + /* PREFIX_0F38FA */ + { + { Bad_Opcode }, +@@ -3768,38 +3881,38 @@ static const struct dis386 prefix_table[][4] = { + + /* PREFIX_VEX_0F90_L_0_W_0 */ + { +- { "kmovw", { MaskG, MaskE }, 0 }, ++ { "%XEkmovw", { MaskG, MaskE }, 0 }, + { Bad_Opcode }, +- { "kmovb", { MaskG, MaskBDE }, 0 }, ++ { "%XEkmovb", { MaskG, MaskBDE }, 0 }, + }, + + /* PREFIX_VEX_0F90_L_0_W_1 */ + { +- { "kmovq", { MaskG, MaskE }, 0 }, ++ { "%XEkmovq", { MaskG, MaskE }, 0 }, + { Bad_Opcode }, +- { "kmovd", { MaskG, MaskBDE }, 0 }, ++ { "%XEkmovd", { MaskG, MaskBDE }, 0 }, + }, + + /* PREFIX_VEX_0F91_L_0_W_0 */ + { +- { "kmovw", { Mw, MaskG }, 0 }, ++ { "%XEkmovw", { Mw, MaskG }, 0 }, + { Bad_Opcode }, +- { "kmovb", { Mb, MaskG }, 0 }, ++ { "%XEkmovb", { Mb, MaskG }, 0 }, + }, + + /* PREFIX_VEX_0F91_L_0_W_1 */ + { +- { "kmovq", { Mq, MaskG }, 0 }, ++ { "%XEkmovq", { Mq, MaskG }, 0 }, + { Bad_Opcode }, +- { "kmovd", { Md, MaskG }, 0 }, ++ { "%XEkmovd", { Md, MaskG }, 0 }, + }, + + /* PREFIX_VEX_0F92_L_0_W_0 */ + { +- { "kmovw", { MaskG, Rdq }, 0 }, ++ { "%XEkmovw", { MaskG, Rdq }, 0 }, + { Bad_Opcode }, +- { "kmovb", { MaskG, Rdq }, 0 }, +- { "kmovd", { MaskG, Rdq }, 0 }, ++ { "%XEkmovb", { MaskG, Rdq }, 0 }, ++ { "%XEkmovd", { MaskG, Rdq }, 0 }, + }, + + /* PREFIX_VEX_0F92_L_0_W_1 */ +@@ -3807,15 +3920,15 @@ static const struct dis386 prefix_table[][4] = { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, +- { "kmovK", { MaskG, Rdq }, 0 }, ++ { "%XEkmovK", { MaskG, Rdq }, 0 }, + }, + + /* PREFIX_VEX_0F93_L_0_W_0 */ + { +- { "kmovw", { Gdq, MaskR }, 0 }, ++ { "%XEkmovw", { Gdq, MaskR }, 0 }, + { Bad_Opcode }, +- { "kmovb", { Gdq, MaskR }, 0 }, +- { "kmovd", { Gdq, MaskR }, 0 }, ++ { "%XEkmovb", { Gdq, MaskR }, 0 }, ++ { "%XEkmovd", { Gdq, MaskR }, 0 }, + }, + + /* PREFIX_VEX_0F93_L_0_W_1 */ +@@ -3823,7 +3936,7 @@ static const struct dis386 prefix_table[][4] = { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, +- { "kmovK", { Gdq, MaskR }, 0 }, ++ { "%XEkmovK", { Gdq, MaskR }, 0 }, + }, + + /* PREFIX_VEX_0F98_L_0_W_0 */ +@@ -3982,12 +4095,22 @@ static const struct dis386 prefix_table[][4] = { + { "vsm4rnds4", { XM, Vex, EXx }, 0 }, + }, + ++ /* PREFIX_VEX_0F38F2_L_0 */ ++ { ++ { "%NFandnS", { Gdq, VexGdq, Edq }, 0 }, ++ }, ++ ++ /* PREFIX_VEX_0F38F3_L_0 */ ++ { ++ { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) }, ++ }, ++ + /* PREFIX_VEX_0F38F5_L_0 */ + { +- { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, +- { "pextS", { Gdq, VexGdq, Edq }, 0 }, ++ { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 }, ++ { "%XEpextS", { Gdq, VexGdq, Edq }, 0 }, + { Bad_Opcode }, +- { "pdepS", { Gdq, VexGdq, Edq }, 0 }, ++ { "%XEpdepS", { Gdq, VexGdq, Edq }, 0 }, + }, + + /* PREFIX_VEX_0F38F6_L_0 */ +@@ -3995,15 +4118,15 @@ static const struct dis386 prefix_table[][4] = { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, +- { "mulxS", { Gdq, VexGdq, Edq }, 0 }, ++ { "%XEmulxS", { Gdq, VexGdq, Edq }, 0 }, + }, + + /* PREFIX_VEX_0F38F7_L_0 */ + { +- { "bextrS", { Gdq, Edq, VexGdq }, 0 }, +- { "sarxS", { Gdq, Edq, VexGdq }, 0 }, +- { "shlxS", { Gdq, Edq, VexGdq }, 0 }, +- { "shrxS", { Gdq, Edq, VexGdq }, 0 }, ++ { "%NFbextrS", { Gdq, Edq, VexGdq }, 0 }, ++ { "%XEsarxS", { Gdq, Edq, VexGdq }, 0 }, ++ { "%XEshlxS", { Gdq, Edq, VexGdq }, 0 }, ++ { "%XEshrxS", { Gdq, Edq, VexGdq }, 0 }, + }, + + /* PREFIX_VEX_0F3AF0_L_0 */ +@@ -4011,7 +4134,15 @@ static const struct dis386 prefix_table[][4] = { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, +- { "rorxS", { Gdq, Edq, Ib }, 0 }, ++ { "%XErorxS", { Gdq, Edq, Ib }, 0 }, ++ }, ++ ++ /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ ++ { ++ { Bad_Opcode }, ++ { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, ++ { Bad_Opcode }, ++ { "urdmsr", { Rq, Id }, 0 }, + }, + + #include "i386-dis-evex-prefix.h" +@@ -4160,13 +4291,13 @@ static const struct dis386 x86_64_table[][2] = { + /* X86_64_E8 */ + { + { "callP", { Jv, BND }, 0 }, +- { "call@", { Jv, BND }, 0 } ++ { "call@", { Jv, BND }, PREFIX_REX2_ILLEGAL } + }, + + /* X86_64_E9 */ + { + { "jmpP", { Jv, BND }, 0 }, +- { "jmp@", { Jv, BND }, 0 } ++ { "jmp@", { Jv, BND }, PREFIX_REX2_ILLEGAL } + }, + + /* X86_64_EA */ +@@ -4322,6 +4453,12 @@ static const struct dis386 x86_64_table[][2] = { + { "movZ", { Td, Em }, 0 }, + }, + ++ { ++ /* X86_64_0F38F8_M_1 */ ++ { Bad_Opcode }, ++ { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, ++ }, ++ + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ + { + { Bad_Opcode }, +@@ -4361,97 +4498,103 @@ static const struct dis386 x86_64_table[][2] = { + /* X86_64_VEX_0F38E0 */ + { + { Bad_Opcode }, +- { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E1 */ + { + { Bad_Opcode }, +- { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E2 */ + { + { Bad_Opcode }, +- { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E3 */ + { + { Bad_Opcode }, +- { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E4 */ + { + { Bad_Opcode }, +- { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E5 */ + { + { Bad_Opcode }, +- { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E6 */ + { + { Bad_Opcode }, +- { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E7 */ + { + { Bad_Opcode }, +- { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E8 */ + { + { Bad_Opcode }, +- { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E9 */ + { + { Bad_Opcode }, +- { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EA */ + { + { Bad_Opcode }, +- { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EB */ + { + { Bad_Opcode }, +- { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EC */ + { + { Bad_Opcode }, +- { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38ED */ + { + { Bad_Opcode }, +- { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EE */ + { + { Bad_Opcode }, +- { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EF */ + { + { Bad_Opcode }, +- { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ { "%XEcmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, ++ }, ++ ++ /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ ++ { ++ { Bad_Opcode }, ++ { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, + }, + }; + +@@ -4739,7 +4882,7 @@ static const struct dis386 three_byte_table[][256] = { + { PREFIX_TABLE (PREFIX_0F38F6) }, + { Bad_Opcode }, + /* f8 */ +- { PREFIX_TABLE (PREFIX_0F38F8) }, ++ { MOD_TABLE (MOD_0F38F8) }, + { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, + { PREFIX_TABLE (PREFIX_0F38FA) }, + { PREFIX_TABLE (PREFIX_0F38FB) }, +@@ -7039,12 +7182,12 @@ static const struct dis386 vex_len_table[][2] = { + + /* VEX_LEN_0F38F2 */ + { +- { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE }, ++ { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) }, + }, + + /* VEX_LEN_0F38F3 */ + { +- { REG_TABLE(REG_VEX_0F38F3_L_0) }, ++ { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) }, + }, + + /* VEX_LEN_0F38F5 */ +@@ -7205,6 +7348,11 @@ static const struct dis386 vex_len_table[][2] = { + { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, + }, + ++ /* VEX_LEN_MAP7_F8 */ ++ { ++ { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, ++ }, ++ + /* VEX_LEN_XOP_08_85 */ + { + { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, +@@ -7811,6 +7959,10 @@ static const struct dis386 vex_w_table[][2] = { + /* VEX_W_0F3ADE */ + { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, + }, ++ { ++ /* VEX_W_MAP7_F8_L_0 */ ++ { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, ++ }, + /* VEX_W_XOP_08_85_L_0 */ + { + { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, +@@ -8125,7 +8277,7 @@ static const struct dis386 mod_table[][2] = { + }, + { + /* MOD_0FAE_REG_5 */ +- { "xrstor", { FXSAVE }, PREFIX_OPCODE }, ++ { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL }, + { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, + }, + { +@@ -8153,6 +8305,11 @@ static const struct dis386 mod_table[][2] = { + { "aesenc128kl", { XM, M }, 0 }, + { "loadiwkey", { XM, EXx }, 0 }, + }, ++ /* MOD_0F38F8 */ ++ { ++ { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, ++ { X86_64_TABLE (X86_64_0F38F8_M_1) }, ++ }, + { + /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ + { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, +@@ -8323,6 +8480,24 @@ ckprefix (instr_info *ins) + return ckp_okay; + ins->last_rex_prefix = i; + break; ++ /* REX2 must be the last prefix. */ ++ case REX2_OPCODE: ++ if (ins->address_mode == mode_64bit) ++ { ++ if (ins->last_rex_prefix >= 0) ++ return ckp_bogus; ++ ++ ins->codep++; ++ if (!fetch_code (ins->info, ins->codep + 1)) ++ return ckp_fetch_error; ++ ins->rex2_payload = *ins->codep; ++ ins->rex2 = ins->rex2_payload >> 4; ++ ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE; ++ ins->codep++; ++ ins->last_rex2_prefix = i; ++ ins->all_prefixes[i] = REX2_OPCODE; ++ } ++ return ckp_okay; + case 0xf3: + ins->prefixes |= PREFIX_REPZ; + ins->last_repz_prefix = i; +@@ -8490,6 +8665,8 @@ prefix_name (enum address_mode mode, uint8_t pref, int sizeflag) + return "bnd"; + case NOTRACK_PREFIX: + return "notrack"; ++ case REX2_OPCODE: ++ return "rex2"; + default: + return NULL; + } +@@ -8507,10 +8684,10 @@ with the -M switch (multiple options should be separated by commas):\n")); + fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); + fprintf (stream, _(" att Display instruction in AT&T syntax\n")); + fprintf (stream, _(" intel Display instruction in Intel syntax\n")); +- fprintf (stream, _(" att-mnemonic\n" +- " Display instruction in AT&T mnemonic\n")); +- fprintf (stream, _(" intel-mnemonic\n" +- " Display instruction in Intel mnemonic\n")); ++ fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n" ++ " Display instruction with AT&T mnemonic\n")); ++ fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n" ++ " Display instruction with Intel mnemonic\n")); + fprintf (stream, _(" addr64 Assume 64bit address size\n")); + fprintf (stream, _(" addr32 Assume 32bit address size\n")); + fprintf (stream, _(" addr16 Assume 16bit address size\n")); +@@ -8527,6 +8704,8 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; + /* Fetch error indicator. */ + static const struct dis386 err_opcode = { NULL, { XX }, 0 }; + ++static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; ++ + /* Get a pointer to struct dis386 with a valid name. */ + + static const struct dis386 * +@@ -8553,6 +8732,7 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + break; + + case USE_PREFIX_TABLE: ++ use_prefix_table: + if (ins->need_vex) + { + /* The prefix in VEX is implicit. */ +@@ -8622,12 +8802,40 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + dp = &prefix_table[dp->op[1].bytemode][vindex]; + break; + ++ case USE_X86_64_EVEX_FROM_VEX_TABLE: ++ case USE_X86_64_EVEX_PFX_TABLE: ++ case USE_X86_64_EVEX_W_TABLE: ++ case USE_X86_64_EVEX_MEM_W_TABLE: ++ ins->evex_type = evex_from_vex; ++ /* EVEX from VEX instructions are 64-bit only and require that EVEX.z, ++ EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0. */ ++ if (ins->address_mode != mode_64bit ++ || (ins->vex.mask_register_specifier & 0x3) != 0 ++ || ins->vex.ll != 0 ++ || ins->vex.zeroing != 0 ++ || ins->vex.b) ++ return &bad_opcode; ++ ++ if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE) ++ goto use_prefix_table; ++ if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE) ++ goto use_vex_w_table; ++ if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE) ++ { ++ if (ins->modrm.mod == 3) ++ return &bad_opcode; ++ goto use_vex_w_table; ++ } ++ ++ /* Fall through. */ + case USE_X86_64_TABLE: + vindex = ins->address_mode == mode_64bit ? 1 : 0; + dp = &x86_64_table[dp->op[1].bytemode][vindex]; + break; + + case USE_3BYTE_TABLE: ++ if (ins->last_rex2_prefix >= 0) ++ return &err_opcode; + if (!fetch_code (ins->info, ins->codep + 2)) + return &err_opcode; + vindex = *ins->codep++; +@@ -8769,6 +8977,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + case 0x3: + vex_table_index = VEX_0F3A; + break; ++ case 0x7: ++ vex_table_index = VEX_MAP7; ++ break; + } + ins->codep++; + ins->vex.w = *ins->codep & 0x80; +@@ -8803,7 +9014,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + ins->need_vex = 3; + ins->codep++; + vindex = *ins->codep++; +- dp = &vex_table[vex_table_index][vindex]; ++ if (vex_table_index != VEX_MAP7) ++ dp = &vex_table[vex_table_index][vindex]; ++ else if (vindex == 0xf8) ++ dp = &map7_f8_opcode; ++ else ++ dp = &bad_opcode; + ins->end_codep = ins->codep; + /* There is no MODRM byte for VEX0F 77. */ + if ((vex_table_index != VEX_0F || vindex != 0x77) +@@ -8846,6 +9062,7 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + break; + + case USE_VEX_W_TABLE: ++ use_vex_w_table: + if (!ins->need_vex) + abort (); + +@@ -8859,9 +9076,13 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + if (!fetch_code (ins->info, ins->codep + 4)) + return &err_opcode; + /* The first byte after 0x62. */ ++ if (*ins->codep & 0x8) ++ ins->rex2 |= REX_B; ++ if (!(*ins->codep & 0x10)) ++ ins->rex2 |= REX_R; ++ + ins->rex = ~(*ins->codep >> 5) & 0x7; +- ins->vex.r = *ins->codep & 0x10; +- switch ((*ins->codep & 0xf)) ++ switch (*ins->codep & 0x7) + { + default: + return &bad_opcode; +@@ -8874,12 +9095,21 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + case 0x3: + vex_table_index = EVEX_0F3A; + break; ++ case 0x4: ++ vex_table_index = EVEX_MAP4; ++ ins->evex_type = evex_from_legacy; ++ if (ins->address_mode != mode_64bit) ++ return &bad_opcode; ++ break; + case 0x5: + vex_table_index = EVEX_MAP5; + break; + case 0x6: + vex_table_index = EVEX_MAP6; + break; ++ case 0x7: ++ vex_table_index = EVEX_MAP7; ++ break; + } + + /* The second byte after 0x62. */ +@@ -8890,9 +9120,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + + ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; + +- /* The U bit. */ + if (!(*ins->codep & 0x4)) +- return &bad_opcode; ++ ins->rex2 |= REX_X; + + switch ((*ins->codep & 0x3)) + { +@@ -8919,24 +9148,54 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) + ins->vex.v = *ins->codep & 0x8; + ins->vex.mask_register_specifier = *ins->codep & 0x7; + ins->vex.zeroing = *ins->codep & 0x80; ++ /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared ++ when it's an evex_default one. */ ++ ins->vex.nf = *ins->codep & 0x4; + + if (ins->address_mode != mode_64bit) + { ++ /* Report bad for !evex_default and when two fixed values of evex ++ change.. */ ++ if (ins->evex_type != evex_default ++ || (ins->rex2 & (REX_B | REX_X))) ++ return &bad_opcode; + /* In 16/32-bit mode silently ignore following bits. */ + ins->rex &= ~REX_B; +- ins->vex.r = true; ++ ins->rex2 &= ~REX_R; + } + ++ /* EVEX from legacy instructions, when the EVEX.ND bit is 0, ++ all bits of EVEX.vvvv and EVEX.V' must be 1. */ ++ if (ins->evex_type == evex_from_legacy && !ins->vex.nd ++ && (ins->vex.register_specifier || !ins->vex.v)) ++ return &bad_opcode; ++ + ins->need_vex = 4; ++ ++ /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the ++ lower 2 bits of EVEX.aaa must be 0. */ ++ if (ins->evex_type == evex_from_legacy ++ && ((ins->vex.mask_register_specifier & 0x3) != 0 ++ || ins->vex.ll != 0 ++ || ins->vex.zeroing != 0)) ++ return &bad_opcode; ++ + ins->codep++; + vindex = *ins->codep++; +- dp = &evex_table[vex_table_index][vindex]; ++ if (vex_table_index != EVEX_MAP7) ++ dp = &evex_table[vex_table_index][vindex]; ++ else if (vindex == 0xf8) ++ dp = &map7_f8_opcode; ++ else ++ dp = &bad_opcode; + ins->end_codep = ins->codep; + if (!fetch_modrm (ins)) + return &err_opcode; + +- /* Set vector length. */ +- if (ins->modrm.mod == 3 && ins->vex.b) ++ /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00, ++ which has the same encoding as vex.length == 128 and they can share ++ the same processing with vex.length in OP_VEX. */ ++ if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy) + ins->vex.length = 512; + else + { +@@ -9128,6 +9387,7 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + .last_data_prefix = -1, + .last_addr_prefix = -1, + .last_rex_prefix = -1, ++ .last_rex2_prefix = -1, + .last_seg_prefix = -1, + .fwait_prefix = -1, + }; +@@ -9167,9 +9427,10 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + } + else if (startswith (p, "intel")) + { +- ins.intel_syntax = 1; + if (startswith (p + 5, "-mnemonic")) + ins.intel_mnemonic = true; ++ else ++ ins.intel_syntax = 1; + } + else if (startswith (p, "att")) + { +@@ -9292,24 +9553,25 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + goto out; + } + +- if (*ins.codep == 0x0f) ++ /* REX2.M in rex2 prefix represents map0 or map1. */ ++ if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M)) + { +- unsigned char threebyte; ++ if (!ins.rex2) ++ { ++ ins.codep++; ++ if (!fetch_code (info, ins.codep + 1)) ++ goto fetch_error_out; ++ } + +- ins.codep++; +- if (!fetch_code (info, ins.codep + 1)) +- goto fetch_error_out; +- threebyte = *ins.codep; +- dp = &dis386_twobyte[threebyte]; +- ins.need_modrm = twobyte_has_modrm[threebyte]; +- ins.codep++; ++ dp = &dis386_twobyte[*ins.codep]; ++ ins.need_modrm = twobyte_has_modrm[*ins.codep]; + } + else + { + dp = &dis386[*ins.codep]; + ins.need_modrm = onebyte_has_modrm[*ins.codep]; +- ins.codep++; + } ++ ins.codep++; + + /* Save sizeflag for printing the extra ins.prefixes later before updating + it for mnemonic and operand processing. The prefix names depend +@@ -9335,6 +9597,22 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + dp = get_valid_dis386 (dp, &ins); + if (dp == &err_opcode) + goto fetch_error_out; ++ ++ /* For APX instructions promoted from legacy maps 0/1, embedded prefix ++ is interpreted as the operand size override. */ ++ if (ins.evex_type == evex_from_legacy ++ && ins.vex.prefix == DATA_PREFIX_OPCODE) ++ sizeflag ^= DFLAG; ++ ++ if(ins.evex_type == evex_default) ++ ins.vex.nf = false; ++ else ++ /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest ++ are cleared separately.) in mask_register_specifier and keep the low ++ 2 bits of mask_register_specifier to report errors for invalid cases ++ . */ ++ ins.vex.mask_register_specifier &= 0x3; ++ + if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0) + { + if (!get_sib (&ins, sizeflag)) +@@ -9387,10 +9665,13 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + oappend (&ins, "/(bad)"); + } + } ++ /* vex.nf is cleared after being consumed. */ ++ if (ins.vex.nf) ++ oappend (&ins, "{bad-nf}"); + + /* Check whether rounding control was enabled for an insn not +- supporting it. */ +- if (ins.modrm.mod == 3 && ins.vex.b ++ supporting it, when evex.b is not treated as evex.nd. */ ++ if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default + && !(ins.evex_used & EVEX_b_used)) + { + for (i = 0; i < MAX_OPERANDS; ++i) +@@ -9454,7 +9735,15 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + goto out; + } + +- switch (dp->prefix_requirement) ++ if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL) ++ && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0) ++ { ++ i386_dis_printf (info, dis_style_text, "(bad)"); ++ ret = ins.end_codep - priv.the_buffer; ++ goto out; ++ } ++ ++ switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL) + { + case PREFIX_DATA: + /* If only the data prefix is marked as mandatory, its absence renders +@@ -9506,6 +9795,25 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + if (ins.last_repnz_prefix >= 0) + ins.all_prefixes[ins.last_repnz_prefix] = 0xf2; + break; ++ ++ case PREFIX_NP_OR_DATA: ++ if (ins.vex.prefix == REPE_PREFIX_OPCODE ++ || ins.vex.prefix == REPNE_PREFIX_OPCODE) ++ { ++ i386_dis_printf (info, dis_style_text, "(bad)"); ++ ret = ins.end_codep - priv.the_buffer; ++ goto out; ++ } ++ break; ++ ++ case NO_PREFIX: ++ if (ins.vex.prefix) ++ { ++ i386_dis_printf (info, dis_style_text, "(bad)"); ++ ret = ins.end_codep - priv.the_buffer; ++ goto out; ++ } ++ break; + } + + /* Check if the REX prefix is used. */ +@@ -9513,6 +9821,14 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + && !ins.need_vex && ins.last_rex_prefix >= 0) + ins.all_prefixes[ins.last_rex_prefix] = 0; + ++ /* Check if the REX2 prefix is used. */ ++ if (ins.last_rex2_prefix >= 0 ++ && ((ins.rex2 & REX2_SPECIAL) ++ || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0 ++ && (ins.rex ^ ins.rex_used) == 0 ++ && (ins.rex2 & 7)))) ++ ins.all_prefixes[ins.last_rex2_prefix] = 0; ++ + /* Check if the SEG prefix is used. */ + if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES + | PREFIX_FS | PREFIX_GS)) != 0 +@@ -9541,7 +9857,11 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) + if (name == NULL) + abort (); + prefix_length += strlen (name) + 1; +- i386_dis_printf (info, dis_style_mnemonic, "%s ", name); ++ if (ins.all_prefixes[i] == REX2_OPCODE) ++ i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name, ++ (unsigned int) ins.rex2_payload); ++ else ++ i386_dis_printf (info, dis_style_mnemonic, "%s ", name); + } + + /* Check maximum code length. */ +@@ -10077,6 +10397,16 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + int cond = 1; + unsigned int l = 0, len = 0; + char last[4]; ++ bool evex_printed = false; ++ ++ /* We don't want to add any prefix or suffix to (bad), so return early. */ ++ if (!strncmp (in_template, "(bad)", 5)) ++ { ++ oappend (ins, "(bad)"); ++ *ins->obufp = 0; ++ ins->mnemonicendp = ins->obufp; ++ return 0; ++ } + + for (p = in_template; *p; p++) + { +@@ -10090,6 +10420,12 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + switch (*p) + { + default: ++ if (ins->evex_type == evex_from_legacy && !ins->vex.nd ++ && !(ins->rex2 & 7) && !evex_printed) ++ { ++ oappend (ins, "{evex} "); ++ evex_printed = true; ++ } + *ins->obufp++ = *p; + break; + case '%': +@@ -10120,7 +10456,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + case 'A': + if (ins->intel_syntax) + break; +- if ((ins->need_modrm && ins->modrm.mod != 3) ++ if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd) + || (sizeflag & SUFFIX_ALWAYS)) + *ins->obufp++ = 'b'; + break; +@@ -10204,7 +10540,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + { + case 'X': + if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2 +- || !ins->vex.r ++ || (ins->rex2 & 7) + || (ins->modrm.mod == 3 && (ins->rex & REX_X)) + || !ins->vex.v || ins->vex.mask_register_specifier) + break; +@@ -10226,6 +10562,11 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + *ins->obufp++ = '}'; + *ins->obufp++ = ' '; + break; ++ case 'M': ++ if (ins->modrm.mod != 3 && !(ins->rex2 & 7)) ++ oappend (ins, "{evex} "); ++ evex_printed = true; ++ break; + default: + abort (); + } +@@ -10245,16 +10586,39 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); + break; + case 'F': +- if (ins->intel_syntax) ++ if (l == 0) ++ { ++ if (ins->intel_syntax) ++ break; ++ if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) ++ { ++ if (sizeflag & AFLAG) ++ *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; ++ else ++ *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w'; ++ ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); ++ } ++ } ++ else if (l == 1 && last[0] == 'C') + break; +- if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) ++ else if (l == 1 && last[0] == 'N') + { +- if (sizeflag & AFLAG) +- *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; +- else +- *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w'; +- ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); ++ if (ins->vex.nf) ++ { ++ oappend (ins, "{nf} "); ++ /* This bit needs to be cleared after it is consumed. */ ++ ins->vex.nf = false; ++ evex_printed = true; ++ } ++ else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7) ++ && ins->vex.v) ++ { ++ oappend (ins, "{evex} "); ++ evex_printed = true; ++ } + } ++ else ++ abort (); + break; + case 'G': + if (ins->intel_syntax || (ins->obufp[-1] != 's' +@@ -10311,7 +10675,16 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + *ins->obufp++ = 'd'; + break; + case 'L': +- abort (); ++ if (ins->intel_syntax) ++ break; ++ if (sizeflag & SUFFIX_ALWAYS) ++ { ++ if (ins->rex & REX_W) ++ *ins->obufp++ = 'q'; ++ else ++ *ins->obufp++ = 'l'; ++ } ++ break; + case 'M': + if (ins->intel_mnemonic != cond) + *ins->obufp++ = 'r'; +@@ -10346,6 +10719,19 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + case 'P': + if (l == 0) + { ++ if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W)) ++ { ++ /* For pushp and popp, p is printed and do not print {rex2} ++ for them. */ ++ *ins->obufp++ = 'p'; ++ ins->rex2 |= REX2_SPECIAL; ++ break; ++ } ++ ++ /* For "!P" print nothing else in Intel syntax. */ ++ if (!cond && ins->intel_syntax) ++ break; ++ + if ((ins->modrm.mod == 3 || !cond) + && !(sizeflag & SUFFIX_ALWAYS)) + break; +@@ -10390,7 +10776,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag) + if (ins->intel_syntax && !alt) + break; + USED_REX (REX_W); +- if ((ins->need_modrm && ins->modrm.mod != 3) ++ if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd) + || (sizeflag & SUFFIX_ALWAYS)) + { + if (ins->rex & REX_W) +@@ -10818,7 +11204,8 @@ print_displacement (instr_info *ins, bfd_signed_vma val) + static void + intel_operand_size (instr_info *ins, int bytemode, int sizeflag) + { +- if (ins->vex.b) ++ /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */ ++ if (ins->vex.b && ins->evex_type == evex_default) + { + if (!ins->vex.no_broadcast) + switch (bytemode) +@@ -11088,6 +11475,8 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, + USED_REX (rexmask); + if (ins->rex & rexmask) + reg += 8; ++ if (ins->rex2 & rexmask) ++ reg += 16; + + switch (bytemode) + { +@@ -11095,7 +11484,7 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, + case b_swap_mode: + if (reg & 4) + USED_REX (0); +- if (ins->rex) ++ if (ins->rex || ins->rex2) + names = att_names8rex; + else + names = att_names8; +@@ -11300,6 +11689,7 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, + /* Skip mod/rm byte. */ + MODRM_CHECK; + ins->codep++; ++ ins->has_skipped_modrm = true; + return true; + } + +@@ -11310,7 +11700,10 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) + int riprel = 0; + int shift; + +- if (ins->vex.evex) ++ add += (ins->rex2 & REX_B) ? 16 : 0; ++ ++ /* Handles EVEX other than APX EVEX-promoted instructions. */ ++ if (ins->vex.evex && ins->evex_type == evex_default) + { + + /* Zeroing-masking is invalid for memory destinations. Set the flag +@@ -11454,6 +11847,13 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) + abort (); + if (ins->vex.evex) + { ++ /* S/G EVEX insns require EVEX.X4 not to be set. */ ++ if (ins->rex2 & REX_X) ++ { ++ oappend (ins, "(bad)"); ++ return true; ++ } ++ + if (!ins->vex.v) + vindex += 16; + check_gather = ins->obufp == ins->op_out[1]; +@@ -11483,6 +11883,9 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) + } + break; + default: ++ if (ins->rex2 & REX_X) ++ vindex += 16; ++ + if (vindex != 4) + indexes = ins->address_mode == mode_64bit && !addr32flag + ? att_names64 : att_names32; +@@ -11653,7 +12056,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) + + if (ins->rex & REX_R) + modrm_reg += 8; +- if (!ins->vex.r) ++ if (ins->rex2 & REX_R) + modrm_reg += 16; + if (vindex == modrm_reg) + oappend (ins, "/(bad)"); +@@ -11735,7 +12138,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) + print_operand_value (ins, disp & 0xffff, dis_style_text); + } + } +- if (ins->vex.b) ++ if (ins->vex.b && ins->evex_type == evex_default) + { + ins->evex_used |= EVEX_b_used; + +@@ -11818,7 +12221,11 @@ OP_E (instr_info *ins, int bytemode, int sizeflag) + { + /* Skip mod/rm byte. */ + MODRM_CHECK; +- ins->codep++; ++ if (!ins->has_skipped_modrm) ++ { ++ ins->codep++; ++ ins->has_skipped_modrm = true; ++ } + + if (ins->modrm.mod == 3) + { +@@ -11855,10 +12262,7 @@ OP_indirE (instr_info *ins, int bytemode, int sizeflag) + static bool + OP_G (instr_info *ins, int bytemode, int sizeflag) + { +- if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit) +- oappend (ins, "(bad)"); +- else +- print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); ++ print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); + return true; + } + +@@ -11866,7 +12270,7 @@ static bool + OP_REG (instr_info *ins, int code, int sizeflag) + { + const char *s; +- int add; ++ int add = 0; + + switch (code) + { +@@ -11879,8 +12283,8 @@ OP_REG (instr_info *ins, int code, int sizeflag) + USED_REX (REX_B); + if (ins->rex & REX_B) + add = 8; +- else +- add = 0; ++ if (ins->rex2 & REX_B) ++ add += 16; + + switch (code) + { +@@ -12011,6 +12415,8 @@ OP_I (instr_info *ins, int bytemode, int sizeflag) + case const_1_mode: + if (ins->intel_syntax) + oappend (ins, "1"); ++ else ++ oappend (ins, "$1"); + return true; + default: + oappend (ins, INTERNAL_DISASSEMBLER_ERROR); +@@ -12487,7 +12893,7 @@ OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) + reg += 8; + if (ins->vex.evex) + { +- if (!ins->vex.r) ++ if (ins->rex2 & REX_R) + reg += 16; + } + +@@ -12592,6 +12998,8 @@ OP_EX (instr_info *ins, int bytemode, int sizeflag) + USED_REX (REX_B); + if (ins->rex & REX_B) + reg += 8; ++ if (ins->rex2 & REX_B) ++ reg += 16; + if (ins->vex.evex) + { + USED_REX (REX_X); +@@ -12623,9 +13031,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) + { + case d_mode: + case dq_mode: ++ case q_mode: + case mask_mode: + return OP_E (ins, bytemode, sizeflag); +- case q_mode: ++ case q_mm_mode: + return OP_EM (ins, x_mode, sizeflag); + case xmm_mode: + if (ins->vex.length <= 128) +@@ -13095,6 +13504,13 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) + if (!ins->need_vex) + return true; + ++ if (ins->evex_type == evex_from_legacy) ++ { ++ ins->evex_used |= EVEX_b_used; ++ if (!ins->vex.nd) ++ return true; ++ } ++ + reg = ins->vex.register_specifier; + ins->vex.register_specifier = 0; + if (ins->address_mode != mode_64bit) +@@ -13186,12 +13602,22 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) + names = att_names_xmm; + ins->evex_used |= EVEX_len_used; + break; ++ case v_mode: + case dq_mode: + if (ins->rex & REX_W) + names = att_names64; ++ else if (bytemode == v_mode ++ && !(sizeflag & DFLAG)) ++ names = att_names16; + else + names = att_names32; + break; ++ case b_mode: ++ names = att_names8rex; ++ break; ++ case q_mode: ++ names = att_names64; ++ break; + case mask_bd_mode: + case mask_mode: + if (reg > 0x7) +@@ -13491,7 +13917,7 @@ DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag) + /* Calc destination register number. */ + if (ins->rex & REX_R) + modrm_reg += 8; +- if (!ins->vex.r) ++ if (ins->rex2 & REX_R) + modrm_reg += 16; + + /* Calc src1 register number. */ +@@ -13576,3 +14002,58 @@ PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) + + return OP_M (ins, bytemode, sizeflag); + } ++ ++static bool ++PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag) ++{ ++ if (ins->modrm.mod != 3) ++ return true; ++ ++ unsigned int vvvv_reg = ins->vex.register_specifier ++ | (!ins->vex.v << 4); ++ unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0) ++ + (ins->rex2 & REX_B ? 16 : 0); ++ ++ /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */ ++ if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4 ++ || (!ins->modrm.reg ++ && vvvv_reg == rm_reg)) ++ { ++ oappend (ins, "(bad)"); ++ return true; ++ } ++ ++ return OP_VEX (ins, bytemode, sizeflag); ++} ++ ++static bool ++JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag) ++{ ++ if (ins->last_rex2_prefix >= 0) ++ { ++ uint64_t op; ++ ++ if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0 ++ || (ins->rex & REX_W) != 0x0) ++ { ++ oappend (ins, "(bad)"); ++ return true; ++ } ++ ++ if (bytemode == eAX_reg) ++ return true; ++ ++ if (!get64 (ins, &op)) ++ return false; ++ ++ ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs"); ++ ins->rex2 |= REX2_SPECIAL; ++ oappend_immediate (ins, op); ++ ++ return true; ++ } ++ ++ if (bytemode == eAX_reg) ++ return OP_IMREG (ins, bytemode, sizeflag); ++ return OP_OFF64 (ins, bytemode, sizeflag); ++} +diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c +--- a/opcodes/i386-gen.c ++++ b/opcodes/i386-gen.c +@@ -1,4 +1,4 @@ +-/* Copyright (C) 2007-2023 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2024 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + +@@ -63,7 +63,7 @@ static const dependency isa_dependencies[] = + { "NOCONA", + "GENERIC64|FISTTP|SSE3|MONITOR|CX16" }, + { "CORE", +- "P4|FISTTP|SSE3|MONITOR|CX16" }, ++ "P4|FISTTP|SSE3|MONITOR" }, + { "CORE2", + "NOCONA|SSSE3" }, + { "COREI7", +@@ -94,6 +94,8 @@ static const dependency isa_dependencies[] = + "ZNVER2|INVLPGB|TLBSYNC|VAES|VPCLMULQDQ|INVPCID|SNP|OSPKE" }, + { "ZNVER4", + "ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" }, ++ { "ZNVER5", ++ "ZNVER4|AVX_VNNI|MOVDIRI|MOVDIR64B|AVX512_VP2INTERSECT|PREFETCHI" }, + { "BTVER1", + "GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" }, + { "BTVER2", +@@ -166,6 +168,10 @@ static const dependency isa_dependencies[] = + "AVX2" }, + { "AVX_NE_CONVERT", + "AVX2" }, ++ { "CX16", ++ "64" }, ++ { "LKGS", ++ "64" }, + { "FRED", + "LKGS" }, + { "AVX512F", +@@ -240,13 +246,13 @@ static const dependency isa_dependencies[] = + { "SNP", + "SEV_ES" }, + { "RMPQUERY", +- "SNP" }, ++ "SNP|64" }, + { "TSX", + "RTM|HLE" }, + { "TSXLDTRK", + "RTM" }, + { "AMX_TILE", +- "XSAVE" }, ++ "XSAVE|64" }, + { "AMX_INT8", + "AMX_TILE" }, + { "AMX_BF16", +@@ -259,6 +265,20 @@ static const dependency isa_dependencies[] = + "SSE2" }, + { "WIDEKL", + "KL" }, ++ { "PBNDKB", ++ "64" }, ++ { "UINTR", ++ "64" }, ++ { "PREFETCHI", ++ "64" }, ++ { "CMPCCXADD", ++ "64" }, ++ { "MSRLIST", ++ "64" }, ++ { "USER_MSR", ++ "64" }, ++ { "APX_F", ++ "XSAVE|64" }, + }; + + /* This array is populated as process_i386_initializers() walks cpu_flags[]. */ +@@ -380,6 +400,8 @@ static bitfield cpu_flags[] = + BITFIELD (RAO_INT), + BITFIELD (FRED), + BITFIELD (LKGS), ++ BITFIELD (USER_MSR), ++ BITFIELD (APX_F), + BITFIELD (MWAITX), + BITFIELD (CLZERO), + BITFIELD (OSPKE), +@@ -463,12 +485,12 @@ static bitfield opcode_modifiers[] = + BITFIELD (StaticRounding), + BITFIELD (SAE), + BITFIELD (Disp8MemShift), +- BITFIELD (Vsz), + BITFIELD (Optimize), +- BITFIELD (ATTMnemonic), +- BITFIELD (ATTSyntax), +- BITFIELD (IntelSyntax), ++ BITFIELD (Dialect), + BITFIELD (ISA64), ++ BITFIELD (NoEgpr), ++ BITFIELD (NF), ++ BITFIELD (Rex2), + }; + + #define CLASS(n) #n, n +@@ -587,7 +609,7 @@ static void + process_copyright (FILE *fp) + { + fprintf (fp, "/* This file is automatically generated by i386-gen. Do not edit! */\n\ +-/* Copyright (C) 2007-2023 Free Software Foundation, Inc.\n\ ++/* Copyright (C) 2007-2024 Free Software Foundation, Inc.\n\ + \n\ + This file is part of the GNU opcodes library.\n\ + \n\ +@@ -771,8 +793,10 @@ add_isa_dependencies (bitfield *flags, const char *f, int value, + } + free (deps); + +- /* ISA extensions with dependencies need CPU_ANY_*_FLAGS emitted. */ +- if (reverse < ARRAY_SIZE (isa_reverse_deps[0])) ++ /* ISA extensions with dependencies need CPU_ANY_*_FLAGS emitted, ++ unless the sole dependency is the "64-bit mode only" one. */ ++ if (reverse < ARRAY_SIZE (isa_reverse_deps[0]) ++ && strcmp (isa_dependencies[i].deps, "64")) + isa_reverse_deps[reverse][reverse] = 1; + + is_avx = orig_is_avx; +@@ -787,15 +811,16 @@ add_isa_dependencies (bitfield *flags, const char *f, int value, + + static void + output_cpu_flags (FILE *table, bitfield *flags, unsigned int size, +- int macro, const char *comma, const char *indent, int lineno) ++ int mode, const char *comma, const char *indent, int lineno) + { + unsigned int i = 0, j = 0; + +- memset (&active_cpu_flags, 0, sizeof(active_cpu_flags)); ++ if (mode < 0) ++ memset (&active_cpu_flags, 0, sizeof(active_cpu_flags)); + + fprintf (table, "%s{ { ", indent); + +- if (!macro) ++ if (mode <= 0) + { + for (j = ~0u; i < CpuAttrEnums; i++) + { +@@ -806,7 +831,8 @@ output_cpu_flags (FILE *table, bitfield *flags, unsigned int size, + fail ("%s: %d: invalid combination of CPU identifiers\n", + filename, lineno); + j = i; +- active_cpu_flags.array[i / 32] |= 1U << (i % 32); ++ if (mode) ++ active_cpu_flags.array[i / 32] |= 1U << (i % 32); + } + + /* Write 0 to indicate "no associated flag". */ +@@ -824,16 +850,25 @@ output_cpu_flags (FILE *table, bitfield *flags, unsigned int size, + if (((j + 1) % 20) == 0) + { + /* We need \\ for macro. */ +- if (macro) ++ if (mode > 0) + fprintf (table, " \\\n %s", indent); + else + fprintf (table, "\n %s", indent); + } +- if (flags[i].value) ++ if (mode < 0 && flags[i].value) + active_cpu_flags.array[i / 32] |= 1U << (i % 32); + } + +- fprintf (table, "%d } }%s\n", flags[i].value, comma); ++#if defined(CpuAttrUnused) != defined(CpuUnused) ++ if (mode <= 0) ++# ifdef CpuUnused ++ fprintf (table, " } }%s\n", comma); ++# else ++ fprintf (table, "%d, 0 } }%s\n", flags[i].value, comma); ++# endif ++ else ++#endif ++ fprintf (table, "%d } }%s\n", flags[i].value, comma); + } + + static void +@@ -846,15 +881,17 @@ process_i386_cpu_flag (FILE *table, char *flag, + unsigned int i; + int value = 1; + bool is_isa = false; +- bitfield flags [ARRAY_SIZE (cpu_flags)]; ++ bitfield all [ARRAY_SIZE (cpu_flags)]; ++ bitfield any [ARRAY_SIZE (cpu_flags)]; + + /* Copy the default cpu flags. */ +- memcpy (flags, cpu_flags, sizeof (cpu_flags)); ++ memcpy (all, cpu_flags, sizeof (cpu_flags)); ++ memcpy (any, cpu_flags, sizeof (cpu_flags)); + + if (flag == NULL) + { + for (i = 0; i < ARRAY_SIZE (isa_reverse_deps[0]); ++i) +- flags[i].value = isa_reverse_deps[reverse][i]; ++ any[i].value = isa_reverse_deps[reverse][i]; + goto output; + } + +@@ -876,9 +913,9 @@ process_i386_cpu_flag (FILE *table, char *flag, + + /* First we turn on everything except for cpuno64 and - if + present - the padding field. */ +- for (i = 0; i < ARRAY_SIZE (flags); i++) +- if (flags[i].position < CpuNo64) +- flags[i].value = 1; ++ for (i = 0; i < ARRAY_SIZE (any); i++) ++ if (any[i].position < CpuNo64) ++ any[i].value = 1; + + /* Turn off selective bits. */ + value = 0; +@@ -886,10 +923,10 @@ process_i386_cpu_flag (FILE *table, char *flag, + + if (name != NULL && value != 0) + { +- for (i = 0; i < ARRAY_SIZE (flags); i++) +- if (strcasecmp (flags[i].name, name) == 0) ++ for (i = 0; i < ARRAY_SIZE (any); i++) ++ if (strcasecmp (any[i].name, name) == 0) + { +- add_isa_dependencies (flags, name, 1, reverse); ++ add_isa_dependencies (any, name, 1, reverse); + is_isa = true; + break; + } +@@ -897,18 +934,40 @@ process_i386_cpu_flag (FILE *table, char *flag, + + if (strcmp (flag, "0")) + { ++ bool combined = false; ++ + if (is_isa) + return; + + /* Turn on/off selective bits. */ + last = flag + strlen (flag); ++ if (name == NULL && strchr (flag, '&')) ++ { ++ for (; next < last && *next != '('; ) ++ { ++ str = next_field (next, '&', &next, last); ++ set_bitfield (str, all, value, ARRAY_SIZE (all), lineno); ++ } ++ if (*next == '(') ++ { ++ if (*--last != ')') ++ fail ("%s: %d: missing `)' in bitfield: %s\n", filename, ++ lineno, flag); ++ ++next; ++ *last = '\0'; ++ } ++ combined = true; ++ } + for (; next && next < last; ) + { + str = next_field (next, '|', &next, last); +- if (name == NULL) +- set_bitfield (str, flags, value, ARRAY_SIZE (flags), lineno); +- else +- add_isa_dependencies (flags, str, value, reverse); ++ if (name) ++ add_isa_dependencies (any, str, value, reverse); ++ else if (combined || next < last) ++ set_bitfield (str, any, value, ARRAY_SIZE (any), lineno); ++ else /* Singular specifiers go into "all". */ ++ set_bitfield (str, all, value, ARRAY_SIZE (all), lineno); ++ combined = true; + } + } + +@@ -918,6 +977,15 @@ process_i386_cpu_flag (FILE *table, char *flag, + size_t len = strlen (name); + char *upper = xmalloc (len + 1); + ++ /* Cpu64 is special: It specifies a mode dependency, not an ISA one. Zap ++ the flag from ISA initializer macros (and from CPU_ANY_64_FLAGS ++ itself we only care about tracking its dependents. Also don't emit the ++ (otherwise all zero) CPU_64_FLAGS. */ ++ if (flag != NULL && reverse == Cpu64) ++ return; ++ if (is_isa || flag == NULL) ++ any[Cpu64].value = 0; ++ + for (i = 0; i < len; ++i) + { + /* Don't emit #define-s for auxiliary entries. */ +@@ -930,8 +998,18 @@ process_i386_cpu_flag (FILE *table, char *flag, + flag != NULL ? "": "ANY_", upper); + free (upper); + } ++ else ++ { ++ /* Synthesize "64-bit mode only" dependencies from the dependencies we ++ have accumulated. */ ++ for (i = 0; i < ARRAY_SIZE (isa_reverse_deps[0]); ++i) ++ if (all[i].value && isa_reverse_deps[Cpu64][i]) ++ all[Cpu64].value = 1; ++ ++ output_cpu_flags(table, all, ARRAY_SIZE (all), -1, comma, indent, lineno); ++ } + +- output_cpu_flags (table, flags, ARRAY_SIZE (flags), name != NULL, ++ output_cpu_flags (table, any, ARRAY_SIZE (any), name != NULL, + comma, indent, lineno); + } + +@@ -1008,10 +1086,44 @@ get_element_size (char **opnd, int lineno) + return elem_size; + } + ++static bool ++rex2_disallowed (const unsigned long long opcode, unsigned int length, ++ unsigned int space, const char *cpu_flags) ++{ ++ /* Some opcodes encode a ModR/M-like byte directly in the opcode. */ ++ unsigned int base_opcode = opcode >> (8 * length - 8); ++ ++ /* All opcodes listed map0 0x4*, 0x7*, 0xa*, 0xe* and map1 0x3*, 0x8* ++ are reserved under REX2 and triggers #UD when prefixed with REX2 */ ++ if (space == 0) ++ switch (base_opcode >> 4) ++ { ++ case 0x4: ++ case 0x7: ++ case 0xA: ++ case 0xE: ++ return true; ++ default: ++ return false; ++ } ++ ++ if (space == SPACE_0F) ++ switch (base_opcode >> 4) ++ { ++ case 0x3: ++ case 0x8: ++ return true; ++ default: ++ return false; ++ } ++ ++ return false; ++} ++ + static void + process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, + unsigned int prefix, const char *extension_opcode, +- char **opnd, int lineno) ++ char **opnd, int lineno, bool rex2_disallowed) + { + char *str, *next, *last; + bitfield modifiers [ARRAY_SIZE (opcode_modifiers)]; +@@ -1021,8 +1133,10 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, + SPACE(0F), + SPACE(0F38), + SPACE(0F3A), ++ SPACE(EVEXMAP4), + SPACE(EVEXMAP5), + SPACE(EVEXMAP6), ++ SPACE(VEXMAP7), + SPACE(XOP08), + SPACE(XOP09), + SPACE(XOP0A), +@@ -1127,6 +1241,22 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, + fprintf (table, " SPACE_%s, %s,\n", + spaces[space], extension_opcode ? extension_opcode : "None"); + ++ /* Rather than evaluating multiple conditions at runtime to determine ++ whether an EVEX encoding is being dealt with, derive that information ++ right here. A missing EVex attribute means "dynamic". */ ++ if (!modifiers[EVex].value ++ && (modifiers[Disp8MemShift].value ++ || modifiers[Broadcast].value ++ || modifiers[Masking].value ++ || modifiers[SAE].value)) ++ modifiers[EVex].value = EVEXDYN; ++ ++ /* Vex, legacy map2 and map3 and rex2_disallowed do not support EGPR. ++ For templates supporting both Vex and EVex allowing EGPR. */ ++ if ((modifiers[Vex].value || space > SPACE_0F || rex2_disallowed) ++ && !modifiers[EVex].value) ++ modifiers[NoEgpr].value = 1; ++ + output_opcode_modifier (table, modifiers, ARRAY_SIZE (modifiers)); + } + +@@ -1351,7 +1481,9 @@ output_i386_opcode (FILE *table, const char *name, char *str, + free (ident); + + process_i386_opcode_modifier (table, opcode_modifier, space, prefix, +- extension_opcode, operand_types, lineno); ++ extension_opcode, operand_types, lineno, ++ rex2_disallowed (opcode, length, space, ++ cpu_flags)); + + process_i386_cpu_flag (table, cpu_flags, NULL, ",", " ", lineno, CpuMax); + +@@ -1406,10 +1538,10 @@ opcode_hash_eq (const void *p, const void *q) + return strcmp (name, entry->name) == 0; + } + +-static void ++static bool + parse_template (char *buf, int lineno) + { +- char sep, *end, *name; ++ char sep, *end, *ptr; + struct template *tmpl; + struct template_instance *last_inst = NULL; + +@@ -1436,8 +1568,16 @@ parse_template (char *buf, int lineno) + prev->next = tmpl->next; + else + templates = tmpl->next; +- return; ++ return true; + } ++ ++ /* Check whether this actually is a reference to an existing template: ++ If there's '>' ahead of ':', it can't be a new template definition ++ (and template undefs have are dealt with above). */ ++ ptr = strchr (buf, '>'); ++ if (ptr != NULL && ptr < end) ++ return false; ++ + *end++ = '\0'; + remove_trailing_whitespaces (buf); + +@@ -1512,6 +1652,8 @@ parse_template (char *buf, int lineno) + + tmpl->next = templates; + templates = tmpl; ++ ++ return true; + } + + static unsigned int +@@ -1768,10 +1910,12 @@ process_i386_opcodes (FILE *table) + /* Ignore comments. */ + case '\0': + continue; +- break; ++ + case '<': +- parse_template (p, lineno); +- continue; ++ if (parse_template (p, lineno)) ++ continue; ++ break; ++ + default: + if (!marker) + continue; +@@ -1808,23 +1952,26 @@ process_i386_opcodes (FILE *table) + + /* Generate opcode sets array. */ + fprintf (table, "\n/* i386 opcode sets table. */\n\n"); +- fprintf (table, "static const insn_template *const i386_op_sets[] =\n{\n"); +- fprintf (table, " i386_optab,\n"); ++ fprintf (table, "typedef unsigned short i386_op_off_t;\n"); ++ fprintf (table, "static const i386_op_off_t i386_op_sets[] =\n{\n "); + + for (nr = j = 0; j < i; j++) + { + struct opcode_entry *next = &opcode_array[j]->entry; + ++ if ((j + 1) % 8 != 0) ++ fprintf (table, "%5u,", nr); ++ else ++ fprintf (table, "%5u,\n ", nr); + do + { + ++nr; + next = next->next; + } + while (next); +- fprintf (table, " i386_optab + %u,\n", nr); + } + +- fprintf (table, "};\n"); ++ fprintf (table, "%5u\n};\n", nr); + + /* Emit mnemonics and associated #define-s. */ + qsort (opcode_array, i, sizeof (*opcode_array), mnemonic_cmp); +@@ -2140,6 +2287,8 @@ main (int argc, char **argv) + qsort (operand_types, ARRAY_SIZE (operand_types), + sizeof (operand_types [0]), compare); + ++ process_i386_initializers (); ++ + table = fopen ("i386-tbl.h", "w"); + if (table == NULL) + fail ("can't create i386-tbl.h, errno = %s\n", +@@ -2149,7 +2298,6 @@ main (int argc, char **argv) + + process_i386_opcodes (table); + process_i386_registers (table); +- process_i386_initializers (); + + fclose (table); + +diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h +--- a/opcodes/i386-init.h ++++ b/opcodes/i386-init.h +@@ -1,5 +1,5 @@ + /* This file is automatically generated by i386-gen. Do not edit! */ +-/* Copyright (C) 2007-2023 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2024 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + +@@ -26,7 +26,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_286_FLAGS \ + { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -36,7 +36,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_386_FLAGS \ + { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -46,7 +46,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_486_FLAGS \ + { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -56,7 +56,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_586_FLAGS \ + { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -65,8 +65,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_686_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ +@@ -75,8 +75,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CMOV_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -86,7 +86,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_FXSR_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -96,7 +96,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CLFLUSH_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -106,7 +106,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_NOP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -116,7 +116,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SYSCALL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -126,7 +126,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_8087_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -136,7 +136,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_687_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ +@@ -145,8 +145,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_FISTTP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ +@@ -155,8 +155,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +@@ -166,7 +166,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SSE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ +@@ -176,7 +176,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SSE2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +@@ -186,7 +186,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SSE3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -196,7 +196,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PADLOCK_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +@@ -206,7 +206,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SVME_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ +@@ -216,7 +216,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_VMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -226,7 +226,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -236,7 +236,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SSSE3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -246,7 +246,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SSE4A_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -256,7 +256,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_LZCNT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -266,7 +266,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_POPCNT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -276,7 +276,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MONITOR_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -286,7 +286,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SSE4_1_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -296,7 +296,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SSE4_2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -306,7 +306,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -315,8 +315,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX512CD_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -325,8 +325,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512ER_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -335,8 +335,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512PF_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -345,8 +345,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512DQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -355,8 +355,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512BW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -365,8 +365,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_IAMCU_FLAGS \ + { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -376,7 +376,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_XSAVE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -386,7 +386,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_XSAVEOPT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -396,7 +396,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +@@ -406,7 +406,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PCLMULQDQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +@@ -416,7 +416,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_FMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -425,8 +425,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_FMA4_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -435,8 +435,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_XOP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -445,8 +445,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_LWP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -456,7 +456,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_BMI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -466,7 +466,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_TBM_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -476,7 +476,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MOVBE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -486,7 +486,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CX16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -496,7 +496,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_LAHF_SAHF_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -506,7 +506,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_EPT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -516,7 +516,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RDTSCP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -526,7 +526,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_FSGSBASE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -536,7 +536,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RDRND_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -546,7 +546,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_F16C_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -555,8 +555,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_BMI2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -566,7 +566,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RTM_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -576,7 +576,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_INVPCID_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -586,7 +586,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_VMFUNC_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -596,7 +596,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MPX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -606,7 +606,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RDSEED_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -616,7 +616,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ADX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -626,7 +626,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PRFCHW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -636,7 +636,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SMAP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -646,7 +646,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SHA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +@@ -656,7 +656,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SHA512_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -665,8 +665,8 @@ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SM3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -675,8 +675,8 @@ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SM4_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -685,8 +685,8 @@ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CLFLUSHOPT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -696,7 +696,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_XSAVES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -706,7 +706,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_XSAVEC_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -716,7 +716,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PREFETCHWT1_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -726,7 +726,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SE1_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -736,7 +736,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CLWB_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -746,7 +746,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX512IFMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -755,8 +755,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512VBMI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -765,8 +765,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_4FMAPS_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -775,8 +775,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_4VNNIW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -785,8 +785,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_VPOPCNTDQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -795,8 +795,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_VBMI2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -805,8 +805,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_VNNI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -815,8 +815,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_BITALG_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -825,8 +825,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_BF16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -835,8 +835,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512_VP2INTERSECT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -845,8 +845,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_TDX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -856,7 +856,7 @@ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX_VNNI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -865,8 +865,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX512_FP16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -875,8 +875,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_PREFETCHI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -886,7 +886,7 @@ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX_IFMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -895,8 +895,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX_VNNI_INT8_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -905,8 +905,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX_VNNI_INT16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -915,8 +915,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CMPCCXADD_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -926,7 +926,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_WRMSRNS_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -936,7 +936,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MSRLIST_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -946,7 +946,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX_NE_CONVERT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -955,8 +955,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RAO_INT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -966,7 +966,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_FRED_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -976,7 +976,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_LKGS_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -986,9 +986,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + +-#define CPU_MWAITX_FLAGS \ ++#define CPU_USER_MSR_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -996,9 +996,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + +-#define CPU_CLZERO_FLAGS \ ++#define CPU_MWAITX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1006,17 +1006,27 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } ++ ++#define CPU_CLZERO_FLAGS \ ++ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_OSPKE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RDPID_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1024,9 +1034,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PTWRITE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1034,9 +1044,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_IBT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1044,9 +1054,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SHSTK_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1054,9 +1064,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AMX_INT8_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1064,9 +1074,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AMX_BF16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1074,9 +1084,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AMX_FP16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1084,9 +1094,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AMX_COMPLEX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1094,9 +1104,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AMX_TILE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1104,9 +1114,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_GFNI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +@@ -1114,9 +1124,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_VAES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1124,9 +1134,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_VPCLMULQDQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1134,9 +1144,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_WBNOINVD_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1144,9 +1154,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PCONFIG_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1154,9 +1164,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PBNDKB_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1164,9 +1174,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_WAITPKG_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1174,9 +1184,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_UINTR_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1184,9 +1194,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CLDEMOTE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1194,9 +1204,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MOVDIRI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1204,9 +1214,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MOVDIR64B_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1214,9 +1224,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ENQCMD_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1225,8 +1235,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SERIALIZE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1235,8 +1245,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RDPRU_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1245,8 +1255,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_MCOMMIT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1255,8 +1265,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SEV_ES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ +@@ -1265,8 +1275,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_TSXLDTRK_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1275,8 +1285,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_KL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +@@ -1285,8 +1295,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_WIDEKL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +@@ -1295,8 +1305,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_HRESET_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1305,8 +1315,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_INVLPGB_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1315,8 +1325,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_TLBSYNC_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1325,8 +1335,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_SNP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ +@@ -1335,8 +1345,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_RMPQUERY_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ +@@ -1345,8 +1355,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_287_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1355,8 +1365,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_387_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1365,8 +1375,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_3DNOW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +@@ -1375,8 +1385,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_3DNOWA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +@@ -1385,18 +1395,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +- 0, 0, 0, 0 } } +- +-#define CPU_64_FLAGS \ +- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1405,8 +1405,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_HLE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1415,8 +1415,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 1, 0, 0, 0, 0, 0 } } + + #define CPU_AVX512F_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1425,8 +1425,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 0, 0, 0, 0 } } + + #define CPU_AVX512VL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1435,8 +1435,18 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 1, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 1, 0, 0, 0 } } ++ ++#define CPU_APX_F_FLAGS \ ++ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 1, 0, 0 } } + + #define CPU_UNKNOWN_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ +@@ -1446,7 +1456,7 @@ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ +- 1, 1, 0, 0 } } ++ 1, 1, 1, 1, 0, 0 } } + + #define CPU_GENERIC32_FLAGS \ + { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1456,7 +1466,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_GENERIC64_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, \ +@@ -1465,8 +1475,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_NONE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1476,7 +1486,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_PENTIUMPRO_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1485,8 +1495,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_P2_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, \ +@@ -1495,8 +1505,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_P3_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, \ +@@ -1505,8 +1515,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_P4_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, \ +@@ -1515,8 +1525,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_NOCONA_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ +@@ -1525,18 +1535,18 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CORE_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_CORE2_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ +@@ -1545,8 +1555,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_COREI7_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ +@@ -1555,8 +1565,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_K6_FLAGS \ + { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +@@ -1565,8 +1575,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_K6_2_FLAGS \ + { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +@@ -1575,8 +1585,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ATHLON_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, \ +@@ -1585,8 +1595,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_K8_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, \ +@@ -1595,8 +1605,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AMDFAM10_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ +@@ -1605,8 +1615,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_BDVER1_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ +@@ -1615,8 +1625,8 @@ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_BDVER2_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ +@@ -1625,8 +1635,8 @@ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_BDVER3_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ +@@ -1635,58 +1645,68 @@ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_BDVER4_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ZNVER1_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ + 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, \ + 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ZNVER2_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ + 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, \ + 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \ +- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ ++ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ZNVER3_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ + 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, \ + 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ +- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ ++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ZNVER4_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, \ + 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, \ + 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, \ +- 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ +- 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, \ +- 1, 1, 0, 0 } } ++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ ++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, \ ++ 0, 1, 1, 0, 0, 0 } } ++ ++#define CPU_ZNVER5_FLAGS \ ++ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ ++ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, \ ++ 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, \ ++ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, \ ++ 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ ++ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, \ ++ 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, \ ++ 0, 1, 1, 0, 0, 0 } } + + #define CPU_BTVER1_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ +@@ -1695,8 +1715,8 @@ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_BTVER2_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ +@@ -1705,8 +1725,8 @@ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ABM_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1716,7 +1736,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_AVX10_1_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1725,8 +1745,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1, \ + 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 1, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 1, 0, 0, 0 } } + + #define CPU_TSX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1735,8 +1755,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 1, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_FXSR_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1744,9 +1764,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_8087_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ +@@ -1755,8 +1775,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_687_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ +@@ -1766,7 +1786,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_FISTTP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ +@@ -1776,7 +1796,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_MMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +@@ -1785,8 +1805,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SSE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ +@@ -1794,9 +1814,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SSE2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ +@@ -1804,9 +1824,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SSE3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ +@@ -1816,7 +1836,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SVME_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ +@@ -1825,8 +1845,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_VMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1836,7 +1856,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SSSE3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1846,7 +1866,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SSE4A_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1856,7 +1876,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SSE4_1_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1866,7 +1886,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SSE4_2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1876,7 +1896,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1884,9 +1904,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 1, 1, 0, 0 } } ++ 0, 1, 1, 0, 0, 0 } } + + #define CPU_ANY_AVX512CD_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1896,7 +1916,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512ER_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1906,7 +1926,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512PF_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1916,7 +1936,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512DQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1926,7 +1946,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512BW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1936,7 +1956,7 @@ + 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_IAMCU_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1946,17 +1966,17 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_XSAVE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, \ + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ +- 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, \ +- 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 1, 0, 0 } } ++ 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ ++ 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 1, 1, 0, 0 } } + + #define CPU_ANY_XSAVEOPT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1966,7 +1986,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1974,9 +1994,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_PCLMULQDQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1984,9 +2004,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_FMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -1996,7 +2016,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_FMA4_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2006,7 +2026,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_XOP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2016,7 +2036,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_LWP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2026,7 +2046,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_EPT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2036,7 +2056,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_F16C_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2046,7 +2066,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_RTM_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2055,8 +2075,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_VMFUNC_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2066,7 +2086,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_MPX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2076,7 +2096,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SHA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2086,7 +2106,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SHA512_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2096,7 +2116,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SM3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2106,7 +2126,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SM4_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2116,7 +2136,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_XSAVES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2126,7 +2146,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_XSAVEC_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2136,7 +2156,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512IFMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2146,7 +2166,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512VBMI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2156,7 +2176,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_4FMAPS_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2166,7 +2186,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_4VNNIW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2176,7 +2196,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_VPOPCNTDQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2186,7 +2206,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_VBMI2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2196,7 +2216,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_VNNI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2206,7 +2226,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_BITALG_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2216,7 +2236,7 @@ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_BF16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2226,7 +2246,7 @@ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_VP2INTERSECT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2236,7 +2256,7 @@ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX_VNNI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2246,7 +2266,7 @@ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX512_FP16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2256,7 +2276,7 @@ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX_IFMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2266,7 +2286,7 @@ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX_VNNI_INT8_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2276,7 +2296,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX_VNNI_INT16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2286,7 +2306,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AVX_NE_CONVERT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2296,7 +2316,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_FRED_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2306,7 +2326,7 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_LKGS_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2316,17 +2336,17 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_OSPKE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AMX_INT8_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2334,9 +2354,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AMX_BF16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2344,9 +2364,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AMX_FP16_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2354,9 +2374,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AMX_COMPLEX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2364,9 +2384,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_AMX_TILE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2374,9 +2394,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_GFNI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2384,9 +2404,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_VAES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2394,9 +2414,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_VPCLMULQDQ_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2404,9 +2424,9 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SEV_ES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2415,8 +2435,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_TSXLDTRK_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2425,8 +2445,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_KL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2435,8 +2455,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_WIDEKL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2445,8 +2465,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_SNP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2455,8 +2475,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_RMPQUERY_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2465,8 +2485,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_287_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ +@@ -2475,8 +2495,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_387_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ +@@ -2485,8 +2505,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_3DNOW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2495,8 +2515,8 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } + + #define CPU_ANY_3DNOWA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2505,8 +2525,18 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ +- 0, 0, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0 } } ++ ++#define CPU_ANY_64_FLAGS \ ++ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 1, 0, 0 } } + + #define CPU_ANY_AVX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2514,9 +2544,9 @@ + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ +- 1, 1, 0, 0 } } ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ ++ 0, 1, 1, 0, 0, 0 } } + + #define CPU_ANY_AVX512F_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2526,7 +2556,7 @@ + 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 1, 1, 0, 0 } } ++ 0, 1, 1, 0, 0, 0 } } + + #define CPU_ANY_AVX512VL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +@@ -2536,5 +2566,15 @@ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ +- 0, 1, 0, 0 } } ++ 0, 0, 1, 0, 0, 0 } } ++ ++#define CPU_ANY_APX_F_FLAGS \ ++ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 1, 0, 0 } } + +diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl +--- a/opcodes/i386-opc.tbl ++++ b/opcodes/i386-opc.tbl +@@ -1,5 +1,5 @@ + // i386 opcode table. +-// Copyright (C) 2007-2023 Free Software Foundation, Inc. ++// Copyright (C) 2007-2024 Free Software Foundation, Inc. + // + // This file is part of the GNU opcodes library. + // +@@ -85,6 +85,11 @@ + #define RegKludge OperandConstraint=REG_KLUDGE + #define SwapSources OperandConstraint=SWAP_SOURCES + #define Ugh OperandConstraint=UGH ++#define ImplicitStackOp OperandConstraint=IMPLICIT_STACK_OP ++ ++#define ATTSyntax Dialect=ATT_SYNTAX ++#define ATTMnemonic Dialect=ATT_MNEMONIC ++#define IntelSyntax Dialect=INTEL_SYNTAX + + #define IgnoreSize MnemonicSize=IGNORESIZE + #define DefaultSize MnemonicSize=DEFAULTSIZE +@@ -109,9 +114,12 @@ + #define SpaceXOP09 OpcodeSpace=SPACE_XOP09 + #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A + ++#define EVexMap4 OpcodeSpace=SPACE_EVEXMAP4|EVex128 + #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 + #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 + ++#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 ++ + #define VexW0 VexW=VEXW0 + #define VexW1 VexW=VEXW1 + #define VexWIG VexW=VEXWIG +@@ -133,12 +141,22 @@ + + #define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL + +-#define Vsz256 Vsz=VSZ256 +-#define Vsz512 Vsz=VSZ512 ++#define DstVVVV VexVVVV=VexVVVV_DST ++ ++// The template supports VEX format for cpuid and EVEX format for cpuid & APX_F. ++// While therefore we really mean cpuid|(cpuid&APX_F) here, this can't be ++// expressed in the generated templates. It's equivalent to just cpuid|APX_F ++// anyway, but that is not what we want (as APX_F alone isn't a sufficient ++// prereq for such insns). Instead the assembler will massage the CPU specifier ++// to the equivalent of either cpuid&(cpuid) or cpuid&(APX_F) (or something ++// substantially similar), depending on what encoding was requested. ++#define APX_F(cpuid) cpuid&(cpuid|APX_F) + + // The EVEX purpose of StaticRounding appears only together with SAE. Re-use + // the bit to mark commutative VEX encodings where swapping the source + // operands may allow to switch from 3-byte to 2-byte VEX encoding. ++// And re-use the bit to mark some NDD insns that swapping the source operands ++// may allow to switch from EVEX encoding to REX2 encoding. + #define C StaticRounding + + #define FP 387|287|8087 +@@ -156,6 +174,8 @@ + #define i287 287 + #define i387 387 + #define i687 687 ++// Note: Don't add this one to any templates already specifying a 64-bit-mode- ++// only ISA extension: i386-gen takes care of adding such dependencies. + #define x64 64 + + ### MARKER ### +@@ -164,11 +184,11 @@ + mov, 0xa0, No64, D|W|CheckOperandSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } + mov, 0xa0, x64, D|W|CheckOperandSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } + movabs, 0xa0, x64, D|W|CheckOperandSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +-mov, 0x88, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++mov, 0x88, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + // In the 64bit mode the short form mov immediate is redefined to have + // 64bit value. + mov, 0xb0, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } +-mov, 0xc6/0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++mov, 0xc6/0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + mov, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 } + movabs, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 } + // The segment register moves accept WordReg so that a segment register +@@ -181,14 +201,18 @@ mov, 0x8c, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { SReg, Word|U + mov, 0x8e, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } + // Move to/from control debug registers. In the 16 or 32bit modes + // they are 32bit. In the 64bit mode they are 64bit. +-mov, 0xf20, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 } ++mov, 0xf20, i386&No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 } + mov, 0xf20, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 } +-mov, 0xf21, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 } ++mov, 0xf21, i386&No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 } + mov, 0xf21, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 } +-mov, 0xf24, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 } ++mov, 0xf24, i386&No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 } + + // Move after swapping the bytes + movbe, 0x0f38f0, Movbe, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++movbe, 0x60, Movbe&APX_F, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++// This needs to live here for easy EVEX -> REX2 conversion, which wants to ++// restart with the next sequential template. ++bswap, 0xfc8, i486, No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64 } + + // Move with sign extend. + movsb, 0xfbe, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +@@ -201,37 +225,39 @@ movsxd, 0x63, x64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 } + movsxd, 0x63, x64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 } + + // Move with zero extend. +-movzb, 0xfb6, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +-movzw, 0xfb7, i386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } ++movzb, 0xfb6, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++movzw, 0xfb7, i386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } + // The 64-bit variant is not particularly useful since the zero extend + // 32->64 is implicit, but we can encode them. + movzx, 0xfb6, i386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + + // Push instructions. +-push, 0x50, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +-push, 0xff/6, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } +-push, 0x6a, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S } +-push, 0x68, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } +-push, 0x6, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } ++push, 0x50, No64, ImplicitStackOp|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } ++push, 0xff/6, No64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Unspecified|BaseIndex } ++push, 0x6a, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S } ++push, 0x68, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } ++push, 0x6, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } + // In 64bit mode, the operand size is implicitly 64bit. +-push, 0x50, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +-push, 0xff/6, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } +-push, 0x6a, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } +-push, 0x68, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } +-push, 0xfa0, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } ++push, 0x50, x64, ImplicitStackOp|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } ++pushp, 0x50, APX_F, ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 } ++push, 0xff/6, x64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex } ++push, 0x6a, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } ++push, 0x68, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } ++push, 0xfa0, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } + +-pusha, 0x60, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} ++pusha, 0x60, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} + + // Pop instructions. +-pop, 0x58, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +-pop, 0x8f/0, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } +-pop, 0x7, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } ++pop, 0x58, No64, ImplicitStackOp|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } ++pop, 0x8f/0, No64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Unspecified|BaseIndex } ++pop, 0x7, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } + // In 64bit mode, the operand size is implicitly 64bit. +-pop, 0x58, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +-pop, 0x8f/0, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } +-pop, 0xfa1, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } ++pop, 0x58, x64, ImplicitStackOp|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } ++popp, 0x58, APX_F, ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 } ++pop, 0x8f/0, x64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex } ++pop, 0xfa1, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } + +-popa, 0x61, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} ++popa, 0x61, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} + + // Exchange instructions. + // xchg commutes: we allow both operand orders. +@@ -273,70 +299,67 @@ lahf, 0x9f, No64, NoSuf, {} + lahf, 0x9f, LAHF_SAHF, NoSuf, {} + sahf, 0x9e, No64, NoSuf, {} + sahf, 0x9e, LAHF_SAHF, NoSuf, {} +-pushf, 0x9c, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +-pushf, 0x9c, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} +-popf, 0x9d, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +-popf, 0x9d, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} ++pushf, 0x9c, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} ++pushf, 0x9c, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} ++popf, 0x9d, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} ++popf, 0x9d, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} + stc, 0xf9, 0, NoSuf, {} + std, 0xfd, 0, NoSuf, {} + sti, 0xfb, 0, NoSuf, {} + + // Arithmetic. +-add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +-inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +-sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++ ++ ++, << 3, APX_F, D||W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4||, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ++, << 3, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock||, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, << 3, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0x83/, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++, 0x83/, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0x83/, 0, Modrm|No_bSuf|No_sSuf|EVexMap4|, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0x04 | ( << 3), 0, W|No_sSuf|, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } ++, 0x80/, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ++, 0x80/, 0, W|Modrm|No_sSuf|HLEPrefixLock|, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0x80/, APX_F, W|Modrm|EVexMap4|No_sSuf|, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++ ++ + +-dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +-dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-sbb, 0x1c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++// clr with 1 operand is really xor with 2 operands. ++clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } ++clr, 0x30, APX_F, W|Modrm|No_sSuf|RegKludge|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64 } + +-cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } ++cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } + cmp, 0x3c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + + test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + +-and, 0x20, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++ + +-or, 0x8, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++, 0x40 | ( << 3), No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } ++, 0xfe/, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} ++, 0xfe/, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xfe/, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + +-xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++ + +-// clr with 1 operand is really xor with 2 operands. +-clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } ++ + +-adc, 0x10, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-adc, 0x83/2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-adc, 0x14, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +-adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++, 0xf6/, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ++, 0xf6/, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xf6/, APX_F, W|Modrm|No_sSuf|EVexMap4|, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + +-neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++ + + aaa, 0x37, No64, NoSuf, {} + aas, 0x3f, No64, NoSuf, {} +@@ -367,81 +390,82 @@ cqto, 0x99, x64, Size64|NoSuf, {} + // expanding 64-bit multiplies, and *cannot* be selected to accomplish + // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) + // These multiplies can only be selected with single operand forms. +-mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } +-imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +-imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++ ++ ++, 0xf6/, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xf6/, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++imul, 0xaf, APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } ++imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++imul, 0xaf, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++imul, 0x6b, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++imul, 0x69, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + // imul with 2 operands mimics imul with 3 by putting the register in + // both i.rm.reg & i.rm.regmem fields. RegKludge enables this + // transformation. + imul, 0x6b, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } ++imul, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64 } + imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } +- +-div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-div, 0xf6/6, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +-idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-idiv, 0xf6/7, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +- +-rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rcr, 0xc0/3, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sal, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-shl, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-shr, 0xc0/5, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sar, 0xc0/7, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +- +-shld, 0xfa4, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +- +-shrd, 0xfac, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +-shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } ++imul, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } ++ ++ ++ ++ ++ ++
, 0xf6/, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++
, 0xf6/, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++
, 0xf6/, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } ++
, 0xf6/, APX_F, W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } ++ ++
++ ++ ++ ++, 0xd0/, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ++, 0xd0/, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xd0/, APX_F, W|Modrm|No_sSuf|EVexMap4|, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xc0/, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|, { , Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ++, 0xc0/, i186, W|Modrm|No_sSuf, { , Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xc0/, APX_F, W|Modrm|No_sSuf|EVexMap4|, { , Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xd2/, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ++, 0xd2/, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xd2/, APX_F, W|Modrm|No_sSuf|EVexMap4|, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++, 0xd0/, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++ ++ ++ ++ ++ ++shd, 0x24 | , APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++shd, 0x0fa4 | , i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++shd, 0x24 | , APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++shd, 0xa5 | , APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++shd, 0x0fa5 | , i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++shd, 0xa5 | , APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++shd, 0x0fa5 | , i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++ ++ + + // Control transfer instructions. +-call, 0xe8, No64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } +-call, 0xe8, x64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } +-call, 0xe8, x64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 } +-call, 0xff/2, No64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } +-call, 0xff/2, x64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } +-call, 0xff/2, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } ++call, 0xe8, No64, JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } ++call, 0xe8, x64, Amd64|JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } ++call, 0xe8, x64, Intel64|JumpDword|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 } ++call, 0xff/2, No64, Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } ++call, 0xff/2, x64, Amd64|Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } ++call, 0xff/2, x64, Intel64|Modrm|JumpAbsolute|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } + // Intel Syntax remaining call instances. +-call, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +-call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|NoSuf, { Dword|Fword|BaseIndex } +-call, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } ++call, 0x9a, No64, JumpInterSegment|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } ++call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|NoSuf, { Dword|Fword|BaseIndex } ++call, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|ImplicitStackOp|NoSuf, { Dword|Fword|Tbyte|BaseIndex } + lcall, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } + lcall, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } + lcall, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } +@@ -459,22 +483,22 @@ ljmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 + ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } + ljmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } + +-ret, 0xc3, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} +-ret, 0xc2, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } +-ret, 0xc3, x64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} +-ret, 0xc2, x64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } +-ret, 0xc3, x64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} +-ret, 0xc2, x64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } ++ret, 0xc3, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} ++ret, 0xc2, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } ++ret, 0xc3, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} ++ret, 0xc2, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } ++ret, 0xc3, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} ++ret, 0xc2, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } + lret, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} + lret, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } + // Intel Syntax. + retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} + retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } + +-enter, 0xc8, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 } +-enter, 0xc8, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 } +-leave, 0xc9, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +-leave, 0xc9, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} ++enter, 0xc8, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 } ++enter, 0xc8, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 } ++leave, 0xc9, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} ++leave, 0xc9, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} + + +@@ -503,7 +527,7 @@ loopne, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } + loopne, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } + + // Set byte on flag instructions. +-set, 0xf9/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex } ++set, 0xf9/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Unspecified|BaseIndex } + + // String manipulation. + cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk, {} +@@ -540,58 +564,58 @@ xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {} + xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex } + + // Bit manipulation. +-bsf, 0xfbc, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +-bsr, 0xfbd, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +-bt, 0xfa3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } ++bsf, 0xfbc, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++bsr, 0xfbd, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++bt, 0xfa3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } + bt, 0xfba/4, i386, Modrm|No_bSuf|No_sSuf|Optimize, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } +-btc, 0xfbb, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } ++btc, 0xfbb, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } + btc, 0xfba/7, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } +-btr, 0xfb3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } ++btr, 0xfb3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } + btr, 0xfba/6, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } +-bts, 0xfab, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } ++bts, 0xfab, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex } + bts, 0xfba/5, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } + + // Interrupts & op. sys insns. + // See gas/config/tc-i386.c for conversion of 'int $3' into the special + // int 3 insn. +-int, 0xcd, 0, NoSuf, { Imm8 } +-int1, 0xf1, 0, NoSuf, {} +-int3, 0xcc, 0, NoSuf, {} +-into, 0xce, No64, NoSuf, {} +-iret, 0xcf, 0, DefaultSize|No_bSuf|No_sSuf, {} ++int, 0xcd, 0, ImplicitStackOp|NoSuf, { Imm8 } ++int1, 0xf1, 0, ImplicitStackOp|NoSuf, {} ++int3, 0xcc, 0, ImplicitStackOp|NoSuf, {} ++into, 0xce, No64, ImplicitStackOp|NoSuf, {} ++iret, 0xcf, 0, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf, {} + // i386sl, i486sl, later 486, and Pentium. + rsm, 0xfaa, i386, NoSuf, {} + +-bound, 0x62, i186|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } ++bound, 0x62, i186&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } + + hlt, 0xf4, 0, NoSuf, {} + +-nop, 0xf1f/0, Nop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } ++nop, 0xf1f/0, Nop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex } + + // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in + // 32bit mode and "xchg %rax,%rax" in 64bit mode. + nop, 0x90, 0, NoSuf|RepPrefixOk, {} + + // Protection control. +-arpl, 0x63, i286|No64, RegMem|CheckOperandSize|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Reg16|Reg32 } +-arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Word|Unspecified|BaseIndex } ++arpl, 0x63, i286&No64, RegMem|CheckOperandSize|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Reg16|Reg32 } ++arpl, 0x63, i286&No64, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Word|Unspecified|BaseIndex } + lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } + lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +-lgdt, 0xf01/2, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } ++lgdt, 0xf01/2, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } + lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +-lidt, 0xf01/3, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } ++lidt, 0xf01/3, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } + lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } + lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } + lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +-lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } ++lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Unspecified|BaseIndex } + lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } + lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } + ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } + +-sgdt, 0xf01/0, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } ++sgdt, 0xf01/0, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } + sgdt, 0xf01/0, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +-sidt, 0xf01/1, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } ++sidt, 0xf01/1, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } + sidt, 0xf01/1, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } + sldt, 0xf00/0, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } + sldt, 0xf00/0, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +@@ -700,14 +724,13 @@ faddp, 0xdec1, FP, NoSuf, {} + fsub, 0xd8/4, FP, Modrm|NoSuf, { FloatReg } + fsub, 0xd8/4, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } + // alias for fsubp +-fsub, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +-fsub, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic, {} ++fsub, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic, {} + fsub, 0xd8/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } + fisub, 0xde/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +-fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +-fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +-fsubp, 0xdee1, FP, NoSuf|ATTMnemonic|ATTSyntax, {} ++fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } ++fsubp, 0xde/4, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } ++fsubp, 0xdee1, FP, NoSuf|ATTMnemonic, {} + fsubp, 0xde/5, FP, Modrm|NoSuf, { FloatAcc, FloatReg } + fsubp, 0xde/5, FP, Modrm|NoSuf, { FloatReg } + fsubp, 0xdee9, FP, NoSuf, {} +@@ -716,14 +739,13 @@ fsubp, 0xdee9, FP, NoSuf, {} + fsubr, 0xd8/5, FP, Modrm|NoSuf, { FloatReg } + fsubr, 0xd8/5, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } + // alias for fsubrp +-fsubr, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +-fsubr, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic, {} ++fsubr, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic, {} + fsubr, 0xd8/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } + fisubr, 0xde/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +-fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +-fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +-fsubrp, 0xdee9, FP, NoSuf|ATTMnemonic|ATTSyntax, {} ++fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } ++fsubrp, 0xde/5, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } ++fsubrp, 0xdee9, FP, NoSuf|ATTMnemonic, {} + fsubrp, 0xde/4, FP, Modrm|NoSuf, { FloatAcc, FloatReg } + fsubrp, 0xde/4, FP, Modrm|NoSuf, { FloatReg } + fsubrp, 0xdee1, FP, NoSuf, {} +@@ -745,14 +767,13 @@ fmulp, 0xdec9, FP, NoSuf, {} + fdiv, 0xd8/6, FP, Modrm|NoSuf, { FloatReg } + fdiv, 0xd8/6, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } + // alias for fdivp +-fdiv, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +-fdiv, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic, {} ++fdiv, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic, {} + fdiv, 0xd8/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } + fidiv, 0xde/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +-fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +-fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +-fdivp, 0xdef1, FP, NoSuf|ATTMnemonic|ATTSyntax, {} ++fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } ++fdivp, 0xde/6, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } ++fdivp, 0xdef1, FP, NoSuf|ATTMnemonic, {} + fdivp, 0xde/7, FP, Modrm|NoSuf, { FloatAcc, FloatReg } + fdivp, 0xde/7, FP, Modrm|NoSuf, { FloatReg } + fdivp, 0xdef9, FP, NoSuf, {} +@@ -761,14 +782,13 @@ fdivp, 0xdef9, FP, NoSuf, {} + fdivr, 0xd8/7, FP, Modrm|NoSuf, { FloatReg } + fdivr, 0xd8/7, FP, D|Modrm|NoSuf, { FloatReg, FloatAcc } + // alias for fdivrp +-fdivr, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +-fdivr, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic, {} ++fdivr, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic, {} + fdivr, 0xd8/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } + fidivr, 0xde/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +-fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +-fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +-fdivrp, 0xdef9, FP, NoSuf|ATTMnemonic|ATTSyntax, {} ++fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic, { FloatAcc, FloatReg } ++fdivrp, 0xde/7, FP, Modrm|NoSuf|ATTMnemonic, { FloatReg } ++fdivrp, 0xdef9, FP, NoSuf|ATTMnemonic, {} + fdivrp, 0xde/6, FP, Modrm|NoSuf, { FloatAcc, FloatReg } + fdivrp, 0xde/6, FP, Modrm|NoSuf, { FloatReg } + fdivrp, 0xdef1, FP, NoSuf, {} +@@ -831,14 +851,14 @@ fwait, 0x9b, FP, NoSuf, {} + + // Opcode prefixes; we allow them as separate insns too. + +-addr16, 0x67, i386|No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} ++addr16, 0x67, i386&No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} + addr32, 0x67, i386, Size32|IgnoreSize|NoSuf|IsPrefix, {} +-aword, 0x67, i386|No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} ++aword, 0x67, i386&No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} + adword, 0x67, i386, Size32|IgnoreSize|NoSuf|IsPrefix, {} + data16, 0x66, i386, Size16|IgnoreSize|NoSuf|IsPrefix, {} +-data32, 0x66, i386|No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} ++data32, 0x66, i386&No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} + word, 0x66, i386, Size16|IgnoreSize|NoSuf|IsPrefix, {} +-dword, 0x66, i386|No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} ++dword, 0x66, i386&No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} + lock, 0xf0, 0, NoSuf|IsPrefix, {} + wait, 0x9b, 0, NoSuf|IsPrefix, {} + cs, 0x2e, 0, NoSuf|IsPrefix, {} +@@ -888,18 +908,18 @@ rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {} + + // Pseudo prefixes (base_opcode == PSEUDO_PREFIX) + +- ++ rex:REX:x64, rex2:REX2:APX_F, nf:NF:APX_F, + ++ nooptimize:NoOptimize:0> + + {}, PSEUDO_PREFIX/Prefix_, , NoSuf|IsPrefix, {} + +-// 486 extensions. ++// 486 extensions (BSWAP moved elsewhere). + +-bswap, 0xfc8, i486, No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64 } +-xadd, 0xfc0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +-cmpxchg, 0xfb0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ++xadd, 0xfc0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ++cmpxchg, 0xfb0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } + invd, 0xf08, i486, NoSuf, {} + wbinvd, 0xf09, i486, NoSuf, {} + invlpg, 0xf01/7, i486, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +@@ -915,13 +935,13 @@ cmpxchg8b, 0xfc7/1, i586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefi + + // Pentium II/Pentium Pro extensions. + sysenter, 0xf34, x64, Intel64Only|NoSuf, {} +-sysenter, 0xf34, i686|No64, NoSuf, {} ++sysenter, 0xf34, i686&No64, NoSuf, {} + sysexit, 0xf35, x64, Intel64Only|No_bSuf|No_wSuf|No_sSuf, {} +-sysexit, 0xf35, i686|No64, NoSuf, {} ++sysexit, 0xf35, i686&No64, NoSuf, {} + fxsave, 0xfae/0, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +-fxsave64, 0xfae/0, FXSR|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } ++fxsave64, 0xfae/0, FXSR&x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } + fxrstor, 0xfae/1, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +-fxrstor64, 0xfae/1, FXSR|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } ++fxrstor64, 0xfae/1, FXSR&x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } + rdpmc, 0xf33, i686, NoSuf, {} + // official undefined instr. + ud2, 0xf0b, i186, NoSuf, {} +@@ -934,7 +954,8 @@ ud2b, 0xfb9, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|U + // 3rd official undefined instr (older CPUs don't take a ModR/M byte) + ud0, 0xfff, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +-cmov, 0xf4, CMOV, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++cmov, 0x4, CMOV&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } ++cmov, 0xf4, CMOV, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + + fcmovb, 0xda/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } + fcmovnae, 0xda/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } +@@ -992,9 +1013,9 @@ pause, 0xf390, i186, NoSuf, {} + b:0:VexW0:Byte:AVX512DQ:66:AVX512VBMI, + + w:1:VexW1:Word:AVX512F::AVX512BW> + +- ++ + + emms, 0xf77, MMX, NoSuf, {} + // These really shouldn't allow for Reg64 (movq is the right mnemonic for +@@ -1002,21 +1023,21 @@ emms, 0xf77, MMX, NoSuf, {} + // spec). AMD's spec, having been in existence for much longer, failed to + // recognize that and specified movd for 32- and 64-bit operations. + movd, 0x666e, AVX, D|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } +-movd, 0x666e, AVX|x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } ++movd, 0x666e, AVX&x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } + movd, 0x660f6e, SSE2, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +-movd, 0x660f6e, SSE2|x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } ++movd, 0x660f6e, SSE2&x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } + // The MMX templates have to remain after at least the SSE2AVX ones. + movd, 0xf6e, MMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX } +-movd, 0xf6e, MMX|x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } +-movq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +-movq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +-movq, 0x666e, AVX|x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } ++movd, 0xf6e, MMX&x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } ++movq, 0xf37e, AVX, Load|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } ++movq, 0x66d6, AVX, Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } ++movq, 0x666e, AVX&x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } + movq, 0xf30f7e, SSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } + movq, 0x660fd6, SSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } +-movq, 0x660f6e, SSE2|x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } ++movq, 0x660f6e, SSE2&x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } + // The MMX templates have to remain after at least the SSE2AVX ones. + movq, 0xf6f, MMX, D|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } +-movq, 0xf6e, MMX|x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } ++movq, 0xf6e, MMX&x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } + packssdw, 0x0f6b, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } + packsswb, 0x0f63, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } + packuswb, 0x0f67, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +@@ -1083,11 +1104,11 @@ cmpss, 0xf30fc2, , Modrm|||NoSuf, { Imm8, Dwor + comiss, 0x0f2f, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } + cvtpi2ps, 0xf2a, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } + cvtps2pi, 0xf2d, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } +-cvtsi2ss, 0xf30f2a, |No64, Modrm|||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +-cvtsi2ss, 0xf32a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-cvtsi2ss, 0xf32a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-cvtsi2ss, 0xf30f2a, SSE|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-cvtsi2ss, 0xf30f2a, SSE|x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++cvtsi2ss, 0xf30f2a, &No64, Modrm|||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } ++cvtsi2ss, 0xf32a, AVX&x64, Modrm|Vex=3|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } ++cvtsi2ss, 0xf32a, AVX&x64, Modrm|Vex=3|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } ++cvtsi2ss, 0xf30f2a, SSE&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } ++cvtsi2ss, 0xf30f2a, SSE&x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } + cvtss2si, 0xf32d, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } + cvtss2si, 0xf30f2d, SSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } + cvttps2pi, 0xf2c, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } +@@ -1178,11 +1199,11 @@ comisd, 0x660f2f, , Modrm||NoSuf, { Qword|Unspecified + cvtpi2pd, 0x660f2a, SSE2, Modrm|NoSuf, { RegMMX, RegXMM } + cvtpi2pd, 0xf3e6, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } + cvtpi2pd, 0x660f2a, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +-cvtsi2sd, 0xf20f2a, |No64, Modrm|IgnoreSize|||No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +-cvtsi2sd, 0xf22a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-cvtsi2sd, 0xf22a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-cvtsi2sd, 0xf20f2a, SSE2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-cvtsi2sd, 0xf20f2a, SSE2|x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++cvtsi2sd, 0xf20f2a, &No64, Modrm|IgnoreSize|||No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } ++cvtsi2sd, 0xf22a, AVX&x64, Modrm|Vex=3|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } ++cvtsi2sd, 0xf22a, AVX&x64, Modrm|Vex=3|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } ++cvtsi2sd, 0xf20f2a, SSE2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } ++cvtsi2sd, 0xf20f2a, SSE2&x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM } + divpd, 0x660f5e, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } + divsd, 0xf20f5e, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } + maxpd, 0x660f5f, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +@@ -1271,7 +1292,7 @@ fisttpll, 0xdd/1, FISTTP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } + + // CMPXCHG16B instruction. + +-cmpxchg16b, 0xfc7/1, CX16|x64, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } ++cmpxchg16b, 0xfc7/1, CX16, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } + + // MONITOR instructions. + +@@ -1281,7 +1302,7 @@ monitor, 0xf01c8, MONITOR, NoSuf, {} + // all modes. + monitor, 0xf01c8, MONITOR, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } + // The 64-bit form exists only for compatibility with older gas. +-monitor, 0xf01c8, MONITOR|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } ++monitor, 0xf01c8, MONITOR&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } + mwait, 0xf01c9, MONITOR, NoSuf, {} + // mwait is very special. AX and CX are always 32 bits. + // The 64-bit form exists only for compatibility with older gas. +@@ -1295,10 +1316,10 @@ vmlaunch, 0xf01c2, VMX, NoSuf, {} + vmresume, 0xf01c3, VMX, NoSuf, {} + vmptrld, 0xfc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } + vmptrst, 0xfc7/7, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +-vmread, 0xf78, VMX|No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32, Reg32|Unspecified|BaseIndex } +-vmread, 0xf78, VMX|x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex } +-vmwrite, 0xf79, VMX|No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32 } +-vmwrite, 0xf79, VMX|x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } ++vmread, 0xf78, VMX&No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32, Reg32|Unspecified|BaseIndex } ++vmread, 0xf78, VMX&x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64, Reg64|Unspecified|BaseIndex } ++vmwrite, 0xf79, VMX&No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32 } ++vmwrite, 0xf79, VMX&x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64|Unspecified|BaseIndex, Reg64 } + vmxoff, 0xf01c4, VMX, NoSuf, {} + vmxon, 0xf30fc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } + +@@ -1312,15 +1333,18 @@ getsec, 0xf37, SMX, NoSuf, {} + + // EPT instructions. + +-invept, 0x660f3880, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +-invept, 0x660f3880, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +-invvpid, 0x660f3881, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +-invvpid, 0x660f3881, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } ++invept, 0x660f3880, EPT&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } ++invept, 0x660f3880, EPT&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } ++invept, 0xf3f0, EPT&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } ++invvpid, 0x660f3881, EPT&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } ++invvpid, 0x660f3881, EPT&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } ++invvpid, 0xf3f1, EPT&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } + + // INVPCID instruction + +-invpcid, 0x660f3882, INVPCID|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +-invpcid, 0x660f3882, INVPCID|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } ++invpcid, 0x660f3882, INVPCID&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } ++invpcid, 0x660f3882, INVPCID&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } ++invpcid, 0xf3f2, INVPCID&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } + + // SSSE3 instructions. + +@@ -1355,10 +1379,10 @@ blendvp, 0x664a | , AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf| + blendvp, 0x660f3814 | , SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } + blendvp, 0x660f3814 | , SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } + dpp, 0x660f3a40 | , , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } +-extractps, 0x6617, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +-extractps, 0x6617, AVX|x64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } +-extractps, 0x660f3a17, SSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +-extractps, 0x660f3a17, SSE4_1|x64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } ++extractps, 0x6617, AVX, Modrm|Vex128|Space0F3A|VexW0|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } ++extractps, 0x6617, AVX&x64, RegMem|Vex128|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } ++extractps, 0x660f3a17, SSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } ++extractps, 0x660f3a17, SSE4_1&x64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } + insertps, 0x660f3a21, , Modrm|||NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } + movntdqa, 0x660f382a, , Modrm||NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } + mpsadbw, 0x660f3a42, , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } +@@ -1372,14 +1396,14 @@ pcmpeqq, 0x660f3829, , Modrm|||NoSuf|O + pextr, 0x660f3a14 | , , RegMem||NoSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } + pextr, 0x660f3a14 | , , Modrm||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } + pextrd, 0x660f3a16, , Modrm||NoSuf|IgnoreSize, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } +-pextrq, 0x6616, AVX|x64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } +-pextrq, 0x660f3a16, SSE4_1|x64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } ++pextrq, 0x6616, AVX&x64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } ++pextrq, 0x660f3a16, SSE4_1&x64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } + phminposuw, 0x660f3841, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } + pinsrb, 0x660f3a20, , Modrm|||NoSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } + pinsrb, 0x660f3a20, , Modrm|||NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM } + pinsrd, 0x660f3a22, , Modrm|||NoSuf|IgnoreSize, { Imm8, Reg32|Unspecified|BaseIndex, RegXMM } +-pinsrq, 0x6622, AVX|x64, Modrm|Vex|Space0F3A|VexVVVV|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } +-pinsrq, 0x660f3a22, SSE4_1|x64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } ++pinsrq, 0x6622, AVX&x64, Modrm|Vex|Space0F3A|VexVVVV|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } ++pinsrq, 0x660f3a22, SSE4_1&x64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } + pmaxsb, 0x660f383c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } + pmaxsd, 0x660f383d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } + pmaxud, 0x660f383f, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +@@ -1411,33 +1435,36 @@ rounds, 0x660f3a0a | , , Modrm|| + + pcmpgtq, 0x660f3837, , Modrm|||NoSuf|Optimize, { RegXMM|Unspecified|BaseIndex, RegXMM } +-pcmpestri, 0x660f3a61, |No64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +-pcmpestri, 0x6661, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +-pcmpestri, 0x660f3a61, SSE4_2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +-pcmpestrm, 0x660f3a60, |No64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +-pcmpestrm, 0x6660, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +-pcmpestrm, 0x660f3a60, SSE4_2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } ++pcmpestri, 0x660f3a61, &No64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } ++pcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } ++pcmpestri, 0x660f3a61, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } ++pcmpestrm, 0x660f3a60, &No64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } ++pcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } ++pcmpestrm, 0x660f3a60, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } + pcmpistri, 0x660f3a63, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } + pcmpistrm, 0x660f3a62, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } + crc32, 0xf20f38f0, SSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } +-crc32, 0xf20f38f0, SSE4_2|x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } ++crc32, 0xf20f38f0, SSE4_2&x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } ++crc32, 0xf0, APX_F, W|Modrm|No_sSuf|No_qSuf|EVexMap4, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } ++crc32, 0xf0, APX_F, W|Modrm|No_wSuf|No_lSuf|No_sSuf|EVexMap4, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } + + // xsave/xrstor New Instructions. + +-xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +-xsave64, 0xfae/4, Xsave|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +-xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +-xrstor64, 0xfae/5, Xsave|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } ++xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex } ++xsave64, 0xfae/4, Xsave&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } ++xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex } ++xrstor64, 0xfae/5, Xsave&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } + xgetbv, 0xf01d0, Xsave, NoSuf, {} + xsetbv, 0xf01d1, Xsave, NoSuf, {} + + // xsaveopt +-xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +-xsaveopt64, 0xfae/6, Xsaveopt|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } ++ ++xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex } ++xsaveopt64, 0xfae/6, Xsaveopt&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } + + // AES instructions. + +- ++ + + aesdec, 0x660f38de, AES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } + aesdeclast, 0x660f38df, AES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +@@ -1448,7 +1475,7 @@ aeskeygenassist, 0x660f3adf, AES, Modrm||NoSuf, { Imm8, + + // PCLMULQDQ + +- ++ + + pclmulqdq, 0x660f3a44, PCLMULQDQ, Modrm||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } + pclmullqlqdq, 0x660f3a44/0x00, PCLMULQDQ, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +@@ -1458,7 +1485,7 @@ pclmulhqhqdq, 0x660f3a44/0x11, PCLMULQDQ, Modrm| ++ + + gf2p8affineqb, 0x660f3ace, GFNI, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } + gf2p8affineinvqb, 0x660f3acf, GFNI, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +@@ -1477,6 +1504,9 @@ gf2p8mulb, 0x660f38cf, GFNI, Modrm||NoSuf, { RegXMM|Uns + true_us:1f:C> + + // is used for VEX instructions with x/y suffixes. ++// NOTE: The order of the "unnamed" ($-prefixed) entries here needs to remain ++// in sync with , for match_template()'s EVEX-to-VEX lowering to ++// continue to work. + , 0x55, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSiz + vandp, 0x54, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vblendp, 0x660c | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vblendvp, 0x664a | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +-vbroadcastf128, 0x661a, AVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } ++vbroadcastf128, 0x661a, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } ++// vbroadcastf32x4 in disguise (see vround{p,s}{s,d} comment) ++vbroadcastf128, 0x661a, APX_F&AVX512VL, Modrm|EVex256|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } + vbroadcastsd, 0x6619, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } + vbroadcastss, 0x6618, AVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } + vcmpp, 0xc2/0x, AVX, Modrm||Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1519,14 +1551,18 @@ vdivp, 0x5e, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize + vdivs, 0x5e, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } + vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } + vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +-vextractf128, 0x6619, AVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } +-vextractps, 0x6617, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +-vextractps, 0x6617, AVX|AVX512F|x64, RegMem|Vex128|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } ++vextractf128, 0x6619, AVX, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } ++// vextractf32x4 in disguise (see vround{p,s}{s,d} comment) ++vextractf128, 0x6619, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex } ++vextractps, 0x6617, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } ++vextractps, 0x6617, x64&(AVX|AVX512F), RegMem|Vex128|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } + vhaddpd, 0x667c, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vhaddps, 0xf27c, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vhsubpd, 0x667d, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vhsubps, 0xf27d, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vinsertf128, 0x6618, AVX, Modrm|Vex256|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } ++// vinsertf32x4 in disguise (see vround{p,s}{s,d} comment) ++vinsertf128, 0x6618, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|NoSuf, { Imm8, Xmmword|Unspecified|BaseIndex, RegYMM, RegYMM } + vinsertps, 0x6621, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } + vlddqu, 0xf2f0, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } + vldmxcsr, 0xae/2, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } +@@ -1544,7 +1580,7 @@ vmovap, 0x28, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSu + // support assembler for AMD64, we accept 64bit operand on vmovd so + // that we can use one template for both SSE and AVX instructions. + vmovd, 0x666e, AVX|AVX512F, D|Modrm|Vex128|EVex128|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +-vmovd, 0x667e, AVX|x64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } ++vmovd, 0x667e, AVX&x64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } + vmovddup, 0xf212, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } + vmovddup, 0xf212, AVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } + vmovdqa, 0x666f, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1561,7 +1597,7 @@ vmovntdqa, 0x662a, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckOperandSize|NoSuf, + vmovntp, 0x2b, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } + vmovq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } + vmovq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +-vmovq, 0x666e, AVX|AVX512F|x64, D|Modrm|Vex128|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } ++vmovq, 0x666e, x64&(AVX|AVX512F), D|Modrm|Vex128|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } + vmovs, 0x10, AVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { |Unspecified|BaseIndex, RegXMM } + vmovs, 0x10, AVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } + vmovshdup, 0xf316, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1591,10 +1627,10 @@ vpblendw, 0x660e, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize| + vpcmpeq, 0x6674 | , AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpcmpeqd, 0x6676, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpcmpeqq, 0x6629, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +-vpcmpestri, 0x6661, AVX|No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +-vpcmpestri, 0x6661, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +-vpcmpestrm, 0x6660, AVX|No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +-vpcmpestrm, 0x6660, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } ++vpcmpestri, 0x6661, AVX&No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } ++vpcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } ++vpcmpestrm, 0x6660, AVX&No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } ++vpcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } + vpcmpgt, 0x6664 | , AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpcmpgtd, 0x6666, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1605,7 +1641,7 @@ vpermilps, 0x660c, AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|VexW + vpermilps, 0x6604, AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F3A|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vpermilpd, 0x660d, AVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpermilpd, 0x6605, AVX, Modrm|Vex|Space0F3A|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +-vpextr, 0x6616, AVX|, Modrm|Vex|Space0F3A||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } ++vpextr, 0x6616, AVX&, Modrm|Vex|Space0F3A||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } + vpextrw, 0x66c5, AVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 } + vpextr, 0x6614 | , AVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } + vpextr, 0x6614 | , AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } +@@ -1618,7 +1654,7 @@ vphsubsw, 0x6607, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize| + vphsubw, 0x6605, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpinsrb, 0x6620, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } + vpinsrb, 0x6620, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } +-vpinsr, 0x6622, AVX|, Modrm|Vex|Space0F3A|VexVVVV||NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } ++vpinsr, 0x6622, AVX&, Modrm|Vex|Space0F3A|VexVVVV||NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } + vpinsrw, 0x66c4, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } + vpinsrw, 0x66c4, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } + vpmaddubsw, 0x6604, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1636,18 +1672,18 @@ vpminub, 0x66da, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|N + vpminud, 0x663b, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpminuw, 0x663a, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpmovmskb, 0x66d7, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } +-vpmovsxbd, 0x6621, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +-vpmovsxbq, 0x6622, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } ++vpmovsxbd, 0x6621, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } ++vpmovsxbq, 0x6622, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } + vpmovsxbw, 0x6620, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } + vpmovsxdq, 0x6625, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +-vpmovsxwd, 0x6623, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +-vpmovsxwq, 0x6624, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +-vpmovzxbd, 0x6631, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +-vpmovzxbq, 0x6632, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } ++vpmovsxwd, 0x6623, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++vpmovsxwq, 0x6624, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } ++vpmovzxbd, 0x6631, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } ++vpmovzxbq, 0x6632, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } + vpmovzxbw, 0x6630, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } + vpmovzxdq, 0x6635, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +-vpmovzxwd, 0x6633, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +-vpmovzxwq, 0x6634, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } ++vpmovzxwd, 0x6633, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++vpmovzxwq, 0x6634, AVX|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } + vpmuldq, 0x6628, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpmulhrsw, 0x660b, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } + vpmulhuw, 0x66e4, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1695,6 +1731,10 @@ vrcpps, 0x53, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecifie + vrcpss, 0xf353, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } + vroundp, 0x6608 | , AVX, Modrm|Vex|Space0F3A|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } + vrounds, 0x660a | , AVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++// These are really clones of VRNDSCALE{P,S}{S,D}, with broadcast, masking, SAE, ++// 512-bit operand size, and register sources dropped. ++vroundp, 0x6608 | , APX_F&AVX512VL, Modrm|Space0F3A||Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } ++vrounds, 0x660a | , APX_F&AVX512F, Modrm|EVexLIG|Space0F3A|VexVVVV||Disp8MemShift|NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } + vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } + vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } + vshufp, 0xc6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1714,22 +1754,24 @@ vzeroupper, 0x77, AVX, Vex|Space0F|VexWIG|NoSuf, {} + + // 256bit integer AVX2 instructions. + +-vpmovsxbd, 0x6621, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +-vpmovsxbq, 0x6622, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++vpmovsxbd, 0x6621, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } ++vpmovsxbq, 0x6622, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + vpmovsxbw, 0x6620, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } + vpmovsxdq, 0x6625, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +-vpmovsxwd, 0x6623, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +-vpmovsxwq, 0x6624, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +-vpmovzxbd, 0x6631, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +-vpmovzxbq, 0x6632, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++vpmovsxwd, 0x6623, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } ++vpmovsxwq, 0x6624, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } ++vpmovzxbd, 0x6631, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } ++vpmovzxbq, 0x6632, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + vpmovzxbw, 0x6630, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } + vpmovzxdq, 0x6635, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +-vpmovzxwd, 0x6633, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +-vpmovzxwq, 0x6634, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } ++vpmovzxwd, 0x6633, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } ++vpmovzxwq, 0x6634, AVX2|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } + + // New AVX2 instructions. + +-vbroadcasti128, 0x665A, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } ++vbroadcasti128, 0x665A, AVX2, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } ++// vbroadcasti32x4 in disguise (see vround{p,s}{s,d} comment) ++vbroadcasti128, 0x665a, APX_F&AVX512VL, Modrm|EVex256|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } + vbroadcastsd, 0x6619, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } + vbroadcastss, 0x6618, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vpblendd, 0x6602, AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +@@ -1741,8 +1783,12 @@ vpermd, 0x6636, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|VexVVVV|Vex + vpermpd, 0x6601, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } + vpermps, 0x6616, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } + vpermq, 0x6600, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +-vextracti128, 0x6639, AVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } ++vextracti128, 0x6639, AVX2, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } ++// vextracti32x4 in disguise (see vround{p,s}{s,d} comment) ++vextracti128, 0x6639, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex } + vinserti128, 0x6638, AVX2, Modrm|Vex256|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } ++// vinserti32x4 in disguise (see vround{p,s}{s,d} comment) ++vinserti128, 0x6638, APX_F&AVX512VL, Modrm|EVex256|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|NoSuf, { Imm8, Xmmword|Unspecified|BaseIndex, RegYMM, RegYMM } + vpmaskmov, 0x668e, AVX2, Modrm|Vex|Space0F38|VexVVVV||CheckOperandSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } + vpmaskmov, 0x668c, AVX2, Modrm|Vex|Space0F38|VexVVVV||CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } + vpsllv, 0x6647, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +@@ -1765,26 +1811,26 @@ vpgatherqq, 0x6691, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW1|SwapSources|NoSuf + + // AES + AVX + +-vaesdec, 0x66de, AVX|AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vaesdeclast, 0x66df, AVX|AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vaesenc, 0x66dc, AVX|AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vaesenclast, 0x66dd, AVX|AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vaesimc, 0x66db, AVX|AES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } +-vaeskeygenassist, 0x66df, AVX|AES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } ++vaesdec, 0x66de, AVX&AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vaesdeclast, 0x66df, AVX&AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vaesenc, 0x66dc, AVX&AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vaesenclast, 0x66dd, AVX&AES, Modrm|Vex|Space0F38|VexVVVV|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vaesimc, 0x66db, AVX&AES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } ++vaeskeygenassist, 0x66df, AVX&AES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } + + // PCLMULQDQ + AVX + +-vpclmulqdq, 0x6644, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vpclmullqlqdq, 0x6644/0x00, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vpclmullqhqdq, 0x6644/0x10, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +-vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vpclmulqdq, 0x6644, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vpclmullqlqdq, 0x6644/0x00, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vpclmulhqlqdq, 0x6644/0x01, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vpclmullqhqdq, 0x6644/0x10, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } ++vpclmulhqhqdq, 0x6644/0x11, AVX&PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } + + // GFNI + AVX + +-vgf2p8affineinvqb, 0x66cf, AVX|GFNI, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +-vgf2p8affineqb, 0x66ce, AVX|GFNI, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +-vgf2p8mulb, 0x66cf, GFNI|AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vgf2p8affineinvqb, 0x66cf, AVX&GFNI, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } ++vgf2p8affineqb, 0x66ce, AVX&GFNI, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } ++vgf2p8mulb, 0x66cf, GFNI&(AVX|AVX512F), Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + + // FSGSBASE, RDRND and F16C + +@@ -1803,8 +1849,8 @@ vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Uns + + + + + vfmaddp, 0x6688 | 0x, , Modrm||Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +@@ -1831,14 +1877,14 @@ xtest, 0xf01d6, HLE|RTM, NoSuf, {} + + // BMI2 instructions. + +-bzhi, 0xf5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-mulx, 0xf2f6, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +-pdep, 0xf2f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +-pext, 0xf3f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +-rorx, 0xf2f0, BMI2, Modrm|CheckOperandSize|Vex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +-sarx, 0xf3f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-shlx, 0x66f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-shrx, 0xf2f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++bzhi, 0xf5, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++mulx, 0xf2f6, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } ++pdep, 0xf2f5, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } ++pext, 0xf3f5, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } ++rorx, 0xf2f0, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++sarx, 0xf3f7, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++shlx, 0x66f7, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++shrx, 0xf2f7, APX_F(BMI2), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } + + // FMA4 instructions + +@@ -1908,12 +1954,13 @@ lwpins, 0x12/0, LWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV|Vex, { Imm32|Imm32S, Reg32|U + + // BMI instructions + +-andn, 0xf2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +-bextr, 0xf7, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-blsi, 0xf3/3, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-blsmsk, 0xf3/2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-blsr, 0xf3/1, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++andn, 0xf2, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } ++bextr, 0xf7, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++blsi, 0xf3/3, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++blsmsk, 0xf3/2, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++blsr, 0xf3/1, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++tzcnt, 0xf4, BMI&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + + // TBM instructions + +@@ -1990,10 +2037,12 @@ insertq, 0xf20f79, SSE4a, Modrm|NoSuf, { RegXMM, RegXMM } + insertq, 0xf20f78, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } + + // LZCNT instruction +-lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++lzcnt, 0xf5, LZCNT&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + + // POPCNT instruction +-popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++popcnt, 0x88, POPCNT&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + + // VIA PadLock extensions. + xstore-rng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} +@@ -2016,8 +2065,11 @@ xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {} + xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} + + // Multy-precision Add Carry, rdseed instructions. +-adcx, 0x660f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +-adox, 0xf30f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++ ++adx, 0x66, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } ++adx, 0x0f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++adx, 0x66, ADX&APX_F, Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } ++ + rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } + + // SMAP instructions. +@@ -2030,12 +2082,12 @@ bnd, 0xf2, MPX, NoSuf|IsPrefix, {} + // MPX instructions. + bndmk, 0xf30f1b, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } + bndmov, 0x660f1a, MPX, D|Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } +-bndcl, 0xf30f1a, MPX|No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +-bndcl, 0xf30f1a, MPX|x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +-bndcu, 0xf20f1a, MPX|No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +-bndcu, 0xf20f1a, MPX|x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +-bndcn, 0xf20f1b, MPX|No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +-bndcn, 0xf20f1b, MPX|x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } ++bndcl, 0xf30f1a, MPX&No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } ++bndcl, 0xf30f1a, MPX&x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } ++bndcu, 0xf20f1a, MPX&No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } ++bndcu, 0xf20f1a, MPX&x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } ++bndcn, 0xf20f1b, MPX&No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } ++bndcn, 0xf20f1b, MPX&x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } + bndstx, 0x0f1b, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { RegBND, BaseIndex } + bndldx, 0x0f1a, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } + +@@ -2073,26 +2125,29 @@ vsm4rnds4, 0xf2da, SM4, Modrm|Space0F38|Vex|VexVVVV|VexW0|CheckOperandSize|NoSuf + + // VAES + +-vaesdec, 0x66de, VAES|AVX|AVX512F, Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vaesdeclast, 0x66df, VAES|AVX|AVX512F, Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vaesenc, 0x66dc, VAES|AVX|AVX512F, Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vaesenclast, 0x66dd, VAES|AVX|AVX512F, Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vaesdec, 0x66de, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vaesdeclast, 0x66df, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vaesenc, 0x66dc, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vaesenclast, 0x66dd, VAES&(AVX|AVX512F), Modrm|Vex|EVexDYN|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + + // VAES instructions end + + // VPCLMULQDQ instructions + +-vpclmulqdq, 0x6644, VPCLMULQDQ|AVX|AVX512F, Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vpclmullqlqdq, 0x6644/0x00, VPCLMULQDQ|AVX|AVX512F, Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vpclmulhqlqdq, 0x6644/0x01, VPCLMULQDQ|AVX|AVX512F, Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vpclmullqhqdq, 0x6644/0x10, VPCLMULQDQ|AVX|AVX512F, Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ|AVX|AVX512F, Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vpclmulqdq, 0x6644, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vpclmullqlqdq, 0x6644/0x00, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vpclmulhqlqdq, 0x6644/0x01, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vpclmullqhqdq, 0x6644/0x10, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDYN|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + + // VPCLMULQDQ instructions end + + // AVX512F instructions. + + // is used for EVEX instructions with x/y suffixes. ++// NOTE: The order of the "unnamed" ($-prefixed) entries here needs to remain ++// in sync with , for match_template()'s EVEX-to-VEX lowering to ++// continue to work. + , 0x45, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { R + kxnor, 0x46, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } + kxor, 0x47, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } + +-kmov, 0x90, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +-kmov, 0x91, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } +-kmov, 0x92, , D|Modrm|Vex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } ++kmov, 0x90, APX_F(), Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } ++kmov, 0x91, APX_F(), Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } ++kmov, 0x92, APX_F(), D|Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } + + knot, 0x44, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } + kortest, 0x98, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } +@@ -2188,11 +2243,11 @@ vcvtudq2pd, 0xF37A, AVX512F, Modrm|EVex=1|Masking|Space0F|VexW=1|Broadcast|Disp8 + vcvtdq2ps, 0x5B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vcvtps2udq, 0x79, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +-vcvtpd2dq, 0xf2e6, AVX512F|, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } ++vcvtpd2dq, 0xf2e6, AVX512F&, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } + +-vcvtpd2ps, 0x665a, AVX512F|, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } ++vcvtpd2ps, 0x665a, AVX512F&, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } + +-vcvtpd2udq, 0x79, AVX512F|, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } ++vcvtpd2udq, 0x79, AVX512F&, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } + + vcvtph2ps, 0x6613, AVX512F, Modrm|EVex512|Masking|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } + +@@ -2223,8 +2278,8 @@ vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf| + + vcvtss2sd, 0xF35A, AVX512F, Modrm|EVexLIG|Masking|Space0F|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } + +-vcvttpd2dq, 0x66e6, AVX512F|, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +-vcvttpd2udq, 0x78, AVX512F|, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } ++vcvttpd2dq, 0x66e6, AVX512F&, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } ++vcvttpd2udq, 0x78, AVX512F&, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } + + vcvttps2dq, 0xF35B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vcvttps2udq, 0x78, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +@@ -2272,8 +2327,8 @@ vmovntdqa, 0x662A, AVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckOperandSize + vgetexpp, 0x6642, , Modrm|Masking|||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vgetexps, 0x6643, , Modrm|EVexLIG|Masking||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } + +-vinsertf32x4, 0x6618, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +-vinserti32x4, 0x6638, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } ++vinsertf32x4, 0x6618, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } ++vinserti32x4, 0x6638, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } + + vinsertf64x4, 0x661A, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexVVVV|VexW1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } + vinserti64x4, 0x663A, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexVVVV|VexW1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +@@ -2470,17 +2525,17 @@ clflushopt, 0x660fae/7, ClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex + + // XSAVES/XRSTORS instructions. + +-xrstors, 0xfc7/3, XSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } +-xrstors64, 0xfc7/3, XSAVES|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +-xsaves, 0xfc7/5, XSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } +-xsaves64, 0xfc7/5, XSAVES|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } ++xrstors, 0xfc7/3, XSAVES, Modrm|NoSuf|NoEgpr, { Unspecified|BaseIndex } ++xrstors64, 0xfc7/3, XSAVES&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } ++xsaves, 0xfc7/5, XSAVES, Modrm|NoSuf|NoEgpr, { Unspecified|BaseIndex } ++xsaves64, 0xfc7/5, XSAVES&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } + + // XSAVES instructions end. + + // XSAVEC instructions. + +-xsavec, 0xfc7/4, XSAVEC, Modrm|NoSuf, { Unspecified|BaseIndex } +-xsavec64, 0xfc7/4, XSAVEC|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } ++xsavec, 0xfc7/4, XSAVEC, Modrm|NoSuf|NoEgpr, { Unspecified|BaseIndex } ++xsavec64, 0xfc7/4, XSAVEC&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex } + + // XSAVEC instructions end. + +@@ -2494,108 +2549,108 @@ enclv, 0xf01c0, SE1, NoSuf, {} + + // AVX512VL instructions. + +-vgatherdpd, 0x6692, AVX512F|AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +-vgatherdps, 0x6692, AVX512F|AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +-vgatherdps, 0x6692, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +-vgatherqp, 0x6693, AVX512F|AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } +-vgatherqpd, 0x6693, AVX512F|AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } +-vgatherqps, 0x6693, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +-vpgatherdd, 0x6690, AVX512F|AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +-vpgatherdd, 0x6690, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +-vpgatherdq, 0x6690, AVX512F|AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +-vpgatherq, 0x6691, AVX512F|AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } +-vpgatherqd, 0x6691, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +-vpgatherqq, 0x6691, AVX512F|AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } +- +-vpscatterdd, 0x66A0, AVX512F|AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +-vpscatterdd, 0x66A0, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +-vpscatterdq, 0x66A0, AVX512F|AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +-vpscatterq, 0x66A1, AVX512F|AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } +-vpscatterqd, 0x66A1, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +-vpscatterqq, 0x66A1, AVX512F|AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } +-vscatterdpd, 0x66A2, AVX512F|AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +-vscatterdps, 0x66A2, AVX512F|AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +-vscatterdps, 0x66A2, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +-vscatterqp, 0x66A3, AVX512F|AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } +-vscatterqpd, 0x66A3, AVX512F|AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } +-vscatterqps, 0x66A3, AVX512F|AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +- +-vcvtdq2pd, 0xF3E6, AVX512F|AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtdq2pd, 0xF3E6, AVX512F|AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +-vcvtudq2pd, 0xF37A, AVX512F|AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtudq2pd, 0xF37A, AVX512F|AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +- +-vcvtph2ps, 0x6613, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtph2ps, 0x6613, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +- +-vcvtps2pd, 0x5A, AVX512F|AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtps2pd, 0x5A, AVX512F|AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +- +-vcvtps2ph, 0x661D, AVX512F|AVX512VL, Modrm|EVex128|Masking|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vcvtps2ph, 0x661D, AVX512F|AVX512VL, Modrm|EVex256|Masking|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } +- +-vmovddup, 0xF212, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +- +-vpmovdb, 0xF331, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovdb, 0xF331, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovsdb, 0xF321, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovsdb, 0xF321, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovusdb, 0xF311, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovusdb, 0xF311, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +- +-vpmovdw, 0xF333, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovdw, 0xF333, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +-vpmovsdw, 0xF323, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovsdw, 0xF323, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +-vpmovusdw, 0xF313, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovusdw, 0xF313, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +- +-vpmovqb, 0xF332, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +-vpmovqb, 0xF332, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovsqb, 0xF322, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +-vpmovsqb, 0xF322, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovusqb, 0xF312, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +-vpmovusqb, 0xF312, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +- +-vpmovqd, 0xF335, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovqd, 0xF335, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +-vpmovsqd, 0xF325, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovsqd, 0xF325, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +-vpmovusqd, 0xF315, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovusqd, 0xF315, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +- +-vpmovqw, 0xF334, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovqw, 0xF334, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovsqw, 0xF324, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovsqw, 0xF324, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +-vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +- +-vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +-vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +-vpmovzxdq, 0x6635, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +-vpmovzxdq, 0x6635, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } ++vgatherdpd, 0x6692, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } ++vgatherdps, 0x6692, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } ++vgatherdps, 0x6692, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } ++vgatherqp, 0x6693, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } ++vgatherqpd, 0x6693, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } ++vgatherqps, 0x6693, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } ++vpgatherdd, 0x6690, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } ++vpgatherdd, 0x6690, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } ++vpgatherdq, 0x6690, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } ++vpgatherq, 0x6691, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } ++vpgatherqd, 0x6691, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } ++vpgatherqq, 0x6691, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } ++ ++vpscatterdd, 0x66A0, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } ++vpscatterdd, 0x66A0, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } ++vpscatterdq, 0x66A0, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } ++vpscatterq, 0x66A1, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } ++vpscatterqd, 0x66A1, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } ++vpscatterqq, 0x66A1, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } ++vscatterdpd, 0x66A2, AVX512VL, Modrm|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } ++vscatterdps, 0x66A2, AVX512VL, Modrm|EVex=2|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } ++vscatterdps, 0x66A2, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } ++vscatterqp, 0x66A3, AVX512VL, Modrm|EVex128|Masking|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } ++vscatterqpd, 0x66A3, AVX512VL, Modrm|EVex256|Masking|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } ++vscatterqps, 0x66A3, AVX512VL, Modrm|EVex=3|Masking|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } ++ ++vcvtdq2pd, 0xF3E6, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtdq2pd, 0xF3E6, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++ ++vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } ++ ++vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++ ++vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex128|Masking|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex256|Masking|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } ++ ++vmovddup, 0xF212, AVX512VL, Modrm|EVex=2|Masking|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++ ++vpmovdb, 0xF331, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovdb, 0xF331, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovsdb, 0xF321, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovsdb, 0xF321, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovusdb, 0xF311, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovusdb, 0xF311, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } ++ ++vpmovdw, 0xF333, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovdw, 0xF333, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++vpmovsdw, 0xF323, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovsdw, 0xF323, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++vpmovusdw, 0xF313, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovusdw, 0xF313, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++ ++vpmovqb, 0xF332, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } ++vpmovqb, 0xF332, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovsqb, 0xF322, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } ++vpmovsqb, 0xF322, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovusqb, 0xF312, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } ++vpmovusqb, 0xF312, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } ++ ++vpmovqd, 0xF335, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovqd, 0xF335, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++vpmovsqd, 0xF325, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovsqd, 0xF325, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++vpmovusqd, 0xF315, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovusqd, 0xF315, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++ ++vpmovqw, 0xF334, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovqw, 0xF334, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovsqw, 0xF324, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovsqw, 0xF324, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovusqw, 0xF314, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } ++vpmovusqw, 0xF314, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } ++ ++vpmovsxdq, 0x6625, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++vpmovsxdq, 0x6625, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } ++vpmovzxdq, 0x6635, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++vpmovzxdq, 0x6635, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + + // AVX512VL instructions end. + + // AVX512BW instructions. + +-kadd, 0x4a, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } +-kand, 0x41, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } +-kandn, 0x42, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf|Optimize, { RegMask, RegMask, RegMask } +-kmov, 0x90, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +-kmov, 0x91, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, |Unspecified|BaseIndex } +-kmov, 0xf292, AVX512BW, D|Modrm|Vex128|Space0F|||NoSuf, { , RegMask } +-knot, 0x44, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } +-kor, 0x45, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } +-kortest, 0x98, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } +-ktest, 0x99, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } +-kxnor, 0x46, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } +-kxor, 0x47, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf|Optimize, { RegMask, RegMask, RegMask } +-kunpckdq, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|Vsz512|NoSuf, { RegMask, RegMask, RegMask } +-kunpckwd, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW0|Vsz256|NoSuf, { RegMask, RegMask, RegMask } +-kshiftl, 0x6633, AVX512BW, Modrm|Vex128|Space0F3A|||NoSuf, { Imm8, RegMask, RegMask } +-kshiftr, 0x6631, AVX512BW, Modrm|Vex128|Space0F3A|||NoSuf, { Imm8, RegMask, RegMask } ++kadd, 0x4a, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } ++kand, 0x41, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } ++kandn, 0x42, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } ++kmov, 0x90, APX_F(AVX512BW), Modrm|Vex128|EVex128|Space0F|VexW1|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } ++kmov, 0x91, APX_F(AVX512BW), Modrm|Vex128|EVex128|Space0F|VexW1|NoSuf, { RegMask, |Unspecified|BaseIndex } ++kmov, 0xf292, APX_F(AVX512BW), D|Modrm|Vex128|EVex128|Space0F||NoSuf, { , RegMask } ++knot, 0x44, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } ++kor, 0x45, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } ++kortest, 0x98, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } ++ktest, 0x99, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } ++kxnor, 0x46, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } ++kxor, 0x47, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } ++kunpckdq, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } ++kunpckwd, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } ++kshiftl, 0x6633, AVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } ++kshiftr, 0x6631, AVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } + + vdbpsadbw, 0x6642, AVX512BW, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +@@ -2681,23 +2736,23 @@ vpmov2m, 0xf329, AVX512BW, Modrm|EVexDYN|Space0F38||NoSuf, { RegXMM + vpmovm2, 0xf328, AVX512BW, Modrm|EVexDYN|Space0F38||NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } + + vpmovswb, 0xF320, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +-vpmovswb, 0xF320, AVX512BW|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovswb, 0xF320, AVX512BW|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++vpmovswb, 0xF320, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovswb, 0xF320, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + + vpmovuswb, 0xF310, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +-vpmovuswb, 0xF310, AVX512BW|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovuswb, 0xF310, AVX512BW|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++vpmovuswb, 0xF310, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovuswb, 0xF310, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + + vpmovwb, 0xF330, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +-vpmovwb, 0xF330, AVX512BW|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +-vpmovwb, 0xF330, AVX512BW|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } ++vpmovwb, 0xF330, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } ++vpmovwb, 0xF330, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + + vpmovsxbw, 0x6620, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +-vpmovsxbw, 0x6620, AVX512BW|AVX512VL, Modrm|EVex=2|Masking|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +-vpmovsxbw, 0x6620, AVX512BW|AVX512VL, Modrm|EVex=3|Masking|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } ++vpmovsxbw, 0x6620, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++vpmovsxbw, 0x6620, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + vpmovzxbw, 0x6630, AVX512BW, Modrm|EVex=1|Masking|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +-vpmovzxbw, 0x6630, AVX512BW|AVX512VL, Modrm|EVex=2|Masking|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +-vpmovzxbw, 0x6630, AVX512BW|AVX512VL, Modrm|EVex=3|Masking|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } ++vpmovzxbw, 0x6630, AVX512BW&AVX512VL, Modrm|EVex=2|Masking|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } ++vpmovzxbw, 0x6630, AVX512BW&AVX512VL, Modrm|EVex=3|Masking|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + + vpsadbw, 0x66F6, AVX512BW, Modrm|Space0F|VexVVVV|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +@@ -2738,36 +2793,36 @@ vcvtpd2qq, 0x667B, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL| + vcvtpd2uqq, 0x6679, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + + vcvtps2qq, 0x667B, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +-vcvtps2qq, 0x667B, AVX512DQ|AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtps2qq, 0x667B, AVX512DQ|AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++vcvtps2qq, 0x667B, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtps2qq, 0x667B, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + vcvtps2uqq, 0x6679, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +-vcvtps2uqq, 0x6679, AVX512DQ|AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtps2uqq, 0x6679, AVX512DQ|AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++vcvtps2uqq, 0x6679, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtps2uqq, 0x6679, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + + vcvtqq2pd, 0xF3E6, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vcvtuqq2pd, 0xF37A, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +-vcvtqq2ps, 0x5b, AVX512DQ|, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } ++vcvtqq2ps, 0x5b, AVX512DQ&, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } + + vcvttpd2qq, 0x667A, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vcvttpd2uqq, 0x6678, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + + vcvttps2qq, 0x667A, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +-vcvttps2qq, 0x667A, AVX512DQ|AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-vcvttps2qq, 0x667A, AVX512DQ|AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++vcvttps2qq, 0x667A, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++vcvttps2qq, 0x667A, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + vcvttps2uqq, 0x6678, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +-vcvttps2uqq, 0x6678, AVX512DQ|AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +-vcvttps2uqq, 0x6678, AVX512DQ|AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } ++vcvttps2uqq, 0x6678, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } ++vcvttps2uqq, 0x6678, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +-vcvtuqq2ps, 0xf27a, AVX512DQ|, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } ++vcvtuqq2ps, 0xf27a, AVX512DQ&, Modrm||Masking|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } + + vextractf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } + vextracti32x8, 0x663B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } + vinsertf32x8, 0x661A, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } + vinserti32x8, 0x663A, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } + +-vpextr, 0x6616, AVX512DQ|, Modrm|EVex128|Space0F3A||Disp8MemShift|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } +-vpinsr, 0x6622, AVX512DQ|, Modrm|EVex128|Space0F3A|VexVVVV||Disp8MemShift|NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } ++vpextr, 0x6616, AVX512DQ&, Modrm|EVex128|Space0F3A||Disp8MemShift|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } ++vpinsr, 0x6622, AVX512DQ&, Modrm|EVex128|Space0F3A|VexVVVV||Disp8MemShift|NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } + + vextractf64x2, 0x6619, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } + vextracti64x2, 0x6639, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +@@ -2777,8 +2832,8 @@ vinserti64x2, 0x6638, AVX512DQ, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Disp8MemSh + vfpclassp, 0x6666, AVX512DQ, Modrm|Masking|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegMask } + vfpclassp, 0x6666, AVX512DQ, Modrm|Masking|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } + vfpclasspz, 0x6666, AVX512DQ, Modrm|EVex512|Masking|Space0F3A||Broadcast|Disp8MemShift=6|NoSuf, { Imm8|Imm8S, RegZMM||Unspecified|BaseIndex, RegMask } +-vfpclasspx, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex128|Masking|Space0F3A||Broadcast|Disp8MemShift=4|NoSuf, { Imm8|Imm8S, RegXMM||Unspecified|BaseIndex, RegMask } +-vfpclasspy, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex256|Masking|Space0F3A||Broadcast|Disp8MemShift=5|NoSuf, { Imm8|Imm8S, RegYMM||Unspecified|BaseIndex, RegMask } ++vfpclasspx, 0x6666, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F3A||Broadcast|Disp8MemShift=4|NoSuf, { Imm8|Imm8S, RegXMM||Unspecified|BaseIndex, RegMask } ++vfpclasspy, 0x6666, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F3A||Broadcast|Disp8MemShift=5|NoSuf, { Imm8|Imm8S, RegYMM||Unspecified|BaseIndex, RegMask } + vfpclasss, 0x67, , Modrm|EVexLIG|Masking|Space0F3A||Disp8MemShift|NoSuf, { Imm8|Imm8S, RegXMM||Unspecified|BaseIndex, RegMask } + + vpmov2m, 0xf339, AVX512DQ, Modrm|EVexDYN|Space0F38||NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } +@@ -2916,8 +2971,8 @@ vpshufbitqmb, 0x668f, AVX512_BITALG, Modrm|Masking|Space0F38|VexVVVV|VexW0|Disp8 + + // AVX512 + GFNI instructions + +-vgf2p8affineinvqb, 0x66cf, GFNI|AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +-vgf2p8affineqb, 0x66ce, GFNI|AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vgf2p8affineinvqb, 0x66cf, GFNI&AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } ++vgf2p8affineqb, 0x66ce, GFNI&AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + + // AVX512 + GFNI instructions end + +@@ -2946,7 +3001,7 @@ clzero, 0xf01fc, CLZERO, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } + monitorx, 0xf01fa, MWAITX, NoSuf, {} + monitorx, 0xf01fa, MWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } + // The 64-bit form exists only for compatibility with older gas. +-monitorx, 0xf01fa, MWAITX|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } ++monitorx, 0xf01fa, MWAITX&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } + + mwaitx, 0xf01fb, MWAITX, NoSuf, {} + // The 64-bit form exists only for compatibility with older gas. +@@ -2963,30 +3018,34 @@ wrpkru, 0xf01ef, OSPKE, NoSuf, {} + + // RDPID instructions. + +-rdpid, 0xf30fc7/7, RDPID|No64, Modrm|IgnoreSize|NoSuf, { Reg32 } +-rdpid, 0xf30fc7/7, RDPID|x64, Modrm|NoSuf|NoRex64, { Reg64 } ++rdpid, 0xf30fc7/7, RDPID&No64, Modrm|IgnoreSize|NoSuf, { Reg32 } ++rdpid, 0xf30fc7/7, RDPID&x64, Modrm|NoSuf|NoRex64, { Reg64 } + + // RDPID instructions end. + + // PTWRITE instructions. + +-ptwrite, 0xf30fae/4, PTWRITE|No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Unspecified|BaseIndex } +-ptwrite, 0xf30fae/4, PTWRITE|x64, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex } ++ptwrite, 0xf30fae/4, PTWRITE&No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex } ++ptwrite, 0xf30fae/4, PTWRITE&x64, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex } + + // PTWRITE instructions end. + + // CET instructions. + + incsspd, 0xf30fae/5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } +-incsspq, 0xf30fae/5, SHSTK|x64, Modrm|NoSuf, { Reg64 } ++incsspq, 0xf30fae/5, SHSTK&x64, Modrm|NoSuf, { Reg64 } + rdsspd, 0xf30f1e/1, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } +-rdsspq, 0xf30f1e/1, SHSTK|x64, Modrm|NoSuf, { Reg64 } ++rdsspq, 0xf30f1e/1, SHSTK&x64, Modrm|NoSuf, { Reg64 } + saveprevssp, 0xf30f01ea, SHSTK, NoSuf, {} + rstorssp, 0xf30f01/5, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } + wrssd, 0x0f38f6, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +-wrssq, 0x0f38f6, SHSTK|x64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } ++wrssd, 0x66, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } ++wrssq, 0x0f38f6, SHSTK&x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } ++wrssq, 0x66, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } + wrussd, 0x660f38f5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +-wrussq, 0x660f38f5, SHSTK|x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } ++wrussd, 0x6665, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } ++wrussq, 0x660f38f5, SHSTK&x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } ++wrussq, 0x6665, SHSTK&APX_F, Modrm|NoSuf|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } + setssbsy, 0xf30f01e8, SHSTK, NoSuf, {} + clrssbsy, 0xf30fae/6, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } + endbr64, 0xf30f1efa, IBT, NoSuf, {} +@@ -3011,7 +3070,7 @@ pconfig, 0x0f01c5, PCONFIG, NoSuf, {} + + // PBNDKB instruction. + +-pbndkb, 0x0f01c7, PBNDKB|x64, NoSuf, {} ++pbndkb, 0x0f01c7, PBNDKB, NoSuf, {} + + // PBNDKB instruction end. + +@@ -3034,7 +3093,9 @@ cldemote, 0x0f1c/0, CLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } + // MOVDIR[I,64B] instructions. + + movdiri, 0xf38f9, MOVDIRI, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } ++movdiri, 0xf9, MOVDIRI&APX_F, Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } + movdir64b, 0x660f38f8, MOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++movdir64b, 0x66f8, MOVDIR64B&APX_F, Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } + + // MOVEDIR instructions end. + +@@ -3042,7 +3103,7 @@ movdir64b, 0x660f38f8, MOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|Bas + + vcvtne2ps2bf16, 0xf272, AVX512_BF16, Modrm|Space0F38|VexVVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +-vcvtneps2bf16, 0xf372, AVX512_BF16|, Modrm|Space0F38||Masking|VexW0|Broadcast|NoSuf, { |Dword, } ++vcvtneps2bf16, 0xf372, AVX512_BF16&, Modrm|Space0F38||Masking|VexW0|Broadcast|NoSuf, { |Dword, } + + vdpbf16ps, 0xf352, AVX512_BF16, Modrm|Space0F38|VexVVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +@@ -3063,7 +3124,9 @@ vcvtneps2bf16, 0xf372, AVX_NE_CONVERT, Modrm||Space0F38|VexW0|NoSu + // ENQCMD instructions. + + enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++enqcmd, 0xf2f8, APX_F(ENQCMD), Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } + enqcmds, 0xf30f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ++enqcmds, 0xf3f8, APX_F(ENQCMD), Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } + + // ENQCMD instructions end. + +@@ -3081,25 +3144,25 @@ mcommit, 0xf30f01fa, MCOMMIT, NoSuf, {} + + // SNP instructions + +-psmash, 0xf30f01ff, SNP|x64, NoSuf, {} +-psmash, 0xf30f01ff, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } ++psmash, 0xf30f01ff, SNP&x64, NoSuf, {} ++psmash, 0xf30f01ff, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } + pvalidate, 0xf20f01ff, SNP, NoSuf, {} + pvalidate, 0xf20f01ff, SNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +-rmpupdate, 0xf20f01fe, SNP|x64, NoSuf, {} +-rmpupdate, 0xf20f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } +-rmpadjust, 0xf30f01fe, SNP|x64, NoSuf, {} +-rmpadjust, 0xf30f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } ++rmpupdate, 0xf20f01fe, SNP&x64, NoSuf, {} ++rmpupdate, 0xf20f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } ++rmpadjust, 0xf30f01fe, SNP&x64, NoSuf, {} ++rmpadjust, 0xf30f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } + // The single-operand forms exist only for compatibility with older gas. + pvalidate, 0xf20f01ff, SNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +-rmpupdate, 0xf20f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +-rmpadjust, 0xf30f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } ++rmpupdate, 0xf20f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } ++rmpadjust, 0xf30f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } + + // SNP instructions end + + // RMPQUERY instruction + +-rmpquery, 0xf30f01fd, RMPQUERY|x64, NoSuf, {} +-rmpquery, 0xf30f01fd, RMPQUERY|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } ++rmpquery, 0xf30f01fd, RMPQUERY, NoSuf, {} ++rmpquery, 0xf30f01fd, RMPQUERY, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } + + // RMPQUERY instruction end + +@@ -3124,26 +3187,26 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {} + + // AMX instructions. + +-ldtilecfg, 0x49/0, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +-sttilecfg, 0x6649/0, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } ++ldtilecfg, 0x49/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } ++sttilecfg, 0x6649/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } + +-tcmmimfp16ps, 0x666c, AMX_COMPLEX|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +-tcmmrlfp16ps, 0x6c, AMX_COMPLEX|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tcmmimfp16ps, 0x666c, AMX_COMPLEX, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tcmmrlfp16ps, 0x6c, AMX_COMPLEX, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } + +-tdpbf16ps, 0xf35c, AMX_BF16|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +-tdpfp16ps, 0xf25c, AMX_FP16|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +-tdpbssd, 0xf25e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +-tdpbuud, 0x5e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +-tdpbusd, 0x665e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +-tdpbsud, 0xf35e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tdpbf16ps, 0xf35c, AMX_BF16, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tdpfp16ps, 0xf25c, AMX_FP16, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tdpbssd, 0xf25e, AMX_INT8, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tdpbuud, 0x5e, AMX_INT8, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tdpbusd, 0x665e, AMX_INT8, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } ++tdpbsud, 0xf35e, AMX_INT8, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } + +-tileloadd, 0xf24b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +-tileloaddt1, 0x664b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +-tilestored, 0xf34b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } ++tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } ++tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } ++tilestored, 0xf34b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } + +-tilerelease, 0x49c0, AMX_TILE|x64, Vex128|Space0F38|VexW0|NoSuf, {} ++tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {} + +-tilezero, 0xf249, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } ++tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } + + // AMX instructions end. + +@@ -3166,19 +3229,19 @@ aesdecwide256kl, 0xf30f38d8/3, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } + // TDX instructions. + + tdcall, 0x660f01cc, TDX, NoSuf, {} +-seamret, 0x660f01cd, TDX|x64, NoSuf, {} +-seamops, 0x660f01ce, TDX|x64, NoSuf, {} +-seamcall, 0x660f01cf, TDX|x64, NoSuf, {} ++seamret, 0x660f01cd, TDX&x64, NoSuf, {} ++seamops, 0x660f01ce, TDX&x64, NoSuf, {} ++seamcall, 0x660f01cf, TDX&x64, NoSuf, {} + + // TDX instructions end. + + // UINTR instructions. + +-uiret, 0xf30f01ec, UINTR|x64, NoSuf, {} +-clui, 0xf30f01ee, UINTR|x64, NoSuf, {} +-stui, 0xf30f01ef, UINTR|x64, NoSuf, {} +-testui, 0xf30f01ed, UINTR|x64, NoSuf, {} +-senduipi, 0xf30fc7/6, UINTR|x64, Modrm|NoSuf|NoRex64, { Reg64 } ++uiret, 0xf30f01ec, UINTR, NoSuf, {} ++clui, 0xf30f01ee, UINTR, NoSuf, {} ++stui, 0xf30f01ef, UINTR, NoSuf, {} ++testui, 0xf30f01ed, UINTR, NoSuf, {} ++senduipi, 0xf30fc7/6, UINTR, Modrm|NoSuf|NoRex64, { Reg64 } + + // UINTR instructions end. + +@@ -3208,37 +3271,37 @@ vcmpph, 0xc2, AVX512_FP16, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8 + vcmpsh, 0xf3c2/0x, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } + vcmpsh, 0xf3c2, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } + +-vcvtdq2ph, 0x5b, AVX512_FP16|, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } +-vcvtudq2ph, 0xf27a, AVX512_FP16|, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } ++vcvtdq2ph, 0x5b, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } ++vcvtudq2ph, 0xf27a, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } + +-vcvtqq2ph, 0x5b, AVX512_FP16|, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } +-vcvtuqq2ph, 0xf27a, AVX512_FP16|, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } ++vcvtqq2ph, 0x5b, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } ++vcvtuqq2ph, 0xf27a, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } + +-vcvtpd2ph, 0x665a, AVX512_FP16|, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } ++vcvtpd2ph, 0x665a, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } + +-vcvtps2phx, 0x661d, AVX512_FP16|, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } ++vcvtps2phx, 0x661d, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } + + vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +-vcvtph2dq, 0x665b, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtph2dq, 0x665b, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } ++vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } + vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvtph2udq, 0x79, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtph2udq, 0x79, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } ++vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } + vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvtph2qq, 0x667b, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +-vcvtph2qq, 0x667b, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } ++vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } ++vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } + vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvtph2uqq, 0x6679, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +-vcvtph2uqq, 0x6679, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } ++vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } ++vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } + vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvtph2pd, 0x5a, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +-vcvtph2pd, 0x5a, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } ++vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } ++vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } + vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } + + vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +@@ -3258,24 +3321,24 @@ vcvtsh2ss, 0x13, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|VexVVVV|VexW0|Disp8 + + vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } + +-vcvttph2dq, 0xf35b, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +-vcvttph2dq, 0xf35b, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } ++vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } ++vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } + vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvttph2udq, 0x78, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +-vcvttph2udq, 0x78, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } ++vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } ++vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } + vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvttph2qq, 0x667a, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +-vcvttph2qq, 0x667a, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } ++vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } ++vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } + vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvttph2uqq, 0x6678, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +-vcvttph2uqq, 0x6678, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } ++vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } ++vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } + vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } + +-vcvtph2psx, 0x6613, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +-vcvtph2psx, 0x6613, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } ++vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } ++vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } + vcvtph2psx, 0x6613, AVX512_FP16, Modrm|EVex512|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } + + vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +@@ -3283,7 +3346,7 @@ vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8Shift + + vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } + +-vfpclassph, 0x66, AVX512_FP16|, Modrm||Masking|Space0F3A|VexW0|Broadcast|NoSuf|, { Imm8|Imm8S, |Word, RegMask } ++vfpclassph, 0x66, AVX512_FP16&, Modrm||Masking|Space0F3A|VexW0|Broadcast|NoSuf|, { Imm8|Imm8S, |Word, RegMask } + + vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } + vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } +@@ -3300,14 +3363,14 @@ vrsqrtsh, 0x664f, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|VexVVVV|VexW0|Disp + + // PREFETCHI instructions. + +-prefetchit0, 0xf18/7, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +-prefetchit1, 0xf18/6, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } ++prefetchit0, 0xf18/7, PREFETCHI, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } ++prefetchit1, 0xf18/6, PREFETCHI, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } + + // PREFETCHI instructions end. + + // CMPCCXADD instructions. + +-cmpxadd, 0x66e, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } ++cmpxadd, 0x66e, APX_F(CMPCCXADD), Modrm|Vex|EVex128|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } + + // CMPCCXADD instructions end. + +@@ -3319,30 +3382,52 @@ wrmsrns, 0x0f01c6, WRMSRNS, NoSuf, {} + + // MSRLIST instructions. + +-rdmsrlist, 0xf20f01c6, MSRLIST|x64, NoSuf, {} +-wrmsrlist, 0xf30f01c6, MSRLIST|x64, NoSuf, {} ++rdmsrlist, 0xf20f01c6, MSRLIST, NoSuf, {} ++wrmsrlist, 0xf30f01c6, MSRLIST, NoSuf, {} + + // MSRLIST instructions end. + + // RAO-INT instructions. + +-aadd, 0xf38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +-aand, 0x660f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +-aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +-axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } ++ ++a, 0x0f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } ++a, 0xfc, RAO_INT&APX_F, Modrm|CheckOperandSize|NoSuf|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } ++ + + // RAO-INT instructions end. + + // LKGS instruction. + +-lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } +-lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } ++lkgs, 0xf20f00/6, LKGS, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } ++lkgs, 0xf20f00/6, LKGS, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } + + // LKGS instruction end. + + // FRED instructions. + +-erets, 0xf20f01ca, FRED|x64, NoSuf, {} +-eretu, 0xf30f01ca, FRED|x64, NoSuf, {} ++erets, 0xf20f01ca, FRED, NoSuf, {} ++eretu, 0xf30f01ca, FRED, NoSuf, {} + + // FRED instructions end. ++ ++// USER_MSR instructions. ++ ++urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } ++urdmsr, 0xf2f8, USER_MSR&APX_F, RegMem|EVexMap4|VexW0|NoSuf, { Reg64, Reg64 } ++urdmsr, 0xf2f8/0, APX_F(USER_MSR), Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 } ++uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } ++uwrmsr, 0xf3f8, USER_MSR&APX_F, Modrm|EVexMap4|VexW0|NoSuf, { Reg64, Reg64 } ++// Immediates want to be first; md_assemble() takes care of swapping operands ++// accordingly. ++uwrmsr, 0xf3f8/0, APX_F(USER_MSR), Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 } ++ ++// USER_MSR instructions end. ++ ++// APX Push2/Pop2 instructions. ++ ++push2, 0xff/6, APX_F, Modrm|VexW0|EVexMap4|VexVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } ++push2p, 0xff/6, APX_F, Modrm|VexW1|EVexMap4|VexVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } ++pop2, 0x8f/0, APX_F, Modrm|VexW0|EVexMap4|VexVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } ++pop2p, 0x8f/0, APX_F, Modrm|VexW1|EVexMap4|VexVVVV|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } ++ ++// APX Push2/Pop2 instructions end. diff --git a/gdb.spec b/gdb.spec index 61aa74a..5fc2a8a 100644 --- a/gdb.spec +++ b/gdb.spec @@ -53,11 +53,11 @@ Name: %{?scl_prefix}gdb # See timestamp of source gnulib installed into gnulib/ . %global snapgnulib 20220501 %global tarname gdb-%{version} -Version: 14.1 +Version: 14.2 # The release always contains a leading reserved number, start it at 1. # `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing. -Release: 8%{?dist} +Release: 1%{?dist} License: GPL-3.0-or-later AND BSD-3-Clause AND FSFAP AND LGPL-2.1-or-later AND GPL-2.0-or-later AND LGPL-2.0-or-later AND LicenseRef-Fedora-Public-Domain AND GFDL-1.3-or-later AND LGPL-2.0-or-later WITH GCC-exception-2.0 AND GPL-3.0-or-later WITH GCC-exception-3.1 AND GPL-2.0-or-later WITH GNU-compiler-exception # Do not provide URL for snapshots as the file lasts there only for 2 days. @@ -112,7 +112,7 @@ Summary: A GNU source-level debugger for C, C++, Fortran, Go and other languages Obsoletes: gdb64 < 5.3.91 %endif -%ifarch %{arm} +%ifarch %{arm} riscv64 %global have_inproctrace 0 %else %global have_inproctrace 1 @@ -314,7 +314,7 @@ BuildRequires: elfutils-debuginfod-client-devel %if 0%{!?el6:1} && 0%{?scl:1} %global have_debuginfod 1 %global use_scl_for_debuginfod 1 -BuildRequires: %{?scl_prefix}elfutils-debuginfod-client-devel +BuildRequires: elfutils-debuginfod-client-devel %endif %endif @@ -343,7 +343,7 @@ BuildRequires: boost-devel BuildRequires: sharutils dejagnu # gcc-objc++ is not covered by the GDB testsuite. # Test supported SCL toolchain components. -BuildRequires: %{?scl_prefix}gcc %{?scl_prefix}gcc-c++ %{?scl_prefix}gcc-gfortran +BuildRequires: %{?scl_testing_prefix}gcc %{?scl_testing_prefix}gcc-c++ %{?scl_testing_prefix}gcc-gfortran %if 0%{!?rhel:1} || 0%{?rhel} < 8 BuildRequires: gcc-objc @@ -398,7 +398,7 @@ BuildRequires: gcc-gnat BuildRequires: libgnat%{bits_local} libgnat%{bits_other} %endif %else -%ifarch %{ix86} x86_64 ia64 ppc %{power64} alpha s390x %{arm} aarch64 +%ifarch %{ix86} x86_64 ia64 ppc %{power64} alpha s390x %{arm} aarch64 riscv64 %if 0%{!?rhel:1} BuildRequires: gcc-gnat BuildRequires: libgnat%{bits_local} libgnat%{bits_other} @@ -420,12 +420,12 @@ BuildRequires: libquadmath%{bits_local} libquadmath%{bits_other} BuildRequires: glibc-static%{bits_other} %endif %ifarch s390x -BuildRequires: %{?scl_preifx}valgrind%{bits_local} +BuildRequires: valgrind%{bits_local} %if 0%{!?rhel:1} || 0%{?rhel} > 7 -BuildRequires: %{?scl_prefix}valgrind%{bits_local} valgrind%{bits_other} +BuildRequires: valgrind%{bits_local} valgrind%{bits_other} %endif %else -BuildRequires: %{?scl_prefix}valgrind%{bits_local} valgrind%{bits_other} +BuildRequires:valgrind%{bits_local} valgrind%{bits_other} %endif %if 0%{!?rhel:1} || 0%{?rhel} > 6 BuildRequires: xz @@ -434,7 +434,7 @@ BuildRequires: xz BuildRequires: rust %endif %if 0%{!?el6:1} -BuildRequires: %{?scl_prefix}elfutils-debuginfod +BuildRequires: elfutils-debuginfod %endif %endif # 0%{?_with_testsuite:1} BuildRequires: make gmp-devel @@ -619,7 +619,7 @@ COMMON_GDB_CONFIGURE_FLAGS="\ ,-Wno-format-overflow\ %endif --enable-build-with-cxx \ -%ifnarch %{ix86} alpha ppc s390 s390x x86_64 ppc64 ppc64le sparc sparcv9 sparc64 %{arm} aarch64 +%ifnarch %{ix86} alpha ppc s390 s390x x86_64 ppc64 ppc64le sparc sparcv9 sparc64 %{arm} aarch64 riscv64 --disable-werror \ %else --enable-werror \ @@ -1250,6 +1250,43 @@ fi %endif %changelog +* Wed May 29 2024 Keith Seitz - 14.2-1.el10 +- Rebase to gdb-14.2 and update all bug references: + RHEL-39326 "better support for $pc not saved" + RHEL-39325 "Infcalls from B/P conditions in multi-threaded inferiors" + RHEL-39324 "gdb: s390: Add arch14 record/replay support" + RHEL-24764 "Add support for Power11 options" + RHEL-34213 "Sync x86 disassembler with (proposed) gdb-15.1 release." + (Keith Seitz, RHEL-33256) + +* Wed May 29 2024 Guinevere Larsen - 14.2-3.el8 +- Remove riscv64-linux-gnu target. It was never meant to be added. + +* Thu May 16 2024 Guinevere Larsen - 14.2-2.el8 +- Backport "better support for $pc not saved" + (Andrew Burgess, RHEL-19390) + +* Mon May 13 2024 Guinevere Larsen +- Backport series Infcalls from B/P conditions in multi-threaded inferiors + (Andrew Burgess, RHEL-13298) + +* Mon May 13 2024 Keith Seitz +- Backport "gdb: s390: Add arch14 record/replay support" + (Andreas Arnez, RHEL-36225) +- Backport "Add support for Power11 options" + (Peter Bergner, RHEL-36518) +- Backport "Sync x86 disassembler with (proposed) gdb-15.1 release." + (many authors, RHEL-36527) + +* Tue Apr 23 2024 Guinevere Larsen - 14.2-1.el8 +- Initial import for GTS14. + +* Tue Mar 12 2024 Alexandra Hájková - 14.2-1 +- Rebase to FSF GDB 14.2. + +* Wed Feb 21 2024 Richard W.M. Jones +- Bump and rebuild for riscv64 + * Mon Jan 29 2024 Kevin Buettner - 14.1-8 - Backport upstream workaround for GCC 14 problem which is causing GDB internal errors (RHBZ 261580, Tom de Vries). diff --git a/sources b/sources index 960a489..1451359 100644 --- a/sources +++ b/sources @@ -1,3 +1,3 @@ SHA512 (gdb-libstdc++-v3-python-8.1.1-20180626.tar.xz) = a8b1c54dd348cfeb37da73f968742896be3dd13a4215f8d8519870c2abea915f5176c3fa6989ddd10f20020a16f0fab20cbae68ee8d58a82234d8778023520f8 +SHA512 (gdb-14.2.tar.xz) = 7e07941f1fe661288cc571b4964012ceabc1760624fce20320db2f470c01439b2386f859b5288da13204b758e2e3b22a74c68c012178db93b9529b06f1e22ede SHA512 (v2.0.5.tar.gz) = 2e7ac2aede84671b15597d9c56dbe077a81357bbf44b6684802592246fb7729b4a5743238ddf02f6ea143b4d29872f581408135f9c1ea1ccc99dab905916d98d -SHA512 (gdb-14.1.tar.xz) = 575e198105076fc4a88f68591aa114ab9c1196e84386a3f7b9b58fe5f30cdeed33f6a5f957b68f08c47284ec922bb60c964627e238471419673fd913575ce427