import gdb-8.2-17.el8
This commit is contained in:
CentOS Sources
Stepan Oksanichenko
parent
ef09c45b0b
commit
c7f2045cbf
@ -783,3 +783,23 @@ Patch191: gdb-rhbz1854784-powerpc-remove-region-limit-dawr-6of7.patch
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# (Rogerio Alves, RH BZ 1854784)
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# (Rogerio Alves, RH BZ 1854784)
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Patch192: gdb-rhbz1854784-powerpc-remove-region-limit-dawr-7of7.patch
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Patch192: gdb-rhbz1854784-powerpc-remove-region-limit-dawr-7of7.patch
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# IBM Z: Add support for HLASM extended mnemonics
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# (Andreas Krebbel, RHBZ 2012818)
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Patch193: gdb-rhbz2012818-ibmz-update-1of5.patch
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# IBM Z: Add risbgz and risbgnz extended mnemonics
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# (Andreas Krebbel, RHBZ 2012818)
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Patch194: gdb-rhbz2012818-ibmz-update-2of5.patch
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# IBM Z: Implement instruction set extensions
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# (Andreas Krebbel, RHBZ 2012818)
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Patch195: gdb-rhbz2012818-ibmz-update-3of5.patch
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# IBM Z: Remove lpswey parameter
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# (Andreas Krebbel, RHBZ 2012818)
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Patch196: gdb-rhbz2012818-ibmz-update-4of5.patch
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# IBM Z: Add another arch14 instruction
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# (Andreas Krebbel, RHBZ 2012818)
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Patch197: gdb-rhbz2012818-ibmz-update-5of5.patch
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@ -190,3 +190,8 @@
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%patch190 -p1
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%patch190 -p1
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%patch191 -p1
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%patch191 -p1
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%patch192 -p1
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%patch192 -p1
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%patch193 -p1
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%patch194 -p1
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%patch195 -p1
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%patch196 -p1
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%patch197 -p1
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99
SOURCES/gdb-rhbz2012818-ibmz-update-1of5.patch
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99
SOURCES/gdb-rhbz2012818-ibmz-update-1of5.patch
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@ -0,0 +1,99 @@
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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Andreas Krebbel <krebbel@linux.ibm.com>
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Date: Thu, 3 Dec 2020 16:31:15 +0100
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Subject: gdb-rhbz2012818-ibmz-update-1of5.patch
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;; IBM Z: Add support for HLASM extended mnemonics
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;; (Andreas Krebbel, RHBZ 2012818)
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Add extended mnemonics used in the HLASM assembler. All of them are
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just aliases for instructions we already support and help when
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assembling code which was written for the HLASM assembler.
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The HLASM mnemonics are documented here:
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https://www.ibm.com/support/knowledgecenter/SSENW6_1.6.0/com.ibm.hlasm.v1r6.asm/asmr1023.pdf
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See the 'Branching with extended mnemonic codes' chapter.
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objdump will still print the existing mnemonics with the exception of
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relative nop branches (i.e. conditional branches with an empty
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condition code mask). Now we have jnop and jgnop which will be used
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by objdump when possible.
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The same change have been applied to the LLVM assembler:
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https://reviews.llvm.org/D92185
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opcodes/
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* s390-opc.txt: Add extended mnemonics.
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gas/
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* testsuite/gas/s390/esa-g5.s: Test new extended mnemonics.
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* testsuite/gas/s390/esa-g5.d: Likewise.
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* testsuite/gas/s390/esa-z900.s: Likewise.
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* testsuite/gas/s390/esa-z900.d: Likewise.
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* testsuite/gas/s390/zarch-z900.s: Likewise.
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* testsuite/gas/s390/zarch-z900.d: Likewise.
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ld/
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* testsuite/ld-s390/tlsbin_64.dd: The newly added jgnop mnemonic
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replaces long relative branches with empty condition code mask.
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diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
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--- a/opcodes/s390-opc.txt
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+++ b/opcodes/s390-opc.txt
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@@ -246,10 +246,14 @@ d7 xc SS_L0RDRD "exclusive OR" g5 esa,zarch
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f8 zap SS_LLRDRD "zero and add" g5 esa,zarch
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a70a ahi RI_RI "add halfword immediate" g5 esa,zarch
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84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch
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+84 jxh RSI_RRP "branch relative on index high" g5 esa,zarch
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85 brxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch
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+85 jxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch
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a705 bras RI_RP "branch relative and save" g5 esa,zarch
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+a705 jas RI_RP "branch relative and save" g5 esa,zarch
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a704 brc RI_UP "branch relative on condition" g5 esa,zarch
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a706 brct RI_RP "branch relative on count" g5 esa,zarch
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+a706 jct RI_RP "branch relative on count" g5 esa,zarch
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b241 cksm RRE_RR "checksum" g5 esa,zarch
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a70e chi RI_RI "compare halfword immediate" g5 esa,zarch
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a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch
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@@ -268,8 +272,11 @@ a701 tml RI_RU "test under mask low" g5 esa,zarch
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4700 nop RX_0RRD "no operation" g5 esa,zarch optparm
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4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch
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47f0 b RX_0RRD "unconditional branch" g5 esa,zarch
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+a704 jnop RI_0P "nop jump" g5 esa,zarch
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a704 j*8 RI_0P "conditional jump" g5 esa,zarch
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+a704 br*8 RI_0P "conditional jump" g5 esa,zarch
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a7f4 j RI_0P "unconditional jump" g5 esa,zarch
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+a7f4 bru RI_0P "unconditional jump" g5 esa,zarch
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b34a axbr RRE_FEFE "add extended bfp" g5 esa,zarch
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b31a adbr RRE_FF "add long bfp" g5 esa,zarch
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ed000000001a adb RXE_FRRD "add long bfp" g5 esa,zarch
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@@ -437,7 +444,9 @@ e3000000001b slgf RXE_RRRD "subtract logical 64<32" z900 zarch
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e3000000000c msg RXE_RRRD "multiply single 64" z900 zarch
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e3000000001c msgf RXE_RRRD "multiply single 64<32" z900 zarch
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ec0000000044 brxhg RIE_RRP "branch relative on index high 64" z900 zarch
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+ec0000000044 jxhg RIE_RRP "branch relative on index high 64" z900 zarch
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ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" z900 zarch
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+ec0000000045 jxleg RIE_RRP "branch relative on index low or equal 64" z900 zarch
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eb0000000044 bxhg RSE_RRRD "branch on index high 64" z900 zarch
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eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" z900 zarch
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eb000000000c srlg RSE_RRRD "shift right single logical 64" z900 zarch
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@@ -462,10 +471,15 @@ eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch
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a702 tmhh RI_RU "test under mask high high" z900 zarch
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a703 tmhl RI_RU "test under mask high low" z900 zarch
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c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch
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+c004 jgnop RIL_0P "nop jump long" z900 esa,zarch
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c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch
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+c004 br*8l RIL_0P "conditional jump long" z900 esa,zarch
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c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch
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+c0f4 brul RIL_0P "unconditional jump long" z900 esa,zarch
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c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch
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+c005 jasl RIL_RP "branch relative and save long" z900 esa,zarch
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a707 brctg RI_RP "branch relative on count 64" z900 zarch
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+a707 jctg RI_RP "branch relative on count 64" z900 zarch
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a709 lghi RI_RI "load halfword immediate 64" z900 zarch
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a70b aghi RI_RI "add halfword immediate 64" z900 zarch
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a70d mghi RI_RI "multiply halfword immediate 64" z900 zarch
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113
SOURCES/gdb-rhbz2012818-ibmz-update-2of5.patch
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113
SOURCES/gdb-rhbz2012818-ibmz-update-2of5.patch
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@ -0,0 +1,113 @@
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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Andreas Krebbel <krebbel@linux.ibm.com>
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Date: Fri, 4 Dec 2020 09:00:43 +0100
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Subject: gdb-rhbz2012818-ibmz-update-2of5.patch
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;; IBM Z: Add risbgz and risbgnz extended mnemonics
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;; (Andreas Krebbel, RHBZ 2012818)
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These two extended mnemonics are documented in the Principles of
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Operations manual but currently not supported by Binutils. They
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provide aliases for already supported instructions with the zero flag
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being set. The flag otherwise is mingled into one of the immediate
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operands what makes asm code much harder to read.
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opcodes/
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* s390-opc.txt: Add risbgz and risbgnz.
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* s390-opc.c (U6_26): New operand type.
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(INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
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mask.
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gas/
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* testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
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* testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
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* testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
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* testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
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diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
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--- a/opcodes/s390-opc.c
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+++ b/opcodes/s390-opc.c
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@@ -218,32 +218,34 @@ const struct s390_operand s390_operands[] =
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{ 8, 8, 0 },
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#define U8_16 68 /* 8 bit unsigned value starting at 16 */
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{ 8, 16, 0 },
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-#define U8_24 69 /* 8 bit unsigned value starting at 24 */
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+#define U6_26 69 /* 6 bit unsigned value starting at 26 */
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+ { 6, 26, 0 },
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+#define U8_24 70 /* 8 bit unsigned value starting at 24 */
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{ 8, 24, 0 },
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-#define U8_28 70 /* 8 bit unsigned value starting at 28 */
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+#define U8_28 71 /* 8 bit unsigned value starting at 28 */
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{ 8, 28, 0 },
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-#define U8_32 71 /* 8 bit unsigned value starting at 32 */
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+#define U8_32 72 /* 8 bit unsigned value starting at 32 */
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{ 8, 32, 0 },
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-#define U12_16 72 /* 12 bit unsigned value starting at 16 */
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+#define U12_16 73 /* 12 bit unsigned value starting at 16 */
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{ 12, 16, 0 },
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-#define U16_16 73 /* 16 bit unsigned value starting at 16 */
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+#define U16_16 74 /* 16 bit unsigned value starting at 16 */
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{ 16, 16, 0 },
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-#define U16_32 74 /* 16 bit unsigned value starting at 32 */
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+#define U16_32 75 /* 16 bit unsigned value starting at 32 */
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{ 16, 32, 0 },
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-#define U32_16 75 /* 32 bit unsigned value starting at 16 */
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+#define U32_16 76 /* 32 bit unsigned value starting at 16 */
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{ 32, 16, 0 },
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/* PC-relative address operands. */
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-#define J12_12 76 /* 12 bit PC relative offset at 12 */
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+#define J12_12 77 /* 12 bit PC relative offset at 12 */
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{ 12, 12, S390_OPERAND_PCREL },
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-#define J16_16 77 /* 16 bit PC relative offset at 16 */
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+#define J16_16 78 /* 16 bit PC relative offset at 16 */
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{ 16, 16, S390_OPERAND_PCREL },
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-#define J16_32 78 /* 16 bit PC relative offset at 32 */
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+#define J16_32 79 /* 16 bit PC relative offset at 32 */
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{ 16, 32, S390_OPERAND_PCREL },
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-#define J24_24 79 /* 24 bit PC relative offset at 24 */
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+#define J24_24 80 /* 24 bit PC relative offset at 24 */
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{ 24, 24, S390_OPERAND_PCREL },
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-#define J32_16 80 /* 32 bit PC relative offset at 16 */
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+#define J32_16 81 /* 32 bit PC relative offset at 16 */
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{ 32, 16, S390_OPERAND_PCREL },
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};
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@@ -313,6 +315,7 @@ const struct s390_operand s390_operands[] =
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#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
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#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
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#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
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+#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
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#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
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#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
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#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
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@@ -534,6 +537,7 @@ const struct s390_operand s390_operands[] =
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#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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+#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
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#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
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--- a/opcodes/s390-opc.txt
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+++ b/opcodes/s390-opc.txt
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@@ -970,6 +970,7 @@ ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
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ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
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ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
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ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
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+ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch
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c40f strl RIL_RP "store relative long (32)" z10 zarch
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c40b stgrl RIL_RP "store relative long (64)" z10 zarch
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c407 sthrl RIL_RP "store halfword relative long" z10 zarch
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@@ -1153,6 +1154,7 @@ eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zar
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eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
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+ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch
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ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
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ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
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ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch
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84
SOURCES/gdb-rhbz2012818-ibmz-update-3of5.patch
Normal file
84
SOURCES/gdb-rhbz2012818-ibmz-update-3of5.patch
Normal file
@ -0,0 +1,84 @@
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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Andreas Krebbel <krebbel@linux.ibm.com>
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Date: Mon, 15 Feb 2021 14:20:00 +0100
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Subject: gdb-rhbz2012818-ibmz-update-3of5.patch
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;; IBM Z: Implement instruction set extensions
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;; (Andreas Krebbel, RHBZ 2012818)
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opcodes/
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* s390-mkopc.c (main): Accept arch14 as cpu string.
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* s390-opc.txt: Add new arch14 instructions.
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include/
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* opcode/s390.h (enum s390_opcode_cpu_val): Add
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S390_OPCODE_ARCH14.
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gas/
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* config/tc-s390.c (s390_parse_cpu): New entry for arch14.
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* doc/c-s390.texi: Document arch14 march option.
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* testsuite/gas/s390/s390.exp: Run the arch14 related tests.
|
||||||
|
* testsuite/gas/s390/zarch-arch14.d: New test.
|
||||||
|
* testsuite/gas/s390/zarch-arch14.s: New test.
|
||||||
|
|
||||||
|
diff --git a/include/opcode/s390.h b/include/opcode/s390.h
|
||||||
|
--- a/include/opcode/s390.h
|
||||||
|
+++ b/include/opcode/s390.h
|
||||||
|
@@ -44,6 +44,7 @@ enum s390_opcode_cpu_val
|
||||||
|
S390_OPCODE_Z13,
|
||||||
|
S390_OPCODE_ARCH12,
|
||||||
|
S390_OPCODE_ARCH13,
|
||||||
|
+ S390_OPCODE_ARCH14,
|
||||||
|
S390_OPCODE_MAXCPU
|
||||||
|
};
|
||||||
|
|
||||||
|
diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
|
||||||
|
--- a/opcodes/s390-mkopc.c
|
||||||
|
+++ b/opcodes/s390-mkopc.c
|
||||||
|
@@ -379,6 +379,8 @@ main (void)
|
||||||
|
min_cpu = S390_OPCODE_ARCH12;
|
||||||
|
else if (strcmp (cpu_string, "arch13") == 0)
|
||||||
|
min_cpu = S390_OPCODE_ARCH13;
|
||||||
|
+ else if (strcmp (cpu_string, "arch14") == 0)
|
||||||
|
+ min_cpu = S390_OPCODE_ARCH14;
|
||||||
|
else {
|
||||||
|
fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
|
||||||
|
exit (1);
|
||||||
|
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
|
||||||
|
--- a/opcodes/s390-opc.txt
|
||||||
|
+++ b/opcodes/s390-opc.txt
|
||||||
|
@@ -2021,3 +2021,31 @@ e60000000052 vcvbg VRR_RV0UU "vector convert to binary 64 bit" arch13 zarch optp
|
||||||
|
# Message Security Assist Extension 9
|
||||||
|
|
||||||
|
b93a kdsa RRE_RR "compute digital signature authentication" arch13 zarch
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+# arch14 instructions
|
||||||
|
+
|
||||||
|
+e60000000074 vschp VRR_VVV0U0U " " arch14 zarch
|
||||||
|
+e60000002074 vschsp VRR_VVV0U0 " " arch14 zarch
|
||||||
|
+e60000003074 vschdp VRR_VVV0U0 " " arch14 zarch
|
||||||
|
+e60000004074 vschxp VRR_VVV0U0 " " arch14 zarch
|
||||||
|
+e6000000007c vscshp VRR_VVV " " arch14 zarch
|
||||||
|
+e6000000007d vcsph VRR_VVV0U0 " " arch14 zarch
|
||||||
|
+e60000000051 vclzdp VRR_VV0U2 " " arch14 zarch
|
||||||
|
+e60000000070 vpkzr VRI_VVV0UU2 " " arch14 zarch
|
||||||
|
+e60000000072 vsrpr VRI_VVV0UU2 " " arch14 zarch
|
||||||
|
+e60000000054 vupkzh VRR_VV0U2 " " arch14 zarch
|
||||||
|
+e6000000005c vupkzl VRR_VV0U2 " " arch14 zarch
|
||||||
|
+
|
||||||
|
+b93b nnpa RRE_00 " " arch14 zarch
|
||||||
|
+e60000000056 vclfnh VRR_VV0UU2 " " arch14 zarch
|
||||||
|
+e6000000005e vclfnl VRR_VV0UU2 " " arch14 zarch
|
||||||
|
+e60000000075 vcrnf VRR_VVV0UU " " arch14 zarch
|
||||||
|
+e6000000005d vcfn VRR_VV0UU2 " " arch14 zarch
|
||||||
|
+e60000000055 vcnf VRR_VV0UU2 " " arch14 zarch
|
||||||
|
+
|
||||||
|
+b98B rdp RRF_RURR2 " " arch14 zarch optparm
|
||||||
|
+
|
||||||
|
+eb0000000071 lpswey SIY_URD " " arch14 zarch
|
||||||
|
+b200 lbear S_RD " " arch14 zarch
|
||||||
|
+b201 stbear S_RD " " arch14 zarch
|
||||||
50
SOURCES/gdb-rhbz2012818-ibmz-update-4of5.patch
Normal file
50
SOURCES/gdb-rhbz2012818-ibmz-update-4of5.patch
Normal file
@ -0,0 +1,50 @@
|
|||||||
|
From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
|
||||||
|
From: Andreas Krebbel <krebbel@linux.ibm.com>
|
||||||
|
Date: Wed, 4 Aug 2021 16:51:36 +0200
|
||||||
|
Subject: gdb-rhbz2012818-ibmz-update-4of5.patch
|
||||||
|
|
||||||
|
;; IBM Z: Remove lpswey parameter
|
||||||
|
;; (Andreas Krebbel, RHBZ 2012818)
|
||||||
|
|
||||||
|
opcodes/
|
||||||
|
* s390-opc.c (INSTR_SIY_RD): New instruction format.
|
||||||
|
(MASK_SIY_RD): New instruction mask.
|
||||||
|
* s390-opc.txt: Change instruction format of lpswey to SIY_RD.
|
||||||
|
|
||||||
|
gas/
|
||||||
|
* testsuite/gas/s390/zarch-arch14.d: Remove last operand of
|
||||||
|
lpswey.
|
||||||
|
* testsuite/gas/s390/zarch-arch14.s: Likewise.
|
||||||
|
|
||||||
|
(cherry picked from commit a164bbda300d1da6f97bfa14ba7fa22475e61d17)
|
||||||
|
|
||||||
|
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
|
||||||
|
--- a/opcodes/s390-opc.c
|
||||||
|
+++ b/opcodes/s390-opc.c
|
||||||
|
@@ -442,6 +442,7 @@ const struct s390_operand s390_operands[] =
|
||||||
|
#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
|
||||||
|
#define INSTR_SI_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
|
||||||
|
#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
|
||||||
|
+#define INSTR_SIY_RD 6, { D20_20,B_16,0,0,0,0 } /* e.g. lpswey*/
|
||||||
|
#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
|
||||||
|
#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */
|
||||||
|
#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */
|
||||||
|
@@ -664,6 +665,7 @@ const struct s390_operand s390_operands[] =
|
||||||
|
#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||||
|
#define MASK_SI_RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||||
|
#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||||
|
+#define MASK_SIY_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0xff }
|
||||||
|
#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
||||||
|
#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
||||||
|
#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
||||||
|
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
|
||||||
|
--- a/opcodes/s390-opc.txt
|
||||||
|
+++ b/opcodes/s390-opc.txt
|
||||||
|
@@ -2046,6 +2046,6 @@ e60000000055 vcnf VRR_VV0UU2 " " arch14 zarch
|
||||||
|
|
||||||
|
b98B rdp RRF_RURR2 " " arch14 zarch optparm
|
||||||
|
|
||||||
|
-eb0000000071 lpswey SIY_URD " " arch14 zarch
|
||||||
|
+eb0000000071 lpswey SIY_RD " " arch14 zarch
|
||||||
|
b200 lbear S_RD " " arch14 zarch
|
||||||
|
b201 stbear S_RD " " arch14 zarch
|
||||||
28
SOURCES/gdb-rhbz2012818-ibmz-update-5of5.patch
Normal file
28
SOURCES/gdb-rhbz2012818-ibmz-update-5of5.patch
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
|
||||||
|
From: Andreas Krebbel <krebbel@linux.ibm.com>
|
||||||
|
Date: Wed, 7 Jul 2021 14:05:00 +0200
|
||||||
|
Subject: gdb-rhbz2012818-ibmz-update-5of5.patch
|
||||||
|
|
||||||
|
;; IBM Z: Add another arch14 instruction
|
||||||
|
;; (Andreas Krebbel, RHBZ 2012818)
|
||||||
|
|
||||||
|
opcodes/
|
||||||
|
|
||||||
|
* opcodes/s390-opc.txt: Add qpaci.
|
||||||
|
|
||||||
|
gas/
|
||||||
|
|
||||||
|
* testsuite/gas/s390/zarch-arch14.d: Add qpaci.
|
||||||
|
* testsuite/gas/s390/zarch-arch14.s: Add qpaci.
|
||||||
|
|
||||||
|
(cherry picked from commit e4cc3b47ec2c4bdb1892db7e9759f90576742f31)
|
||||||
|
|
||||||
|
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
|
||||||
|
--- a/opcodes/s390-opc.txt
|
||||||
|
+++ b/opcodes/s390-opc.txt
|
||||||
|
@@ -2049,3 +2049,5 @@ b98B rdp RRF_RURR2 " " arch14 zarch optparm
|
||||||
|
eb0000000071 lpswey SIY_RD " " arch14 zarch
|
||||||
|
b200 lbear S_RD " " arch14 zarch
|
||||||
|
b201 stbear S_RD " " arch14 zarch
|
||||||
|
+
|
||||||
|
+b28f qpaci S_RD " " arch14 zarch
|
||||||
@ -26,7 +26,7 @@ Version: 8.2
|
|||||||
|
|
||||||
# The release always contains a leading reserved number, start it at 1.
|
# The release always contains a leading reserved number, start it at 1.
|
||||||
# `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing.
|
# `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing.
|
||||||
Release: 16%{?dist}
|
Release: 17%{?dist}
|
||||||
|
|
||||||
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ and GPLv2+ with exceptions and GPL+ and LGPLv2+ and LGPLv3+ and BSD and Public Domain and GFDL
|
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ and GPLv2+ with exceptions and GPL+ and LGPLv2+ and LGPLv3+ and BSD and Public Domain and GFDL
|
||||||
Group: Development/Debuggers
|
Group: Development/Debuggers
|
||||||
@ -1062,6 +1062,10 @@ fi
|
|||||||
%endif
|
%endif
|
||||||
|
|
||||||
%changelog
|
%changelog
|
||||||
|
* Mon Nov 1 2021 Keith Seitz <keiths@redhat.com> - 8.2-17.el8
|
||||||
|
- Backport IBM arch14 updates.
|
||||||
|
(Andreas Krebbel, RHBZ 2012818)
|
||||||
|
|
||||||
* Wed Jul 14 2021 Keith Seitz <keiths@redhat.com> - 8.2-16.el8
|
* Wed Jul 14 2021 Keith Seitz <keiths@redhat.com> - 8.2-16.el8
|
||||||
- Backport "Fix segfault with nameless fortran modules."
|
- Backport "Fix segfault with nameless fortran modules."
|
||||||
(Bernhard Heckel, RH BZ 1934673)
|
(Bernhard Heckel, RH BZ 1934673)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user