diff --git a/SOURCES/_gdb.spec.Patch.include b/SOURCES/_gdb.spec.Patch.include index f1c921d..baf1520 100644 --- a/SOURCES/_gdb.spec.Patch.include +++ b/SOURCES/_gdb.spec.Patch.include @@ -231,3 +231,51 @@ Patch054: gdb-rhel-13298-inferior-funcall-bp-condition-5-of-5.patch #(Andrew Burgess, RHEL-19390) Patch055: gdb-rhel-19390-pc-not-saved.patch +# Backkport "s390: Make operand table indices relative to each other" +# (Jens Remus, RHEL-86801) +Patch056: gdb-rhel-86801-binutils-z17-update-1of12.patch + +# Backkport "s390: Align optional operand definition to specs" +# (Jens Remus, RHEL-86801) +Patch057: gdb-rhel-86801-binutils-z17-update-2of12.patch + +# Backkport "s390: Add missing extended mnemonics" +# (Jens Remus, RHEL-86801) +Patch058: gdb-rhel-86801-binutils-z17-update-3of12.patch + +# Backkport "s390: Correct prno instruction name" +# (Jens Remus, RHEL-86801) +Patch059: gdb-rhel-86801-binutils-z17-update-4of12.patch + +# Backkport "Fix building for the s390 target with clang" +# (Nick Clifton, RHEL-86801) +Patch060: gdb-rhel-86801-binutils-z17-update-5of12.patch + +# Backkport "s390: Align letter case of instruction descriptions" +# (Jens Remus, RHEL-86801) +Patch061: gdb-rhel-86801-binutils-z17-update-6of12.patch + +# Backkport "s390: Provide IBM z16 (arch14) instruction descriptions" +# (Jens Remus, RHEL-86801) +Patch062: gdb-rhel-86801-binutils-z17-update-7of12.patch + +# Backkport "s390: Align opcodes to lower-case" +# (Jens Remus, RHEL-86801) +Patch063: gdb-rhel-86801-binutils-z17-update-8of12.patch + +# Backkport "s390: Simplify (dis)assembly of insn operands with const bits" +# (Jens Remus, RHEL-86801) +Patch064: gdb-rhel-86801-binutils-z17-update-9of12.patch + +# Backkport "s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints" +# (Jens Remus, RHEL-86801) +Patch065: gdb-rhel-86801-binutils-z17-update-10of12.patch + +# Backkport "s390: Add arch15 instructions" +# (Andreas Krebbel, RHEL-86801) +Patch066: gdb-rhel-86801-binutils-z17-update-11of12.patch + +# Backkport "s390: Add support for z17 as CPU name" +# (Jens Remus, RHEL-86801) +Patch067: gdb-rhel-86801-binutils-z17-update-12of12.patch + diff --git a/SOURCES/_gdb.spec.patch.include b/SOURCES/_gdb.spec.patch.include index cb3143d..6bc063a 100644 --- a/SOURCES/_gdb.spec.patch.include +++ b/SOURCES/_gdb.spec.patch.include @@ -1,55 +1,67 @@ -%patch001 -p1 -%patch002 -p1 -%patch003 -p1 -%patch004 -p1 -%patch005 -p1 -%patch006 -p1 -%patch007 -p1 -%patch008 -p1 -%patch009 -p1 -%patch010 -p1 -%patch011 -p1 -%patch012 -p1 -%patch013 -p1 -%patch014 -p1 -%patch015 -p1 -%patch016 -p1 -%patch017 -p1 -%patch018 -p1 -%patch019 -p1 -%patch020 -p1 -%patch021 -p1 -%patch022 -p1 -%patch023 -p1 -%patch024 -p1 -%patch025 -p1 -%patch026 -p1 -%patch027 -p1 -%patch028 -p1 -%patch029 -p1 -%patch030 -p1 -%patch031 -p1 -%patch032 -p1 -%patch033 -p1 -%patch034 -p1 -%patch035 -p1 -%patch036 -p1 -%patch037 -p1 -%patch038 -p1 -%patch039 -p1 -%patch040 -p1 -%patch041 -p1 -%patch042 -p1 -%patch043 -p1 -%patch044 -p1 -%patch045 -p1 -%patch046 -p1 -%patch047 -p1 -%patch048 -p1 -%patch049 -p1 -%patch050 -p1 -%patch051 -p1 -%patch052 -p1 -%patch053 -p1 -%patch054 -p1 -%patch055 -p1 +%patch -p1 -P001 +%patch -p1 -P002 +%patch -p1 -P003 +%patch -p1 -P004 +%patch -p1 -P005 +%patch -p1 -P006 +%patch -p1 -P007 +%patch -p1 -P008 +%patch -p1 -P009 +%patch -p1 -P010 +%patch -p1 -P011 +%patch -p1 -P012 +%patch -p1 -P013 +%patch -p1 -P014 +%patch -p1 -P015 +%patch -p1 -P016 +%patch -p1 -P017 +%patch -p1 -P018 +%patch -p1 -P019 +%patch -p1 -P020 +%patch -p1 -P021 +%patch -p1 -P022 +%patch -p1 -P023 +%patch -p1 -P024 +%patch -p1 -P025 +%patch -p1 -P026 +%patch -p1 -P027 +%patch -p1 -P028 +%patch -p1 -P029 +%patch -p1 -P030 +%patch -p1 -P031 +%patch -p1 -P032 +%patch -p1 -P033 +%patch -p1 -P034 +%patch -p1 -P035 +%patch -p1 -P036 +%patch -p1 -P037 +%patch -p1 -P038 +%patch -p1 -P039 +%patch -p1 -P040 +%patch -p1 -P041 +%patch -p1 -P042 +%patch -p1 -P043 +%patch -p1 -P044 +%patch -p1 -P045 +%patch -p1 -P046 +%patch -p1 -P047 +%patch -p1 -P048 +%patch -p1 -P049 +%patch -p1 -P050 +%patch -p1 -P051 +%patch -p1 -P052 +%patch -p1 -P053 +%patch -p1 -P054 +%patch -p1 -P055 +%patch -p1 -P056 +%patch -p1 -P057 +%patch -p1 -P058 +%patch -p1 -P059 +%patch -p1 -P060 +%patch -p1 -P061 +%patch -p1 -P062 +%patch -p1 -P063 +%patch -p1 -P064 +%patch -p1 -P065 +%patch -p1 -P066 +%patch -p1 -P067 diff --git a/SOURCES/gdb-rhbz1149205-catch-syscall-after-fork-test.patch b/SOURCES/gdb-rhbz1149205-catch-syscall-after-fork-test.patch index 63c4051..4af9e95 100644 --- a/SOURCES/gdb-rhbz1149205-catch-syscall-after-fork-test.patch +++ b/SOURCES/gdb-rhbz1149205-catch-syscall-after-fork-test.patch @@ -8,7 +8,6 @@ Subject: gdb-rhbz1149205-catch-syscall-after-fork-test.patch ;;=fedoratest URL: -Message-ID: <1368136582.30058.7.camel@soleil> From: Philippe Waroquiers To: gdb-patches at sourceware dot org diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-10of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-10of12.patch new file mode 100644 index 0000000..e6b6fb4 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-10of12.patch @@ -0,0 +1,103 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-10of12.patch + +;; Backkport "s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints" +;; (Jens Remus, RHEL-86801) + +This leverages commit ("s390: Simplify (dis)assembly of insn operands +with const bits") to relax the operand constraints of the immediate +operand that contains the constant Z- or T-bit of the following extended +mnemonics: +risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt + +Previously those instructions were the only ones where the assembler +on s390 restricted the specification of the subject I3/I4 operand values +exactly according to their specification to an unsigned 6- or 5-bit +unsigned integer. For any other instructions the assembler allows to +specify any operand value allowed by the instruction format, regardless +of whether the instruction specification is more restrictive. + +Allow to specify the subject I3/I4 operand as unsigned 8-bit integer +with the constant operand bits being ORed during assembly. +Relax the instructions subject significant operand bit masks to only +consider the Z/T-bit as significant, so that the instructions get +disassembled as their *z or *t flavor regardless of whether any reserved +bits are set in addition to the Z/T-bit. +Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set +the T-bit in operand I3, as they otherwise get disassembled as their +rnsbgt, rosbgt, and rxsbgt counterpart. + +This aligns GNU Assembler to LLVM Assembler. + +opcodes/ + * s390-opc.c (U6_18, U5_27, U6_26): Remove. + (INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define + as INSTR_RIE_RRUUU while retaining insn fmt mask. + (MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only + Z/T-bit of I3/I4 operand as significant. + +gas/testsuite/ + * gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit. + +Reported-by: Dominik Steenken +Suggested-by: Ulrich Weigand +Signed-off-by: Jens Remus + +diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c +--- a/opcodes/s390-opc.c ++++ b/opcodes/s390-opc.c +@@ -216,15 +216,9 @@ const struct s390_operand s390_operands[] = + { 4, 36, 0 }, + #define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +-#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */ +- { 6, 18, 0 }, +-#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */ ++#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +-#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */ +- { 5, 27, 0 }, +-#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */ +- { 6, 26, 0 }, +-#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */ ++#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, + #define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */ + { 8, 28, 0 }, +@@ -288,7 +282,7 @@ unused_s390_operands_static_asserts (void) + p - pc relative + r - general purpose register + re - gpr extended operand, a valid general purpose register pair +- u - unsigned integer, 4, 6, 8, 16 or 32 bit ++ u - unsigned integer, 4, 8, 16 or 32 bit + m - mode field, 4 bit + 0 - operand skipped. + The order of the letters reflects the layout of the format in +@@ -324,9 +318,9 @@ unused_s390_operands_static_asserts (void) + #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ + #define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ + #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ +-#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */ +-#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */ +-#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */ ++#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */ ++#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */ ++#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */ + #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ + #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ + #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +@@ -551,9 +545,9 @@ unused_s390_operands_static_asserts (void) + #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } + #define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } + #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff } +-#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff } +-#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff } ++#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } ++#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } ++#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff } + #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-11of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-11of12.patch new file mode 100644 index 0000000..a72b568 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-11of12.patch @@ -0,0 +1,244 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Andreas Krebbel +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-11of12.patch + +;; Backkport "s390: Add arch15 instructions" +;; (Andreas Krebbel, RHEL-86801) + +opcodes/ + * s390-mkopc.c (main) Accept arch15 as CPU string. + * s390-opc.txt: Add arch15 instructions. + +include/ + * opcode/s390.h (enum s390_opcode_cpu_val): Add + S390_OPCODE_ARCH15. + +gas/ + * config/tc-s390.c (s390_parse_cpu): New entry for arch15. + * doc/c-s390.texi: Document arch15 march option. + * doc/as.texi: Likewise. + * testsuite/gas/s390/s390.exp: Run the arch15 related tests. + * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 + instructions. + * testsuite/gas/s390/zarch-arch15.s: Likewise. + +Signed-off-by: Andreas Krebbel +Reviewed-by: Jens Remus + +diff --git a/include/opcode/s390.h b/include/opcode/s390.h +--- a/include/opcode/s390.h ++++ b/include/opcode/s390.h +@@ -45,6 +45,7 @@ enum s390_opcode_cpu_val + S390_OPCODE_ARCH12, + S390_OPCODE_ARCH13, + S390_OPCODE_ARCH14, ++ S390_OPCODE_ARCH15, + S390_OPCODE_MAXCPU + }; + +diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c +--- a/opcodes/s390-mkopc.c ++++ b/opcodes/s390-mkopc.c +@@ -384,6 +384,8 @@ main (void) + else if (strcmp (cpu_string, "z16") == 0 + || strcmp (cpu_string, "arch14") == 0) + min_cpu = S390_OPCODE_ARCH14; ++ else if (strcmp (cpu_string, "arch15") == 0) ++ min_cpu = S390_OPCODE_ARCH15; + else { + fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); + exit (1); +diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c +--- a/opcodes/s390-opc.c ++++ b/opcodes/s390-opc.c +@@ -228,7 +228,9 @@ const struct s390_operand s390_operands[] = + { 12, 16, 0 }, + #define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +-#define U16_32 (U16_16 + 1) /* 16 bit unsigned value starting at 32 */ ++#define U16_20 (U16_16 + 1) /* 16 bit unsigned value starting at 20 */ ++ { 16, 20, 0 }, ++#define U16_32 (U16_20 + 1) /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, + #define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, +@@ -484,6 +486,8 @@ unused_s390_operands_static_asserts (void) + #define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ + #define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */ + #define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */ ++#define INSTR_VRI_VV0UU 6, { V_8,V_12,U8_28,U4_24,0,0 } /* e.g. vcvdq */ ++#define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */ + #define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ + #define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ + #define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */ +@@ -494,10 +498,10 @@ unused_s390_operands_static_asserts (void) + #define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ + #define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ + #define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */ +-#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ + #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ + #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ + #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ ++#define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */ + #define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/ + #define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/ + #define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/ +@@ -523,6 +527,9 @@ unused_s390_operands_static_asserts (void) + #define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ + #define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ + #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ ++#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ ++#define INSTR_VRR_0V0U 6, { V_12,U16_20,0,0,0,0 } /* e.g. vtp */ ++#define INSTR_VRR_0VVU 6, { V_12,V_16,U16_20,0,0,0 } /* e.g. vtz */ + #define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ + #define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ + #define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */ +@@ -711,6 +718,8 @@ unused_s390_operands_static_asserts (void) + #define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } ++#define MASK_VRI_VV0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } ++#define MASK_VRI_VVV0UV { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } + #define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } + #define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } + #define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +@@ -721,10 +730,10 @@ unused_s390_operands_static_asserts (void) + #define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } + #define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } +-#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } + #define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } + #define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } + #define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } ++#define MASK_VRR_VVV0U02 { 0xff, 0x00, 0x0f, 0xf0, 0xf0, 0xff } + #define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } + #define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } + #define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } +@@ -750,6 +759,9 @@ unused_s390_operands_static_asserts (void) + #define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } + #define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } + #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } ++#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } ++#define MASK_VRR_0V0U { 0xff, 0xf0, 0xf0, 0x00, 0x00, 0xff } ++#define MASK_VRR_0VVU { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } + #define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } + #define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -2072,3 +2072,113 @@ b201 stbear S_RD "store bear" arch14 zarch + # Processor-Activity-Instrumentation Facility + + b28f qpaci S_RD "query processor activity counter information" arch14 zarch ++ ++ ++# arch15 instructions ++ ++e70000000089 vblend VRR_VVVU0V " " arch15 zarch ++e70000000089 vblendb VRR_VVV0V " " arch15 zarch ++e70001000089 vblendh VRR_VVV0V " " arch15 zarch ++e70002000089 vblendf VRR_VVV0V " " arch15 zarch ++e70003000089 vblendg VRR_VVV0V " " arch15 zarch ++e70004000089 vblendq VRR_VVV0V " " arch15 zarch ++ ++e70000000088 veval VRI_VVV0UV " " arch15 zarch ++ ++e70000000054 vgem VRR_VV0U " " arch15 zarch ++e70000000054 vgemb VRR_VV " " arch15 zarch ++e70000001054 vgemh VRR_VV " " arch15 zarch ++e70000002054 vgemf VRR_VV " " arch15 zarch ++e70000003054 vgemg VRR_VV " " arch15 zarch ++e70000004054 vgemq VRR_VV " " arch15 zarch ++ ++e700000030d7 vuphg VRR_VV " " arch15 zarch ++e700000030d5 vuplhg VRR_VV " " arch15 zarch ++e700000030d6 vuplg VRR_VV " " arch15 zarch ++e700000030d4 vupllg VRR_VV " " arch15 zarch ++ ++e700000040f2 vavgq VRR_VVV " " arch15 zarch ++e700000040f0 vavglq VRR_VVV " " arch15 zarch ++e700000040db vecq VRR_VV " " arch15 zarch ++e700000040d9 veclq VRR_VV " " arch15 zarch ++e700000040f8 vceqq VRR_VVV " " arch15 zarch ++e700001040f8 vceqqs VRR_VVV " " arch15 zarch ++e700000040fb vchq VRR_VVV " " arch15 zarch ++e700001040fb vchqs VRR_VVV " " arch15 zarch ++e700000040f9 vchlq VRR_VVV " " arch15 zarch ++e700001040f9 vchlqs VRR_VVV " " arch15 zarch ++e70000004053 vclzq VRR_VV " " arch15 zarch ++e70000004052 vctzq VRR_VV " " arch15 zarch ++e700000040de vlcq VRR_VV " " arch15 zarch ++e700000040df vlpq VRR_VV " " arch15 zarch ++e700000040ff vmxq VRR_VVV " " arch15 zarch ++e700000040fd vmxlq VRR_VVV " " arch15 zarch ++e700000040fe vmnq VRR_VVV " " arch15 zarch ++e700000040fc vmnlq VRR_VVV " " arch15 zarch ++e700030000aa vmalg VRR_VVV0V " " arch15 zarch ++e700040000aa vmalq VRR_VVV0V " " arch15 zarch ++e700030000ab vmahg VRR_VVV0V " " arch15 zarch ++e700040000ab vmahq VRR_VVV0V " " arch15 zarch ++e700030000a9 vmalhg VRR_VVV0V " " arch15 zarch ++e700040000a9 vmalhq VRR_VVV0V " " arch15 zarch ++e700030000ae vmaeg VRR_VVV0V " " arch15 zarch ++e700030000ac vmaleg VRR_VVV0V " " arch15 zarch ++e700030000af vmaog VRR_VVV0V " " arch15 zarch ++e700030000ad vmalog VRR_VVV0V " " arch15 zarch ++e700000030a3 vmhg VRR_VVV " " arch15 zarch ++e700000040a3 vmhq VRR_VVV " " arch15 zarch ++e700000030a1 vmlhg VRR_VVV " " arch15 zarch ++e700000040a1 vmlhq VRR_VVV " " arch15 zarch ++e700000030a2 vmlg VRR_VVV " " arch15 zarch ++e700000040a2 vmlq VRR_VVV " " arch15 zarch ++e700000030a6 vmeg VRR_VVV " " arch15 zarch ++e700000030a4 vmleg VRR_VVV " " arch15 zarch ++e700000030a7 vmog VRR_VVV " " arch15 zarch ++e700000030a5 vmlog VRR_VVV " " arch15 zarch ++ ++e700000000b2 vd VRR_VVV0UU " " arch15 zarch ++e700000020b2 vdf VRR_VVV0U02 " " arch15 zarch ++e700000030b2 vdg VRR_VVV0U02 " " arch15 zarch ++e700000040b2 vdq VRR_VVV0U02 " " arch15 zarch ++ ++e700000000b0 vdl VRR_VVV0UU " " arch15 zarch ++e700000020b0 vdlf VRR_VVV0U02 " " arch15 zarch ++e700000030b0 vdlg VRR_VVV0U02 " " arch15 zarch ++e700000040b0 vdlq VRR_VVV0U02 " " arch15 zarch ++ ++e700000000b3 vr VRR_VVV0UU " " arch15 zarch ++e700000020b3 vrf VRR_VVV0U02 " " arch15 zarch ++e700000030b3 vrg VRR_VVV0U02 " " arch15 zarch ++e700000040b3 vrq VRR_VVV0U02 " " arch15 zarch ++ ++e700000000b1 vrl VRR_VVV0UU " " arch15 zarch ++e700000020b1 vrlf VRR_VVV0U02 " " arch15 zarch ++e700000030b1 vrlg VRR_VVV0U02 " " arch15 zarch ++e700000040b1 vrlq VRR_VVV0U02 " " arch15 zarch ++ ++b968 clzg RRE_RR " " arch15 zarch ++b969 ctzg RRE_RR " " arch15 zarch ++ ++e30000000060 lxab RXY_RRRD " " arch15 zarch ++e30000000062 lxah RXY_RRRD " " arch15 zarch ++e30000000064 lxaf RXY_RRRD " " arch15 zarch ++e30000000066 lxag RXY_RRRD " " arch15 zarch ++e30000000068 lxaq RXY_RRRD " " arch15 zarch ++ ++e30000000061 llxab RXY_RRRD " " arch15 zarch ++e30000000063 llxah RXY_RRRD " " arch15 zarch ++e30000000065 llxaf RXY_RRRD " " arch15 zarch ++e30000000067 llxag RXY_RRRD " " arch15 zarch ++e30000000069 llxaq RXY_RRRD " " arch15 zarch ++ ++b96c bextg RRF_R0RR2 " " arch15 zarch ++b96d bdepg RRF_R0RR2 " " arch15 zarch ++ ++b93e kimd RRF_U0RR " " arch15 zarch optparm ++b93f klmd RRF_U0RR " " arch15 zarch optparm ++ ++e6000000004e vcvbq VRR_VV0U2 " " arch15 zarch ++e6000000004a vcvdq VRI_VV0UU " " arch15 zarch ++ ++e6000000005f vtp VRR_0V0U " " arch15 zarch optparm ++e6000000007f vtz VRR_0VVU " " arch15 zarch diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-12of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-12of12.patch new file mode 100644 index 0000000..9fba933 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-12of12.patch @@ -0,0 +1,38 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Wed, 9 Apr 2025 08:59:24 +0200 +Subject: gdb-rhel-86801-binutils-z17-update-12of12.patch + +;; Backkport "s390: Add support for z17 as CPU name" +;; (Jens Remus, RHEL-86801) + +So far IBM z17 was identified as arch15. Add the real name, as it has +been announced. [1] + +[1]: IBM z17 announcement letter, AD25-0015, + https://www.ibm.com/docs/en/announcements/z17-makes-more-possible + +gas/ + * config/tc-s390.c (s390_parse_cpu): Add z17 as alternate CPU + name for arch15. + * doc/c-s390.texi: Likewise. + * doc/as.texi: Likewise. + +opcodes/ + * s390-mkopc.c (main): Add z17 as alternate CPU name for arch15. + +Signed-off-by: Jens Remus + +diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c +--- a/opcodes/s390-mkopc.c ++++ b/opcodes/s390-mkopc.c +@@ -384,7 +384,8 @@ main (void) + else if (strcmp (cpu_string, "z16") == 0 + || strcmp (cpu_string, "arch14") == 0) + min_cpu = S390_OPCODE_ARCH14; +- else if (strcmp (cpu_string, "arch15") == 0) ++ else if (strcmp (cpu_string, "z17") == 0 ++ || strcmp (cpu_string, "arch15") == 0) + min_cpu = S390_OPCODE_ARCH15; + else { + fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-1of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-1of12.patch new file mode 100644 index 0000000..84d9a1d --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-1of12.patch @@ -0,0 +1,343 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:21 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-1of12.patch + +;; Backkport "s390: Make operand table indices relative to each other" +;; (Jens Remus, RHEL-86801) + +This is a purely mechanical change. It allows subsequent insertions into +the operands table without having to renumber all operand indices. + +The only differences in the resulting ELF object are in the .debug_info +section. This has been confirmed by diffing the following xxd and readelf +output: + +xxd s390-opc.o +readelf -aW -x .text -x .data -x .bss -x .rodata -x .debug_info \ + -x .symtab -x .strtab -x .shstrtab --debug-dump s390-opc.o + +opcodes/ + * s390-opc.c: Make operand table indices relative to each other. + +Signed-off-by: Jens Remus +Reviewed-by: Andreas Krebbel + +diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c +--- a/opcodes/s390-opc.c ++++ b/opcodes/s390-opc.c +@@ -34,76 +34,82 @@ + inserting operands into instructions and vice-versa is kept in this + file. */ + ++/* Build-time checks are preferrable over runtime ones. Use this construct ++ in preference where possible. */ ++#define static_assert(e) ((void)sizeof (struct { int _:1 - 2 * !(e); })) ++ ++#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) ++ + /* The operands table. + The fields are bits, shift, insert, extract, flags. */ + + const struct s390_operand s390_operands[] = + { +-#define UNUSED 0 ++#define UNUSED 0 + { 0, 0, 0 }, /* Indicates the end of the operand list */ + + /* General purpose register operands. */ + +-#define R_8 1 /* GPR starting at position 8 */ ++#define R_8 (UNUSED + 1) /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR }, +-#define R_12 2 /* GPR starting at position 12 */ ++#define R_12 (R_8 + 1) /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR }, +-#define R_16 3 /* GPR starting at position 16 */ ++#define R_16 (R_12 + 1) /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR }, +-#define R_20 4 /* GPR starting at position 20 */ ++#define R_20 (R_16 + 1) /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR }, +-#define R_24 5 /* GPR starting at position 24 */ ++#define R_24 (R_20 + 1) /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR }, +-#define R_28 6 /* GPR starting at position 28 */ ++#define R_28 (R_24 + 1) /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +-#define R_32 7 /* GPR starting at position 32 */ ++#define R_32 (R_28 + 1) /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + + /* General purpose register pair operands. */ + +-#define RE_8 8 /* GPR starting at position 8 */ ++#define RE_8 (R_32 + 1) /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_12 9 /* GPR starting at position 12 */ ++#define RE_12 (RE_8 + 1) /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_16 10 /* GPR starting at position 16 */ ++#define RE_16 (RE_12 + 1) /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_20 11 /* GPR starting at position 20 */ ++#define RE_20 (RE_16 + 1) /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_24 12 /* GPR starting at position 24 */ ++#define RE_24 (RE_20 + 1) /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_28 13 /* GPR starting at position 28 */ ++#define RE_28 (RE_24 + 1) /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_32 14 /* GPR starting at position 32 */ ++#define RE_32 (RE_28 + 1) /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, + + /* Floating point register operands. */ + +-#define F_8 15 /* FPR starting at position 8 */ ++#define F_8 (RE_32 + 1) /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR }, +-#define F_12 16 /* FPR starting at position 12 */ ++#define F_12 (F_8 + 1) /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR }, +-#define F_16 17 /* FPR starting at position 16 */ ++#define F_16 (F_12 + 1) /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +-#define F_24 18 /* FPR starting at position 24 */ ++#define F_24 (F_16 + 1) /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR }, +-#define F_28 19 /* FPR starting at position 28 */ ++#define F_28 (F_24 + 1) /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR }, +-#define F_32 20 /* FPR starting at position 32 */ ++#define F_32 (F_28 + 1) /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR }, + + /* Floating point register pair operands. */ + +-#define FE_8 21 /* FPR starting at position 8 */ ++#define FE_8 (F_32 + 1) /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_12 22 /* FPR starting at position 12 */ ++#define FE_12 (FE_8 + 1) /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_16 23 /* FPR starting at position 16 */ ++#define FE_16 (FE_12 + 1) /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_24 24 /* FPR starting at position 24 */ ++#define FE_24 (FE_16 + 1) /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_28 25 /* FPR starting at position 28 */ ++#define FE_28 (FE_24 + 1) /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_32 26 /* FPR starting at position 32 */ ++#define FE_32 (FE_28 + 1) /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, + + /* Vector register operands. */ +@@ -111,145 +117,149 @@ const struct s390_operand s390_operands[] = + /* For each of these operands and additional bit in the RXB operand is + needed. */ + +-#define V_8 27 /* Vector reg. starting at position 8 */ ++#define V_8 (FE_32 + 1) /* Vector reg. starting at position 8 */ + { 4, 8, S390_OPERAND_VR }, +-#define V_12 28 /* Vector reg. starting at position 12 */ ++#define V_12 (V_8 + 1) /* Vector reg. starting at position 12 */ + { 4, 12, S390_OPERAND_VR }, +-#define V_CP16_12 29 /* Vector reg. starting at position 12 */ ++#define V_CP16_12 (V_12 + 1) /* Vector reg. starting at position 12 */ + { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ +-#define V_16 30 /* Vector reg. starting at position 16 */ ++#define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ + { 4, 16, S390_OPERAND_VR }, +-#define V_32 31 /* Vector reg. starting at position 32 */ ++#define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ + { 4, 32, S390_OPERAND_VR }, + + /* Access register operands. */ + +-#define A_8 32 /* Access reg. starting at position 8 */ ++#define A_8 (V_32 + 1) /* Access reg. starting at position 8 */ + { 4, 8, S390_OPERAND_AR }, +-#define A_12 33 /* Access reg. starting at position 12 */ ++#define A_12 (A_8 + 1) /* Access reg. starting at position 12 */ + { 4, 12, S390_OPERAND_AR }, +-#define A_24 34 /* Access reg. starting at position 24 */ ++#define A_24 (A_12 + 1) /* Access reg. starting at position 24 */ + { 4, 24, S390_OPERAND_AR }, +-#define A_28 35 /* Access reg. starting at position 28 */ ++#define A_28 (A_24 + 1) /* Access reg. starting at position 28 */ + { 4, 28, S390_OPERAND_AR }, + + /* Control register operands. */ + +-#define C_8 36 /* Control reg. starting at position 8 */ ++#define C_8 (A_28 + 1) /* Control reg. starting at position 8 */ + { 4, 8, S390_OPERAND_CR }, +-#define C_12 37 /* Control reg. starting at position 12 */ ++#define C_12 (C_8 + 1) /* Control reg. starting at position 12 */ + { 4, 12, S390_OPERAND_CR }, + + /* Base register operands. */ + +-#define B_16 38 /* Base register starting at position 16 */ ++#define B_16 (C_12 + 1) /* Base register starting at position 16 */ + { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, +-#define B_32 39 /* Base register starting at position 32 */ ++#define B_32 (B_16 + 1) /* Base register starting at position 32 */ + { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, + +-#define X_12 40 /* Index register starting at position 12 */ ++#define X_12 (B_32 + 1) /* Index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, + +-#define VX_12 41 /* Vector index register starting at position 12 */ ++#define VX_12 (X_12+1) /* Vector index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, + + /* Address displacement operands. */ + +-#define D_20 42 /* Displacement starting at position 20 */ ++#define D_20 (VX_12 + 1) /* Displacement starting at position 20 */ + { 12, 20, S390_OPERAND_DISP }, +-#define D_36 43 /* Displacement starting at position 36 */ ++#define D_36 (D_20 + 1) /* Displacement starting at position 36 */ + { 12, 36, S390_OPERAND_DISP }, +-#define D20_20 44 /* 20 bit displacement starting at 20 */ ++#define D20_20 (D_36 + 1) /* 20 bit displacement starting at 20 */ + { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, + + /* Length operands. */ + +-#define L4_8 45 /* 4 bit length starting at position 8 */ ++#define L4_8 (D20_20 + 1) /* 4 bit length starting at position 8 */ + { 4, 8, S390_OPERAND_LENGTH }, +-#define L4_12 46 /* 4 bit length starting at position 12 */ ++#define L4_12 (L4_8 + 1) /* 4 bit length starting at position 12 */ + { 4, 12, S390_OPERAND_LENGTH }, +-#define L8_8 47 /* 8 bit length starting at position 8 */ ++#define L8_8 (L4_12 + 1) /* 8 bit length starting at position 8 */ + { 8, 8, S390_OPERAND_LENGTH }, + + /* Signed immediate operands. */ + +-#define I8_8 48 /* 8 bit signed value starting at 8 */ ++#define I8_8 (L8_8 + 1) /* 8 bit signed value starting at 8 */ + { 8, 8, S390_OPERAND_SIGNED }, +-#define I8_32 49 /* 8 bit signed value starting at 32 */ ++#define I8_32 (I8_8 + 1) /* 8 bit signed value starting at 32 */ + { 8, 32, S390_OPERAND_SIGNED }, +-#define I12_12 50 /* 12 bit signed value starting at 12 */ ++#define I12_12 (I8_32 + 1) /* 12 bit signed value starting at 12 */ + { 12, 12, S390_OPERAND_SIGNED }, +-#define I16_16 51 /* 16 bit signed value starting at 16 */ ++#define I16_16 (I12_12 + 1) /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +-#define I16_32 52 /* 16 bit signed value starting at 32 */ ++#define I16_32 (I16_16 + 1) /* 16 bit signed value starting at 32 */ + { 16, 32, S390_OPERAND_SIGNED }, +-#define I24_24 53 /* 24 bit signed value starting at 24 */ ++#define I24_24 (I16_32 + 1) /* 24 bit signed value starting at 24 */ + { 24, 24, S390_OPERAND_SIGNED }, +-#define I32_16 54 /* 32 bit signed value starting at 16 */ ++#define I32_16 (I24_24 + 1) /* 32 bit signed value starting at 16 */ + { 32, 16, S390_OPERAND_SIGNED }, + + /* Unsigned immediate operands. */ + +-#define U4_8 55 /* 4 bit unsigned value starting at 8 */ ++#define U4_8 (I32_16 + 1) /* 4 bit unsigned value starting at 8 */ + { 4, 8, 0 }, +-#define U4_12 56 /* 4 bit unsigned value starting at 12 */ ++#define U4_12 (U4_8 + 1) /* 4 bit unsigned value starting at 12 */ + { 4, 12, 0 }, +-#define U4_16 57 /* 4 bit unsigned value starting at 16 */ ++#define U4_16 (U4_12 + 1) /* 4 bit unsigned value starting at 16 */ + { 4, 16, 0 }, +-#define U4_20 58 /* 4 bit unsigned value starting at 20 */ ++#define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 */ + { 4, 20, 0 }, +-#define U4_24 59 /* 4 bit unsigned value starting at 24 */ ++#define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */ + { 4, 24, 0 }, +-#define U4_OR1_24 60 /* 4 bit unsigned value ORed with 1 */ ++#define U4_OR1_24 (U4_24 + 1) /* 4 bit unsigned value ORed with 1 */ + { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */ +-#define U4_OR2_24 61 /* 4 bit unsigned value ORed with 2 */ ++#define U4_OR2_24 (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */ + { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */ +-#define U4_OR3_24 62 /* 4 bit unsigned value ORed with 3 */ ++#define U4_OR3_24 (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */ + { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */ +-#define U4_28 63 /* 4 bit unsigned value starting at 28 */ ++#define U4_28 (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */ + { 4, 28, 0 }, +-#define U4_OR8_28 64 /* 4 bit unsigned value ORed with 8 */ ++#define U4_OR8_28 (U4_28 + 1) /* 4 bit unsigned value ORed with 8 */ + { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */ +-#define U4_32 65 /* 4 bit unsigned value starting at 32 */ ++#define U4_32 (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */ + { 4, 32, 0 }, +-#define U4_36 66 /* 4 bit unsigned value starting at 36 */ ++#define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */ + { 4, 36, 0 }, +-#define U8_8 67 /* 8 bit unsigned value starting at 8 */ ++#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +-#define U8_16 68 /* 8 bit unsigned value starting at 16 */ ++#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +-#define U6_26 69 /* 6 bit unsigned value starting at 26 */ ++#define U6_26 (U8_16 + 1) /* 6 bit unsigned value starting at 26 */ + { 6, 26, 0 }, +-#define U8_24 70 /* 8 bit unsigned value starting at 24 */ ++#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +-#define U8_28 71 /* 8 bit unsigned value starting at 28 */ ++#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */ + { 8, 28, 0 }, +-#define U8_32 72 /* 8 bit unsigned value starting at 32 */ ++#define U8_32 (U8_28 + 1) /* 8 bit unsigned value starting at 32 */ + { 8, 32, 0 }, +-#define U12_16 73 /* 12 bit unsigned value starting at 16 */ ++#define U12_16 (U8_32 + 1) /* 12 bit unsigned value starting at 16 */ + { 12, 16, 0 }, +-#define U16_16 74 /* 16 bit unsigned value starting at 16 */ ++#define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +-#define U16_32 75 /* 16 bit unsigned value starting at 32 */ ++#define U16_32 (U16_16 + 1) /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, +-#define U32_16 76 /* 32 bit unsigned value starting at 16 */ ++#define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, + + /* PC-relative address operands. */ + +-#define J12_12 77 /* 12 bit PC relative offset at 12 */ ++#define J12_12 (U32_16 + 1) /* 12 bit PC relative offset at 12 */ + { 12, 12, S390_OPERAND_PCREL }, +-#define J16_16 78 /* 16 bit PC relative offset at 16 */ ++#define J16_16 (J12_12 + 1) /* 16 bit PC relative offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +-#define J16_32 79 /* 16 bit PC relative offset at 32 */ ++#define J16_32 (J16_16 + 1) /* 16 bit PC relative offset at 32 */ + { 16, 32, S390_OPERAND_PCREL }, +-#define J24_24 80 /* 24 bit PC relative offset at 24 */ ++#define J24_24 (J16_32 + 1) /* 24 bit PC relative offset at 24 */ + { 24, 24, S390_OPERAND_PCREL }, +-#define J32_16 81 /* 32 bit PC relative offset at 16 */ ++#define J32_16 (J24_24 + 1) /* 32 bit PC relative offset at 16 */ + { 32, 16, S390_OPERAND_PCREL }, + + }; + ++static inline void unused_s390_operands_static_asserts(void) ++{ ++ static_assert(ARRAY_SIZE(s390_operands) - 1 == J32_16); ++} + + /* Macros used to form opcodes. */ + diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-2of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-2of12.patch new file mode 100644 index 0000000..50c77f4 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-2of12.patch @@ -0,0 +1,99 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:21 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-2of12.patch + +;; Backkport "s390: Align optional operand definition to specs" +;; (Jens Remus, RHEL-86801) + +The IBM z/Architecture Principle of Operation [1] specifies the last +operand(s) of some (extended) mnemonics to be optional. Align the +mnemonic definitions in the opcode table according to specification. + +This changes the last operand of the following (extended) mnemonics to +be optional: +risbg, risbgz, risbgn, risbgnz, risbhg, risblg, rnsbg, rosbg, rxsbg + +Note that efpc and sfpc actually have only one operand, but had +erroneously been defined to have two. For backwards compatibility the +wrong RR register format must be retained. Since the superfluous second +operand is defined as optional the instruction can still be coded as +specified. + +[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16, + https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf + +opcodes/ + * s390-opc.txt: Align optional operand definition to + specification. + +testsuite/ + * zarch-z10.s: Add test cases for risbg, risbgz, rnsbg, rosbg, + and rxsbg. + * zarch-z10.d: Likewise. + * zarch-z196.s: Add test cases for risbhg and risblg. + * zarch-z196.d: Likewise. + * zarch-zEC12.s: Add test cases for risbgn and risbgnz. + * zarch-zEC12.d: Likewise. + +Signed-off-by: Jens Remus +Reviewed-by: Andreas Krebbel + +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -305,6 +305,7 @@ b30d debr RRE_FF "divide short bfp" g5 esa,zarch + ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch + b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch + b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch ++# efpc and sfpc have only one operand; retain RR register format for compatibility + b38c efpc RRE_RR "extract fpc" g5 esa,zarch optparm + b342 ltxbr RRE_FEFE "load and test extended bfp" g5 esa,zarch + b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch +@@ -348,6 +349,7 @@ b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch + ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch + b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch + ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch ++# efpc and sfpc have only one operand; retain RR register format for compatibility + b384 sfpc RRE_RR "set fpc" g5 esa,zarch optparm + b299 srnm S_RD "set rounding mode" g5 esa,zarch + b316 sqxbr RRE_FEFE "square root extended bfp" g5 esa,zarch +@@ -966,11 +968,11 @@ c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch + c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch + e30000000036 pfd RXY_URRD "prefetch data" z10 zarch + c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch +-ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch +-ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch +-ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch +-ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch +-ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch ++ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch optparm ++ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch optparm ++ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch optparm ++ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch optparm ++ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch optparm + c40f strl RIL_RP "store relative long (32)" z10 zarch + c40b stgrl RIL_RP "store relative long (64)" z10 zarch + c407 sthrl RIL_RP "store halfword relative long" z10 zarch +@@ -1014,8 +1016,8 @@ e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch + e300000000ca lfh RXY_RRRD "load high" z196 zarch + e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch + e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch +-ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch +-ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch ++ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch optparm ++ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch optparm + e300000000c3 stch RXY_RRRD "store character high" z196 zarch + e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch + e300000000cb stfh RXY_RRRD "store high" z196 zarch +@@ -1153,8 +1155,8 @@ eb0000000023 clt RSY_RURD "compare logical and trap 32 bit reg-mem" zEC12 zarch + eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zarch + eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch + eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch +-ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch +-ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch ++ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch optparm ++ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch optparm + ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch + ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch + ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-3of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-3of12.patch new file mode 100644 index 0000000..37c6ed0 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-3of12.patch @@ -0,0 +1,244 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-3of12.patch + +;; Backkport "s390: Add missing extended mnemonics" +;; (Jens Remus, RHEL-86801) + +Add extended mnemonics specified in the z/Architecture Principles of +Operation [1] and z/Architecture Reference Summary [2], that were +previously missing from the opcode table. + +The following added extended mnemonics are synonyms to a base mnemonic +and therefore disassemble into their base mnemonic: +jc, jcth, lfi, llgfi, llghi + +The following added extended mnemonics are more specific than their base +mnemonic and therefore disassemble into the added extended mnemonic: +risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt + +The following added extended mnemonics are more specific than their base +mnemonic, but disassemble into their base mnemonic due to design +constraints: +notr, notgr + +The missing extended mnemonic jl* conditional jump long flavors cannot +be added, as they would clash with the existing non-standard extended +mnemonic j* conditional jump flavors jle and jlh. The missing extended +mnemonic jlc jump long conditional is not added, as the related jl* +flavors cannot be added. +Note that these missing jl* conditional jump long flavors are already +defined as non-standard jg* flavors instead. While the related missing +extended mnemonic jlc could be added as non-standard jgc instead it is +forgone in favor of not adding further non-standard mnemonics. + +The missing extended mnemonics sllhh, sllhl, slllh, srlhh, srlhl, and +srllh cannot be implemented using the current design, as they require +computed operands. For that reason the following missing extended +mnemonics are not added as well, as they fall into the same category of +instructions that operate on high and low words of registers. They +should better be added together, not to confuse the user, which of those +instructions are currently implemented or not. +lhhr, lhlr, llhfr, llchhr, llchlr, llclhr, llhhhr, llhhlr, llhlhr, +nhhr, nhlr, nlhr, ohhr, ohlr, olhr, xhhr, xhlr, xlhr + +[1] IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16, + https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf +[2] IBM z/Architecture Reference Summary, SA22-7871-11, + https://www.ibm.com/support/pages/sites/default/files/2022-09/SA22-7871-11.pdf + +opcodes/ + * s390-opc.c: Define operand formats R_CP16_28, U6_18, and + U5_27. Define instruction formats RIE_RRUUU3, RIE_RRUUU4, + and RRF_R0RR4. + * s390-opc.txt: Add extended mnemonics jc, jcth, lfi, llgfi, + llghi, notgr, notr, risbhgz, risblgz, rnsbgt, rosbgt, and + rxsbgt. + +gas/ + * config/tc-s390.c: Add support to insert operand for format + R_CP16_28, reusing existing logic for format V_CP16_12. + * testsuite/gas/s390/esa-g5.s: Add test for extended mnemonic + jc. + * testsuite/gas/s390/esa-g5.d: Likewise. + * testsuite/gas/s390/zarch-z900.s: Add test for extended + mnemonic llghi. + * testsuite/gas/s390/zarch-z900.d: Likewise. + * testsuite/gas/s390/zarch-z9-109.s: Add tests for extended + mnemonics lfi and llgfi. + * testsuite/gas/s390/zarch-z9-109.d: Likewise. + * testsuite/gas/s390/zarch-z10.s: Add tests for extended + mnemonics rnsbgt, rosbgt, and rxsbgt. + * testsuite/gas/s390/zarch-z10.d: Likewise. + * testsuite/gas/s390/zarch-z196.s: Add tests for extended + mnemonics jcth, risbhgz, and risblgz. + * testsuite/gas/s390/zarch-z196.d: Likewise. + * testsuite/gas/s390/zarch-arch13.s: Add tests for extended + mnemonics notr and notgr. + * testsuite/gas/s390/zarch-arch13.d: Likewise. + +Signed-off-by: Jens Remus +Reviewed-by: Andreas Krebbel + +diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c +--- a/opcodes/s390-opc.c ++++ b/opcodes/s390-opc.c +@@ -62,7 +62,9 @@ const struct s390_operand s390_operands[] = + { 4, 24, S390_OPERAND_GPR }, + #define R_28 (R_24 + 1) /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +-#define R_32 (R_28 + 1) /* GPR starting at position 32 */ ++#define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */ ++ { 4, 28, S390_OPERAND_GPR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ ++#define R_32 (R_CP16_28+1) /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + + /* General purpose register pair operands. */ +@@ -222,9 +224,13 @@ const struct s390_operand s390_operands[] = + { 4, 36, 0 }, + #define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +-#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ ++#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */ ++ { 6, 18, 0 }, ++#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +-#define U6_26 (U8_16 + 1) /* 6 bit unsigned value starting at 26 */ ++#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */ ++ { 5, 27, 0 }, ++#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */ + { 6, 26, 0 }, + #define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +@@ -289,7 +295,7 @@ static inline void unused_s390_operands_static_asserts(void) + p - pc relative + r - general purpose register + re - gpr extended operand, a valid general purpose register pair +- u - unsigned integer, 4, 8, 16 or 32 bit ++ u - unsigned integer, 4, 6, 8, 16 or 32 bit + m - mode field, 4 bit + 0 - operand skipped. + The order of the letters reflects the layout of the format in +@@ -325,7 +331,9 @@ static inline void unused_s390_operands_static_asserts(void) + #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ + #define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ + #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ +-#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */ ++#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */ ++#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */ ++#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */ + #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ + #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ + #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +@@ -374,6 +382,7 @@ static inline void unused_s390_operands_static_asserts(void) + #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ + #define INSTR_RRF_R0RER 4, { RE_24,R_28,R_16,0,0,0 } /* e.g. mgrk */ + #define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */ ++#define INSTR_RRF_R0RR4 4, { R_24,R_CP16_28,0,0,0,0 } /* e.g. notr */ + #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ + #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ + #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +@@ -550,6 +559,8 @@ static inline void unused_s390_operands_static_asserts(void) + #define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } + #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff } ++#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff } ++#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff } + #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +@@ -598,6 +609,7 @@ static inline void unused_s390_operands_static_asserts(void) + #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RRF_R0RER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_R0RR4 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } + #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } + #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -272,6 +272,7 @@ a701 tml RI_RU "test under mask low" g5 esa,zarch + 4700 nop RX_0RRD "no operation" g5 esa,zarch optparm + 4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch + 47f0 b RX_0RRD "unconditional branch" g5 esa,zarch ++a704 jc RI_UP "conditional jump" g5 esa,zarch + a704 jnop RI_0P "nop jump" g5 esa,zarch + a704 j*8 RI_0P "conditional jump" g5 esa,zarch + a704 br*8 RI_0P "conditional jump" g5 esa,zarch +@@ -473,8 +474,10 @@ eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch + a702 tmhh RI_RU "test under mask high high" z900 zarch + a703 tmhl RI_RU "test under mask high low" z900 zarch + c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch ++# jlc omitted due to missing jl* (see jl*8) and not added as non-standard jgc + c004 jgnop RIL_0P "nop jump long" z900 esa,zarch + c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch ++# jl*8 omitted due to clash with non-standard j*8 flavors jle and jlh; exists as non-standard jg*8 instead + c004 br*8l RIL_0P "conditional jump long" z900 esa,zarch + c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch + c0f4 brul RIL_0P "unconditional jump long" z900 esa,zarch +@@ -523,6 +526,7 @@ a50c llihh RI_RU "load logical immediate high high" z900 zarch + a50d llihl RI_RU "load logical immediate high low" z900 zarch + a50e llilh RI_RU "load logical immediate low high" z900 zarch + a50f llill RI_RU "load logical immediate low low" z900 zarch ++a50f llghi RI_RU "load logical immediate" z900 zarch + b2b1 stfl S_RD "store facility list" z900 esa,zarch + b2b2 lpswe S_RD "load psw extended" z900 zarch + b90d dsgr RRE_RER "divide single 64" z900 zarch +@@ -750,6 +754,7 @@ c006 xihf RIL_RU "exclusive or immediate high" z9-109 zarch + c007 xilf RIL_RU "exclusive or immediate low" z9-109 zarch + c008 iihf RIL_RU "insert immediate high" z9-109 zarch + c009 iilf RIL_RU "insert immediate low" z9-109 zarch ++c009 lfi RIL_RU "insert immediate 32" z9-109 zarch + # z9-109 misc instruction + b983 flogr RRE_RER "find leftmost one" z9-109 zarch + e30000000012 lt RXY_RRRD "load and test 32" z9-109 zarch +@@ -767,6 +772,7 @@ b995 llhr RRE_RR "load logical halfword 32" z9-109 zarch + b985 llghr RRE_RR "load logical halfword 64" z9-109 zarch + c00e llihf RIL_RU "load logical immediate high" z9-109 zarch + c00f llilf RIL_RU "load logical immediate low" z9-109 zarch ++c00f llgfi RIL_RU "load logical immediate" z9-109 zarch + c00c oihf RIL_RU "or immediate high" z9-109 zarch + c00d oilf RIL_RU "or immediate low" z9-109 zarch + c205 slfi RIL_RU "subtract logical immediate 32" z9-109 zarch +@@ -969,8 +975,11 @@ c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch + e30000000036 pfd RXY_URRD "prefetch data" z10 zarch + c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch + ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch optparm ++ec0080000054 rnsbgt RIE_RRUUU4 "rotate then and selected bits and test results" z10 zarch optparm + ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch optparm ++ec0080000057 rxsbgt RIE_RRUUU4 "rotate then exclusive or selected bits and test results" z10 zarch optparm + ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch optparm ++ec0080000056 rosbgt RIE_RRUUU4 "rotate then or selected bits and test results" z10 zarch optparm + ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch optparm + ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch optparm + c40f strl RIL_RP "store relative long (32)" z10 zarch +@@ -1003,6 +1012,7 @@ b9da alhhlr RRF_R0RR2 "add logical high low" z196 zarch + cc0a alsih RIL_RI "add logical with signed immediate high with cc" z196 zarch + cc0b alsihn RIL_RI "add logical with signed immediate high no cc" z196 zarch + cc06 brcth RIL_RP "branch relative on count high" z196 zarch ++cc06 jcth RIL_RP "jump on count high" z196 zarch + b9cd chhr RRE_RR "compare high high" z196 zarch + b9dd chlr RRE_RR "compare high low" z196 zarch + e300000000cd chf RXY_RRRD "compare high" z196 zarch +@@ -1017,7 +1027,9 @@ e300000000ca lfh RXY_RRRD "load high" z196 zarch + e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch + e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch + ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch optparm ++ec000080005d risbhgz RIE_RRUUU3 "rotate then insert selected bits high and zero remaining bits" z196 zarch optparm + ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch optparm ++ec0000800051 risblgz RIE_RRUUU3 "rotate then insert selected bits low and zero remaining bits" z196 zarch optparm + e300000000c3 stch RXY_RRRD "store character high" z196 zarch + e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch + e300000000cb stfh RXY_RRRD "store high" z196 zarch +@@ -1913,7 +1925,9 @@ e50a mvcrl SSE_RDRD "move right to left" arch13 zarch + b974 nnrk RRF_R0RR2 "nand 32 bit" arch13 zarch + b964 nngrk RRF_R0RR2 "nand 64 bit" arch13 zarch + b976 nork RRF_R0RR2 "nor 32 bit" arch13 zarch ++b976 notr RRF_R0RR4 "not 32 bit" arch13 zarch + b966 nogrk RRF_R0RR2 "nor 64 bit" arch13 zarch ++b966 notgr RRF_R0RR4 "not 64 bit" arch13 zarch + b977 nxrk RRF_R0RR2 "not exclusive or 32 bit" arch13 zarch + b967 nxgrk RRF_R0RR2 "not exclusive or 64 bit" arch13 zarch + b975 ocrk RRF_R0RR2 "or with complement 32 bit" arch13 zarch diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-4of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-4of12.patch new file mode 100644 index 0000000..98f4f04 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-4of12.patch @@ -0,0 +1,30 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-4of12.patch + +;; Backkport "s390: Correct prno instruction name" +;; (Jens Remus, RHEL-86801) + +IBM z13 (arch11) introduced ppno (Perform Pseudorandom Number Operation). +IBM z14 (arch12) introduced prno (Perform Random Number Operation) and +deprecated ppno. + +opcodes/ + * s390-opc.txt: Correct prno instruction name. + +Signed-off-by: Jens Remus +Reviewed-by: Andreas Krebbel + +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -1910,7 +1910,7 @@ e30000000049 stgsc RXY_RRRD "store guarded storage controls" arch12 zarch + + b929 kma RRF_R0RR "cipher message with galois counter mode" arch12 zarch + +-b93c prno RRE_RR "perform pseudorandom number operation" arch12 zarch ++b93c prno RRE_RR "perform random number operation" arch12 zarch + b9a1 tpei RRE_RR "test pending external interruption" arch12 zarch + b9ac irbm RRE_RR "insert reference bits multiple" arch12 zarch + diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-5of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-5of12.patch new file mode 100644 index 0000000..f8e7d7b --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-5of12.patch @@ -0,0 +1,24 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Nick Clifton +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-5of12.patch + +;; Backkport "Fix building for the s390 target with clang" +;; (Nick Clifton, RHEL-86801) + +diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c +--- a/opcodes/s390-opc.c ++++ b/opcodes/s390-opc.c +@@ -262,9 +262,10 @@ const struct s390_operand s390_operands[] = + + }; + +-static inline void unused_s390_operands_static_asserts(void) ++static inline void ATTRIBUTE_UNUSED ++unused_s390_operands_static_asserts (void) + { +- static_assert(ARRAY_SIZE(s390_operands) - 1 == J32_16); ++ static_assert (ARRAY_SIZE (s390_operands) - 1 == J32_16); + } + + /* Macros used to form opcodes. */ diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-6of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-6of12.patch new file mode 100644 index 0000000..e4cc432 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-6of12.patch @@ -0,0 +1,97 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-6of12.patch + +;; Backkport "s390: Align letter case of instruction descriptions" +;; (Jens Remus, RHEL-86801) + +Change the bitwise operations names "and" and "or" to lower case. Change +the register name abbreviations "FPR", "GR", and "VR" to upper case. + +opcodes/ + * s390-opc.txt: Align letter case of instruction descriptions. + +Signed-off-by: Jens Remus +Reviewed-by: Andreas Krebbel + +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -144,14 +144,14 @@ d3 mvz SS_L0RDRD "move zones" g5 esa,zarch + 67 mxd RX_FERRD "multiply (long to ext.)" g5 esa,zarch + 27 mxdr RR_FEF "multiply (long to ext.)" g5 esa,zarch + 26 mxr RR_FEFE "multiply (ext.)" g5 esa,zarch +-54 n RX_RRRD "AND" g5 esa,zarch +-d4 nc SS_L0RDRD "AND" g5 esa,zarch +-94 ni SI_URD "AND" g5 esa,zarch +-14 nr RR_RR "AND" g5 esa,zarch +-56 o RX_RRRD "OR" g5 esa,zarch +-d6 oc SS_L0RDRD "OR" g5 esa,zarch +-96 oi SI_URD "OR" g5 esa,zarch +-16 or RR_RR "OR" g5 esa,zarch ++54 n RX_RRRD "and" g5 esa,zarch ++d4 nc SS_L0RDRD "and" g5 esa,zarch ++94 ni SI_URD "and" g5 esa,zarch ++14 nr RR_RR "and" g5 esa,zarch ++56 o RX_RRRD "or" g5 esa,zarch ++d6 oc SS_L0RDRD "or" g5 esa,zarch ++96 oi SI_URD "or" g5 esa,zarch ++16 or RR_RR "or" g5 esa,zarch + f2 pack SS_LLRDRD "pack" g5 esa,zarch + b248 palb RRE_00 "purge ALB" g5 esa,zarch + b218 pc S_RD "program call" g5 esa,zarch +@@ -215,8 +215,8 @@ b6 stctl RS_CCRD "store control" g5 esa,zarch + 40 sth RX_RRRD "store halfword" g5 esa,zarch + b202 stidp S_RD "store CPU id" g5 esa,zarch + 90 stm RS_RRRD "store multiple" g5 esa,zarch +-ac stnsm SI_URD "store then AND system mask" g5 esa,zarch +-ad stosm SI_URD "store then OR system mask" g5 esa,zarch ++ac stnsm SI_URD "store then and system mask" g5 esa,zarch ++ad stosm SI_URD "store then or system mask" g5 esa,zarch + b209 stpt S_RD "store CPU timer" g5 esa,zarch + b211 stpx S_RD "store prefix" g5 esa,zarch + b234 stsch S_RD "store subchannel" g5 esa,zarch +@@ -239,10 +239,10 @@ dd trt SS_L0RDRD "translate and test" g5 esa,zarch + b235 tsch S_RD "test subchannel" g5 esa,zarch + f3 unpk SS_LLRDRD "unpack" g5 esa,zarch + 0102 upt E "update tree" g5 esa,zarch +-57 x RX_RRRD "exclusive OR" g5 esa,zarch +-d7 xc SS_L0RDRD "exclusive OR" g5 esa,zarch +-97 xi SI_URD "exclusive OR" g5 esa,zarch +-17 xr RR_RR "exclusive OR" g5 esa,zarch ++57 x RX_RRRD "exclusive or" g5 esa,zarch ++d7 xc SS_L0RDRD "exclusive or" g5 esa,zarch ++97 xi SI_URD "exclusive or" g5 esa,zarch ++17 xr RR_RR "exclusive or" g5 esa,zarch + f8 zap SS_LLRDRD "zero and add" g5 esa,zarch + a70a ahi RI_RI "add halfword immediate" g5 esa,zarch + 84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch +@@ -821,8 +821,8 @@ b370 lpdfr RRE_FF "load positive no cc" z9-ec zarch + b371 lndfr RRE_FF "load negative no cc" z9-ec zarch + b372 cpsdr RRF_F0FF2 "copy sign" z9-ec zarch + b373 lcdfr RRE_FF "load complement no cc" z9-ec zarch +-b3c1 ldgr RRE_FR "load fpr from gr" z9-ec zarch +-b3cd lgdr RRE_RF "load gr from fpr" z9-ec zarch ++b3c1 ldgr RRE_FR "load FPR from GR" z9-ec zarch ++b3cd lgdr RRE_RF "load GR from FPR" z9-ec zarch + b3d2 adtr RRR_F0FF "add long dfp" z9-ec zarch + b3da axtr RRR_FE0FEFE "add extended dfp" z9-ec zarch + b3e4 cdtr RRE_FF "compare long dfp" z9-ec zarch +@@ -1203,11 +1203,11 @@ e70000000040 vleib VRI_V0IU "vector load byte element immediate" z13 zarch vx + e70000000041 vleih VRI_V0IU "vector load halfword element immediate" z13 zarch vx + e70000000043 vleif VRI_V0IU "vector load word element immediate" z13 zarch vx + e70000000042 vleig VRI_V0IU "vector load double word element immediate" z13 zarch vx +-e70000000021 vlgv VRS_RVRDU "vector load gr from vr element" z13 zarch vx +-e70000000021 vlgvb VRS_RVRD "vector load gr from vr byte element" z13 zarch vx +-e70000001021 vlgvh VRS_RVRD "vector load gr from vr halfword element" z13 zarch vx +-e70000002021 vlgvf VRS_RVRD "vector load gr from vr word element" z13 zarch vx +-e70000003021 vlgvg VRS_RVRD "vector load gr from vr double word element" z13 zarch vx ++e70000000021 vlgv VRS_RVRDU "vector load GR from VR element" z13 zarch vx ++e70000000021 vlgvb VRS_RVRD "vector load GR from VR byte element" z13 zarch vx ++e70000001021 vlgvh VRS_RVRD "vector load GR from VR halfword element" z13 zarch vx ++e70000002021 vlgvf VRS_RVRD "vector load GR from VR word element" z13 zarch vx ++e70000003021 vlgvg VRS_RVRD "vector load GR from VR double word element" z13 zarch vx + e70000000004 vllez VRX_VRRDU "vector load logical element and zero" z13 zarch vx + e70000000004 vllezb VRX_VRRD "vector load logical byte element and zero" z13 zarch vx + e70000001004 vllezh VRX_VRRD "vector load logical halfword element and zero" z13 zarch vx diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-7of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-7of12.patch new file mode 100644 index 0000000..e4638b4 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-7of12.patch @@ -0,0 +1,97 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-7of12.patch + +;; Backkport "s390: Provide IBM z16 (arch14) instruction descriptions" +;; (Jens Remus, RHEL-86801) + +Provide descriptions for instructions introduced with commit ba2b480f103 +("IBM Z: Implement instruction set extensions"). This complements commit +69341966def ("IBM zSystems: Add support for z16 as CPU name."). Use +instruction names from IBM z/Architecture Principles of Operation [1] as +instruction description. + +[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16, + https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf + +opcodes/ + * s390-opc.txt: Add descriptions for IBM z16 (arch14) + instructions. + +Signed-off-by: Jens Remus +Reviewed-by: Andreas Krebbel + +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -2034,31 +2034,41 @@ e60000000052 vcvbg VRR_RV0UU "vector convert to binary 64 bit" arch13 zarch optp + b93a kdsa RRE_RR "compute digital signature authentication" arch13 zarch + + +-# arch14 instructions +- +-e60000000074 vschp VRR_VVV0U0U " " arch14 zarch +-e60000002074 vschsp VRR_VVV0U0 " " arch14 zarch +-e60000003074 vschdp VRR_VVV0U0 " " arch14 zarch +-e60000004074 vschxp VRR_VVV0U0 " " arch14 zarch +-e6000000007c vscshp VRR_VVV " " arch14 zarch +-e6000000007d vcsph VRR_VVV0U0 " " arch14 zarch +-e60000000051 vclzdp VRR_VV0U2 " " arch14 zarch +-e60000000070 vpkzr VRI_VVV0UU2 " " arch14 zarch +-e60000000072 vsrpr VRI_VVV0UU2 " " arch14 zarch +-e60000000054 vupkzh VRR_VV0U2 " " arch14 zarch +-e6000000005c vupkzl VRR_VV0U2 " " arch14 zarch +- +-b93b nnpa RRE_00 " " arch14 zarch +-e60000000056 vclfnh VRR_VV0UU2 " " arch14 zarch +-e6000000005e vclfnl VRR_VV0UU2 " " arch14 zarch +-e60000000075 vcrnf VRR_VVV0UU " " arch14 zarch +-e6000000005d vcfn VRR_VV0UU2 " " arch14 zarch +-e60000000055 vcnf VRR_VV0UU2 " " arch14 zarch +- +-b98B rdp RRF_RURR2 " " arch14 zarch optparm +- +-eb0000000071 lpswey SIY_RD " " arch14 zarch +-b200 lbear S_RD " " arch14 zarch +-b201 stbear S_RD " " arch14 zarch +- +-b28f qpaci S_RD " " arch14 zarch ++# arch14 (z16) instructions ++ ++# Vector-Packed-Decimal-Enhancement Facility 2 ++ ++e60000000074 vschp VRR_VVV0U0U "decimal scale and convert to hfp" arch14 zarch ++e60000002074 vschsp VRR_VVV0U0 "decimal scale and convert to short hfp" arch14 zarch ++e60000003074 vschdp VRR_VVV0U0 "decimal scale and convert to long hfp" arch14 zarch ++e60000004074 vschxp VRR_VVV0U0 "decimal scale and convert to extended hfp" arch14 zarch ++e6000000007c vscshp VRR_VVV "decimal scale and convert and split to hfp" arch14 zarch ++e6000000007d vcsph VRR_VVV0U0 "vector convert hfp to scaled decimal" arch14 zarch ++e60000000051 vclzdp VRR_VV0U2 "vector count leading zero digits" arch14 zarch ++e60000000070 vpkzr VRI_VVV0UU2 "vector pack zoned register" arch14 zarch ++e60000000072 vsrpr VRI_VVV0UU2 "vector shift and round decimal register" arch14 zarch ++e60000000054 vupkzh VRR_VV0U2 "vector unpack zoned high" arch14 zarch ++e6000000005c vupkzl VRR_VV0U2 "vector unpack zoned low" arch14 zarch ++ ++# Neural-Network-Processing-Assist Facility ++ ++b93b nnpa RRE_00 "neural network processing assist" arch14 zarch ++e60000000056 vclfnh VRR_VV0UU2 "vector fp convert and lengthen from nnp high" arch14 zarch ++e6000000005e vclfnl VRR_VV0UU2 "vector fp convert and lengthen from nnp low" arch14 zarch ++e60000000075 vcrnf VRR_VVV0UU "vector fp convert and round to nnp" arch14 zarch ++e6000000005d vcfn VRR_VV0UU2 "vector fp convert from nnp" arch14 zarch ++e60000000055 vcnf VRR_VV0UU2 "vector fp convert to nnp" arch14 zarch ++ ++# Reset-DAT-Protection Facility ++ ++b98B rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm ++ ++# BEAR-Enhancement Facility ++ ++eb0000000071 lpswey SIY_RD "load PSW extended" arch14 zarch ++b200 lbear S_RD "load bear" arch14 zarch ++b201 stbear S_RD "store bear" arch14 zarch ++ ++# Processor-Activity-Instrumentation Facility ++ ++b28f qpaci S_RD "query processor activity counter information" arch14 zarch diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-8of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-8of12.patch new file mode 100644 index 0000000..bd889df --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-8of12.patch @@ -0,0 +1,25 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-8of12.patch + +;; Backkport "s390: Align opcodes to lower-case" +;; (Jens Remus, RHEL-86801) + +opcodes/ + * s390-opc.txt (rdp): Change opcode to lower-case. + +Signed-off-by: Jens Remus + +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -2061,7 +2061,7 @@ e60000000055 vcnf VRR_VV0UU2 "vector fp convert to nnp" arch14 zarch + + # Reset-DAT-Protection Facility + +-b98B rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm ++b98b rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm + + # BEAR-Enhancement Facility + diff --git a/SOURCES/gdb-rhel-86801-binutils-z17-update-9of12.patch b/SOURCES/gdb-rhel-86801-binutils-z17-update-9of12.patch new file mode 100644 index 0000000..34afaf1 --- /dev/null +++ b/SOURCES/gdb-rhel-86801-binutils-z17-update-9of12.patch @@ -0,0 +1,151 @@ +From FEDORA_PATCHES Mon Sep 17 00:00:00 2001 +From: Jens Remus +Date: Mon, 28 Apr 2025 11:23:22 -0700 +Subject: gdb-rhel-86801-binutils-z17-update-9of12.patch + +;; Backkport "s390: Simplify (dis)assembly of insn operands with const bits" +;; (Jens Remus, RHEL-86801) + +Simplify assembly and disassembly of extended mnemonics with operands +with constant ORed bits: +Their instruction template already contains the respective constant +operand bits, as they are significant to distinguish the extended from +their base mnemonic. Operands are ORed into the instruction template. +Therefore it is not necessary to OR the constant bits into the operand +value during assembly in s390_insert_operand. +Additionally the constant operand bits from the instruction template +can be used to mask them from the operand value during disassembly in +s390_print_insn_with_opcode. For now do so for non-length unsigned +integer operands only. + +The separate instruction formats need to be retained, as their masks +differ, which is relevant during disassembly to distinguish the base +and extended mnemonics from each other. + +This affects the following extended mnemonics: +- vfaebs, vfaehs, vfaefs +- vfaezb, vfaezh, vfaezf +- vfaezbs, vfaezhs, vfaezfs +- vstrcbs, vstrchs, vstrcfs +- vstrczb, vstrczh, vstrczf +- vstrczbs, vstrczhs, vstrczfs +- wcefb, wcdgb +- wcelfb, wcdlgb +- wcfeb, wcgdb +- wclfeb, wclgdb +- wfisb, wfidb, wfixb +- wledb, wflrd, wflrx + +include/ + * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, + S390_OPERAND_OR8): Remove. + +opcodes/ + * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. + (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define + as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. + (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining + respective insn fmt mask. + (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): + Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt + mask. + * s390-dis.c (s390_print_insn_with_opcode): Mask constant + operand bits set in insn template of non-length unsigned + integer operands. + +gas/ + * config/tc-s390.c (s390_insert_operand): Do not OR constant + operand value bits. + +Signed-off-by: Jens Remus + +diff --git a/include/opcode/s390.h b/include/opcode/s390.h +--- a/include/opcode/s390.h ++++ b/include/opcode/s390.h +@@ -168,8 +168,4 @@ extern const struct s390_operand s390_operands[]; + + #define S390_OPERAND_CP16 0x1000 + +-#define S390_OPERAND_OR1 0x2000 +-#define S390_OPERAND_OR2 0x4000 +-#define S390_OPERAND_OR8 0x8000 +- + #endif /* S390_H */ +diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c +--- a/opcodes/s390-dis.c ++++ b/opcodes/s390-dis.c +@@ -277,12 +277,14 @@ s390_print_insn_with_opcode (bfd_vma memaddr, + { + enum disassembler_style style; + +- if (flags & S390_OPERAND_OR1) +- val.u &= ~1; +- if (flags & S390_OPERAND_OR2) +- val.u &= ~2; +- if (flags & S390_OPERAND_OR8) +- val.u &= ~8; ++ if (!(flags & S390_OPERAND_LENGTH)) ++ { ++ union operand_value insn_opval; ++ ++ /* Mask any constant operand bits set in insn template. */ ++ insn_opval = s390_extract_operand (opcode->opcode, operand); ++ val.u &= ~insn_opval.u; ++ } + + if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) + && val.u == 0 +diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c +--- a/opcodes/s390-opc.c ++++ b/opcodes/s390-opc.c +@@ -208,17 +208,9 @@ const struct s390_operand s390_operands[] = + { 4, 20, 0 }, + #define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */ + { 4, 24, 0 }, +-#define U4_OR1_24 (U4_24 + 1) /* 4 bit unsigned value ORed with 1 */ +- { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */ +-#define U4_OR2_24 (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */ +- { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */ +-#define U4_OR3_24 (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */ +- { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */ +-#define U4_28 (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */ ++#define U4_28 (U4_24+1) /* 4 bit unsigned value starting at 28 */ + { 4, 28, 0 }, +-#define U4_OR8_28 (U4_28 + 1) /* 4 bit unsigned value ORed with 8 */ +- { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */ +-#define U4_32 (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */ ++#define U4_32 (U4_28+1) /* 4 bit unsigned value starting at 32 */ + { 4, 32, 0 }, + #define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */ + { 4, 36, 0 }, +@@ -512,23 +504,23 @@ unused_s390_operands_static_asserts (void) + #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ + #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ + #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ +-#define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/ +-#define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/ +-#define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/ ++#define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/ ++#define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/ ++#define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/ + #define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ + #define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ + #define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ + #define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ + #define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ + #define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ +-#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ ++#define INSTR_VRR_VV0UU8 INSTR_VRR_VV0UU /* e.g. wcdgb */ + #define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ + #define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ + #define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ + #define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ +-#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/ +-#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/ +-#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/ ++#define INSTR_VRR_VVVU0VB1 INSTR_VRR_VVVU0VB /* e.g. vstrcbs*/ ++#define INSTR_VRR_VVVU0VB2 INSTR_VRR_VVVU0VB /* e.g. vstrczb*/ ++#define INSTR_VRR_VVVU0VB3 INSTR_VRR_VVVU0VB /* e.g. vstrczbs*/ + #define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ + #define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ + #define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ diff --git a/SPECS/gdb.spec b/SPECS/gdb.spec index 63022a2..7436be1 100644 --- a/SPECS/gdb.spec +++ b/SPECS/gdb.spec @@ -57,7 +57,7 @@ Version: 14.2 # The release always contains a leading reserved number, start it at 1. # `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing. -Release: 4%{?dist} +Release: 4.1%{?dist} License: GPL-3.0-or-later AND BSD-3-Clause AND FSFAP AND LGPL-2.1-or-later AND GPL-2.0-or-later AND LGPL-2.0-or-later AND LicenseRef-Fedora-Public-Domain AND GFDL-1.3-or-later AND LGPL-2.0-or-later WITH GCC-exception-2.0 AND GPL-3.0-or-later WITH GCC-exception-3.1 AND GPL-2.0-or-later WITH GNU-compiler-exception # Do not provide URL for snapshots as the file lasts there only for 2 days. @@ -1250,7 +1250,11 @@ fi %endif %changelog -* Wed Jan 9 2025 Keith Seitz - 14.2-4.el9 +* Tue May 6 2025 Keith Seitz - 14.2-4.1.el9 +- Backport IBM z17 binutils patches + (Jens Remus et al, RHEL-89863) + +* Thu Jan 9 2025 Keith Seitz - 14.2-4.el9 - gdb-add-index.patch: Use "command -v" instead of "which". (Keith Seitz, RHEL-73209)