44 lines
1.9 KiB
Diff
44 lines
1.9 KiB
Diff
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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Keith Seitz <keiths@redhat.com>
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Date: Fri, 11 Jan 2019 17:02:19 -0500
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Subject: gdb-rhbz1187581-power8-regs-not-in-8.2-15of15.patch
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;; [PowerPC] Document requirements for VSX feature
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;; Pedro Franco de Carvalho, RH BZ 1187581
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[PowerPC] Document requirements for VSX feature
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As suggested in
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https://sourceware.org/ml/gdb-patches/2018-10/msg00510.html, this
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patch changes the documentation for the VSX tdesc feature to make it
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clear that the altivec and FPU features are requirements.
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gdb/doc/ChangeLog:
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2018-11-09 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* gdb.texinfo (PowerPC Features): Document the altivec and fpu
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requirements for the org.gnu.gdb.power.vsx feature.
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diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
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--- a/gdb/doc/gdb.texinfo
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+++ b/gdb/doc/gdb.texinfo
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@@ -42541,11 +42541,13 @@ contain registers @samp{vr0} through @samp{vr31}, @samp{vscr},
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and @samp{vrsave}.
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The @samp{org.gnu.gdb.power.vsx} feature is optional. It should
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-contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN}
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-will combine these registers with the floating point registers
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-(@samp{f0} through @samp{f31}) and the altivec registers (@samp{vr0}
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-through @samp{vr31}) to present the 128-bit wide registers @samp{vs0}
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-through @samp{vs63}, the set of vector registers for POWER7.
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+contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN} will
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+combine these registers with the floating point registers (@samp{f0}
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+through @samp{f31}) and the altivec registers (@samp{vr0} through
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+@samp{vr31}) to present the 128-bit wide registers @samp{vs0} through
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+@samp{vs63}, the set of vector-scalar registers for POWER7.
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+Therefore, this feature requires both @samp{org.gnu.gdb.power.fpu} and
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+@samp{org.gnu.gdb.power.altivec}.
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The @samp{org.gnu.gdb.power.spe} feature is optional. It should
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contain registers @samp{ev0h} through @samp{ev31h}, @samp{acc}, and
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