161 lines
8.5 KiB
Diff
161 lines
8.5 KiB
Diff
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diff -rup fred/gas/config/tc-i386.c binutils-2.41/gas/config/tc-i386.c
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--- fred/gas/config/tc-i386.c 2023-12-07 10:00:21.013005830 +0000
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+++ binutils-2.41/gas/config/tc-i386.c 2023-12-07 10:00:28.037015037 +0000
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@@ -1053,8 +1053,8 @@ static const arch_entry cpu_arch[] =
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SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false),
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SUBARCH (xsaves, XSAVES, ANY_XSAVES, false),
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SUBARCH (aes, AES, ANY_AES, false),
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- SUBARCH (pclmul, PCLMUL, ANY_PCLMUL, false),
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- SUBARCH (clmul, PCLMUL, ANY_PCLMUL, true),
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+ SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false),
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+ SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true),
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SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false),
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SUBARCH (rdrnd, RDRND, RDRND, false),
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SUBARCH (f16c, F16C, ANY_F16C, false),
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@@ -1861,7 +1861,7 @@ cpu_flags_match (const insn_template *t)
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|| (sse2avx && !i.prefix[DATA_PREFIX]))
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&& (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
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&& (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
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- && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
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+ && (!x.bitfield.cpupclmulqdq || cpu.bitfield.cpupclmulqdq))
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match |= CPU_FLAGS_ARCH_MATCH;
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}
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else if (x.bitfield.cpuavx512f)
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diff -rup fred/opcodes/i386-gen.c binutils-2.41/opcodes/i386-gen.c
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--- fred/opcodes/i386-gen.c 2023-12-07 10:00:22.092007244 +0000
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+++ binutils-2.41/opcodes/i386-gen.c 2023-12-07 10:00:28.038015039 +0000
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@@ -79,7 +79,7 @@ static const dependency isa_dependencies
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{ "AMDFAM10",
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"K8|FISTTP|SSE4A|ABM|MONITOR" },
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{ "BDVER1",
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- "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
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+ "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMULQDQ|PRFCHW" },
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{ "BDVER2",
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"BDVER1|FMA|BMI|TBM|F16C" },
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{ "BDVER3",
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@@ -87,7 +87,7 @@ static const dependency isa_dependencies
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{ "BDVER4",
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"BDVER3|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
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{ "ZNVER1",
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- "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
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+ "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMULQDQ|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
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{ "ZNVER2",
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"ZNVER1|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
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{ "ZNVER3",
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@@ -97,7 +97,7 @@ static const dependency isa_dependencies
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{ "BTVER1",
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"GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
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{ "BTVER2",
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- "BTVER1|AVX|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" },
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+ "BTVER1|AVX|BMI|F16C|AES|PCLMULQDQ|Movbe|Xsaveopt|PRFCHW" },
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{ "286",
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"186" },
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{ "386",
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@@ -132,7 +132,7 @@ static const dependency isa_dependencies
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"XSAVE" },
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{ "AES",
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"SSE2" },
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- { "PCLMUL",
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+ { "PCLMULQDQ",
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"SSE2" },
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{ "FMA",
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"AVX" },
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@@ -307,7 +307,7 @@ static bitfield cpu_flags[] =
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BITFIELD (Xsave),
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BITFIELD (Xsaveopt),
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BITFIELD (AES),
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- BITFIELD (PCLMUL),
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+ BITFIELD (PCLMULQDQ),
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BITFIELD (FMA),
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BITFIELD (FMA4),
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BITFIELD (XOP),
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diff -rup fred/opcodes/i386-init.h binutils-2.41/opcodes/i386-init.h
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--- fred/opcodes/i386-init.h 2023-12-07 10:00:22.092007244 +0000
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+++ binutils-2.41/opcodes/i386-init.h 2023-12-07 10:00:51.260045479 +0000
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@@ -432,7 +432,7 @@
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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-#define CPU_PCLMUL_FLAGS \
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+#define CPU_PCLMULQDQ_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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@@ -1791,7 +1791,7 @@
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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-#define CPU_ANY_PCLMUL_FLAGS \
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+#define CPU_ANY_PCLMULQDQ_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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diff -rup fred/opcodes/i386-opc.h binutils-2.41/opcodes/i386-opc.h
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--- fred/opcodes/i386-opc.h 2023-12-07 10:00:22.093007246 +0000
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+++ binutils-2.41/opcodes/i386-opc.h 2023-12-07 10:00:28.038015039 +0000
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@@ -121,8 +121,8 @@ enum
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CpuXsaveopt,
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/* AES support required */
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CpuAES,
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- /* PCLMUL support required */
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- CpuPCLMUL,
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+ /* PCLMULQDQ support required */
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+ CpuPCLMULQDQ,
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/* FMA support required */
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CpuFMA,
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/* FMA4 support required */
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@@ -374,7 +374,7 @@ typedef union i386_cpu_flags
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unsigned int cpuxsave:1;
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unsigned int cpuxsaveopt:1;
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unsigned int cpuaes:1;
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- unsigned int cpupclmul:1;
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+ unsigned int cpupclmulqdq:1;
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unsigned int cpufma:1;
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unsigned int cpufma4:1;
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unsigned int cpuxop:1;
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diff -rup fred/opcodes/i386-opc.tbl binutils-2.41/opcodes/i386-opc.tbl
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--- fred/opcodes/i386-opc.tbl 2023-12-07 10:00:22.093007246 +0000
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+++ binutils-2.41/opcodes/i386-opc.tbl 2023-12-07 10:00:28.038015039 +0000
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@@ -1448,15 +1448,15 @@ vaesdeclast, 0x66df, VAES, Modrm|Vex256|
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vaesenc, 0x66dc, VAES, Modrm|Vex256|Space0F38|VexVVVV|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
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vaesenclast, 0x66dd, VAES, Modrm|Vex256|Space0F38|VexVVVV|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
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-// PCLMUL
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+// PCLMULQDQ
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<pclmul:cpu:attr, $avx:AVX|:Vex128|VexW0|SSE2AVX|VexVVVV, $sse::>
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-pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM }
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-pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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-pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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-pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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-pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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+pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM }
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+pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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+pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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+pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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+pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
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// GFNI
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@@ -1771,13 +1771,13 @@ vaesenclast, 0x66dd, AVX|AES, Modrm|Vex|
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vaesimc, 0x66db, AVX|AES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
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vaeskeygenassist, 0x66df, AVX|AES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
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-// PCLMUL + AVX
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+// PCLMULQDQ + AVX
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-vpclmulqdq, 0x6644, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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-vpclmullqlqdq, 0x6644/0x00, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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-vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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-vpclmullqhqdq, 0x6644/0x10, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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-vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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+vpclmulqdq, 0x6644, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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+vpclmullqlqdq, 0x6644/0x00, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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+vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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+vpclmullqhqdq, 0x6644/0x10, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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+vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
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// GFNI + AVX
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