diff --git a/gcc.spec b/gcc.spec index bb90c9f..dd3b00e 100644 --- a/gcc.spec +++ b/gcc.spec @@ -358,6 +358,9 @@ Patch3016: 0019-xfails.patch Patch3017: 0020-more-fixes.patch Patch3018: 0021-libstdc++-disable-tests.patch Patch3019: 0022-libstdc++-revert-behavior.patch +Patch3020: gcc13-testsuite-no-ssp.patch +Patch3021: gcc13-testsuite-p10.patch +Patch3022: gcc13-testsuite-plugin.patch %if 0%{?rhel} == 9 %global nonsharedver 110 @@ -736,6 +739,9 @@ rm -f libphobos/testsuite/libphobos.gc/forkgc2.d %if 0%{?rhel} <= 7 %patch -P3019 -p1 -b .dts-test-19~ %endif +%patch -P3020 -p1 -b .dts-test-20~ +%patch -P3021 -p1 -b .dts-test-21~ +%patch -P3021 -p1 -b .dts-test-22~ find gcc/testsuite -name \*.pr96939~ | xargs rm -f @@ -2900,6 +2906,7 @@ fi %changelog * Tue Jun 27 2023 Marek Polacek 13.1.1-4.2 - fix switch to -gdwarf-4 on RHEL 8 (#2217938) +- apply some testsuite fixes (#2217498) * Tue Jun 20 2023 Marek Polacek 13.1.1-4.1 - don't require libgccjit-docs (#2216333) diff --git a/gcc13-testsuite-no-ssp.patch b/gcc13-testsuite-no-ssp.patch new file mode 100644 index 0000000..b041a65 --- /dev/null +++ b/gcc13-testsuite-no-ssp.patch @@ -0,0 +1,46 @@ +From b964d2647b0da15543faed5add5044fd79a85c5c Mon Sep 17 00:00:00 2001 +From: Marek Polacek +Date: Thu, 29 Jun 2023 15:59:29 -0400 +Subject: [PATCH] i386: add -fno-stack-protector to two tests + +These tests fail when the testsuite is executed with -fstack-protector-strong. +To avoid this, this patch adds -fno-stack-protector to dg-options. + +Tested on x86_64-pc-linux-gnu, ok for trunk? + +gcc/testsuite/ChangeLog: + + * gcc.target/i386/pr104610.c: Use -fno-stack-protector. + * gcc.target/i386/pr69482-1.c: Likewise. +--- + gcc/testsuite/gcc.target/i386/pr104610.c | 2 +- + gcc/testsuite/gcc.target/i386/pr69482-1.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c b/gcc/testsuite/gcc.target/i386/pr104610.c +index fe39cbe5b8a..5173fc8898c 100644 +--- a/gcc/testsuite/gcc.target/i386/pr104610.c ++++ b/gcc/testsuite/gcc.target/i386/pr104610.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -mavx -mmove-max=256 -mstore-max=256" } */ ++/* { dg-options "-O2 -mavx -mmove-max=256 -mstore-max=256 -fno-stack-protector" } */ + /* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */ + /* { dg-final { scan-assembler-times {sete} 1 } } */ + /* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */ +diff --git a/gcc/testsuite/gcc.target/i386/pr69482-1.c b/gcc/testsuite/gcc.target/i386/pr69482-1.c +index f192261b104..99bb6ad5a37 100644 +--- a/gcc/testsuite/gcc.target/i386/pr69482-1.c ++++ b/gcc/testsuite/gcc.target/i386/pr69482-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O3" } */ ++/* { dg-options "-O3 -fno-stack-protector" } */ + + static inline void memset_s(void* s, int n) { + volatile unsigned char * p = s; + +base-commit: 070a6bf0bdc6761ad77ac97404c98f00a7007d54 +-- +2.41.0 + diff --git a/gcc13-testsuite-p10.patch b/gcc13-testsuite-p10.patch new file mode 100644 index 0000000..2cffe78 --- /dev/null +++ b/gcc13-testsuite-p10.patch @@ -0,0 +1,131 @@ +commit 38dc1b9145d3b27317a03ace3ab21fb76f6c428a +Author: Carl Love +Date: Fri Mar 10 18:16:52 2023 -0500 + + rs6000: Fix test int_128bit-runnable.c instruction counts + + The test reports two failures on Power 10LE: + + FAIL: .../int_128bit-runnable.c scan-assembler-times \\\\mvdivsq\\\\M 1 + FAIL: .../int_128bit-runnable.c scan-assembler-times \\\\mvextsd2q\\\\M 6 + + The current counts are : + + vdivsq 3 + vextsd2q 4 + + The counts changed with commit: + + commit 852b11da11a181df517c0348df044354ff0656d6 + Author: Michael Meissner + Date: Wed Jul 7 21:55:38 2021 -0400 + + Generate 128-bit int divide/modulus on power10. + + This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ + instructions to do 128-bit arithmetic. + + 2021-07-07 Michael Meissner + + The code generation changed significantly. There are two places where + the vextsd2q is "replaced" by a vdivsq instruction thus increasing the + vdivsq count from 1 to 3. The first case is: + + expected_result = vec_arg1[0]/4; + 10000af8: 60 01 df e8 ld r6,352(r31) + 10000afc: 68 01 ff e8 ld r7,360(r31) + 10000b00: 76 fe e9 7c sradi r9,r7,63 + 10000b04: 67 4b 00 7c mtvsrdd vs32,0,r9 + 10000b08: 02 06 1b 10 vextsd2q v0,v0 <---- + 10000b0c: 03 00 40 39 li r10,3 + 10000b10: 00 00 60 39 li r11,0 + 10000b14: 67 00 09 7c mfvrd r9,v0 + 10000b18: 67 02 08 7c mfvsrld r8,vs32 + 10000b1c: 38 50 08 7d and r8,r8,r10 + 10000b20: 38 58 29 7d and r9,r9,r11 + 10000b24: 78 4b 2b 7d mr r11,r9 + 10000b28: 78 43 0a 7d mr r10,r8 + 10000b2c: 14 30 4a 7f addc r26,r10,r6 + 10000b30: 14 39 6b 7f adde r27,r11,r7 + 10000b34: 46 f0 69 7b sldi r9,r27,62 + 10000b38: 82 f0 58 7b srdi r24,r26,2 + 10000b3c: 78 c3 38 7d or r24,r9,r24 + 10000b40: 74 16 79 7f sradi r25,r27,2 + 10000b44: 30 00 1f fb std r24,48(r31) + 10000b48: 38 00 3f fb std r25,56(r31) + + To: + + expected_result = vec_arg1[0]/4; + 10000af8: 69 01 1f f4 lxv vs32,352(r31) + 10000afc: 04 00 20 39 li r9,4 + 10000b00: 00 00 40 39 li r10,0 + 10000b04: 67 4b 2a 7c mtvsrdd vs33,r10,r9 + 10000b08: 0b 09 00 10 vdivsq v0,v0,v1 <---- + 10000b0c: 3d 00 1f f4 stxv vs32,48(r31) + + The second case were a vexts2q instruction is replaced with vdivsq: + + From: + + expected_result = arg1/16; + 10000c24: 40 00 df e8 ld r6,64(r31) + 10000c28: 48 00 ff e8 ld r7,72(r31) + 10000c2c: 76 fe e9 7c sradi r9,r7,63 + 10000c30: 67 4b 00 7c mtvsrdd vs32,0,r9 + 10000c34: 02 06 1b 10 vextsd2q v0,v0 <--- + 10000c38: 0f 00 40 39 li r10,15 + 10000c3c: 00 00 60 39 li r11,0 + 10000c40: 67 00 09 7c mfvrd r9,v0 + 10000c44: 67 02 08 7c mfvsrld r8,vs32 + 10000c48: 38 50 08 7d and r8,r8,r10 + 10000c4c: 38 58 29 7d and r9,r9,r11 + 10000c50: 78 4b 2b 7d mr r11,r9 + 10000c54: 78 43 0a 7d mr r10,r8 + 10000c58: 14 30 ca 7e addc r22,r10,r6 + 10000c5c: 14 39 eb 7e adde r23,r11,r7 + 10000c60: c6 e0 e9 7a sldi r9,r23,60 + 10000c64: 02 e1 d4 7a srdi r20,r22,4 + 10000c68: 78 a3 34 7d or r20,r9,r20 + 10000c6c: 74 26 f5 7e sradi r21,r23,4 + 10000c70: 30 00 9f fa std r20,48(r31) + 10000c74: 38 00 bf fa std r21,56(r31) + + To: + + expected_result = arg1/16; + 10000be8: 49 00 1f f4 lxv vs32,64(r31) + 10000bec: 10 00 20 39 li r9,16 + 10000bf0: 00 00 40 39 li r10,0 + 10000bf4: 67 4b 2a 7c mtvsrdd vs33,r10,r9 + 10000bf8: 0b 09 00 10 vdivsq v0,v0,v1 <--- + 10000bfc: 3d 00 1f f4 stxv vs32,48(r31) + + The patch has been tested on Power10LE with no regressions. + + gcc/testsuite/ + * gcc.target/powerpc/int_128bit-runnable.c: Update expected + instruction counts. + +diff --git a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c +index 68217c62325..756142d1bc6 100644 +--- a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c ++++ b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c +@@ -4,7 +4,7 @@ + + /* Check that the expected 128-bit instructions are generated if the processor + supports the 128-bit integer instructions. */ +-/* { dg-final { scan-assembler-times {\mvextsd2q\M} 6 } } */ ++/* { dg-final { scan-assembler-times {\mvextsd2q\M} 4 } } */ + /* { dg-final { scan-assembler-times {\mvslq\M} 2 } } */ + /* { dg-final { scan-assembler-times {\mvsrq\M} 2 } } */ + /* { dg-final { scan-assembler-times {\mvsraq\M} 2 } } */ +@@ -18,7 +18,7 @@ + /* { dg-final { scan-assembler-times {\mvmulesd\M} 1 } } */ + /* { dg-final { scan-assembler-times {\mvmulosd\M} 1 } } */ + /* { dg-final { scan-assembler-times {\mvmulld\M} 1 } } */ +-/* { dg-final { scan-assembler-times {\mvdivsq\M} 1 } } */ ++/* { dg-final { scan-assembler-times {\mvdivsq\M} 3 } } */ + /* { dg-final { scan-assembler-times {\mvdivuq\M} 1 } } */ + /* { dg-final { scan-assembler-times {\mvdivesq\M} 1 } } */ + /* { dg-final { scan-assembler-times {\mvdiveuq\M} 1 } } */ diff --git a/gcc13-testsuite-plugin.patch b/gcc13-testsuite-plugin.patch new file mode 100644 index 0000000..a1e0e69 --- /dev/null +++ b/gcc13-testsuite-plugin.patch @@ -0,0 +1,94 @@ +From 2ef902063590ebd7e8b8b8b4d708f6c7dc62a81d Mon Sep 17 00:00:00 2001 +From: Marek Polacek +Date: Thu, 29 Jun 2023 14:57:48 -0400 +Subject: [PATCH] testsuite: Use -fno-report-bug in gcc.dg/plugin/ + +Certain downstream compilers (for example, in Fedora) default to +-freport-bug. The extra output breaks the following tests. We can use +-fno-report-bug to fix that. Patch verified with: + +$ make check RUNTESTFLAGS='--target_board=unix\{,-freport-bug\} plugin.exp' + +Tested x86_64-pc-linux-gnu, ok for trunk/13? + +gcc/testsuite/ChangeLog: + + * gcc.dg/plugin/crash-test-ice-sarif.c: Use -fno-report-bug. Adjust + scan-sarif-file. + * gcc.dg/plugin/crash-test-ice-stderr.c: Use -fno-report-bug. + * gcc.dg/plugin/crash-test-write-though-null-sarif.c: Use + -fno-report-bug. Adjust scan-sarif-file. + * gcc.dg/plugin/crash-test-write-though-null-stderr.c: Use + -fno-report-bug. +--- + gcc/testsuite/gcc.dg/plugin/crash-test-ice-sarif.c | 3 ++- + gcc/testsuite/gcc.dg/plugin/crash-test-ice-stderr.c | 1 + + .../gcc.dg/plugin/crash-test-write-though-null-sarif.c | 3 ++- + .../gcc.dg/plugin/crash-test-write-though-null-stderr.c | 1 + + 4 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/gcc/testsuite/gcc.dg/plugin/crash-test-ice-sarif.c b/gcc/testsuite/gcc.dg/plugin/crash-test-ice-sarif.c +index 3b773a9a84c..84a4347a17e 100644 +--- a/gcc/testsuite/gcc.dg/plugin/crash-test-ice-sarif.c ++++ b/gcc/testsuite/gcc.dg/plugin/crash-test-ice-sarif.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ + /* { dg-options "-fdiagnostics-format=sarif-file" } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_ice (void); + +@@ -56,7 +57,7 @@ void test_inject_ice (void) + { dg-final { scan-sarif-file "\"contextRegion\": " } } + { dg-final { scan-sarif-file "\"artifactLocation\": " } } + { dg-final { scan-sarif-file "\"region\": " } } +- { dg-final { scan-sarif-file "\"startLine\": 8" } } ++ { dg-final { scan-sarif-file "\"startLine\": 9" } } + { dg-final { scan-sarif-file "\"startColumn\": 3" } } + { dg-final { scan-sarif-file "\"endColumn\": 16" } } + { dg-final { scan-sarif-file "\"message\": " } } +diff --git a/gcc/testsuite/gcc.dg/plugin/crash-test-ice-stderr.c b/gcc/testsuite/gcc.dg/plugin/crash-test-ice-stderr.c +index cee701b135c..0064d3bc447 100644 +--- a/gcc/testsuite/gcc.dg/plugin/crash-test-ice-stderr.c ++++ b/gcc/testsuite/gcc.dg/plugin/crash-test-ice-stderr.c +@@ -1,4 +1,5 @@ + /* { dg-do compile } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_ice (void); + +diff --git a/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c b/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c +index 57caa20155f..83b38d2ffb5 100644 +--- a/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c ++++ b/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ + /* { dg-options "-fdiagnostics-format=sarif-file" } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_write_through_null (void); + +@@ -56,7 +57,7 @@ void test_inject_write_through_null (void) + { dg-final { scan-sarif-file "\"contextRegion\": " } } + { dg-final { scan-sarif-file "\"artifactLocation\": " } } + { dg-final { scan-sarif-file "\"region\": " } } +- { dg-final { scan-sarif-file "\"startLine\": 8" } } ++ { dg-final { scan-sarif-file "\"startLine\": 9" } } + { dg-final { scan-sarif-file "\"startColumn\": 3" } } + { dg-final { scan-sarif-file "\"endColumn\": 31" } } + { dg-final { scan-sarif-file "\"message\": " } } +diff --git a/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-stderr.c b/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-stderr.c +index 7b43e423633..a9a211a3b1f 100644 +--- a/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-stderr.c ++++ b/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-stderr.c +@@ -1,4 +1,5 @@ + /* { dg-do compile } */ ++/* { dg-additional-options "-fno-report-bug" } */ + + extern void inject_write_through_null (void); + + +base-commit: 070a6bf0bdc6761ad77ac97404c98f00a7007d54 +-- +2.41.0 +