241 lines
9.3 KiB
Diff
241 lines
9.3 KiB
Diff
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commit ffdd377fc07cdc7b62669d354e23f30940eaaffe
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Author: Kewen Lin <linkw@linux.ibm.com>
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Date: Wed Jun 26 02:16:17 2024 -0500
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rs6000: Fix wrong RTL patterns for vector merge high/low char on LE
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Commit r12-4496 changes some define_expands and define_insns
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for vector merge high/low char, which are altivec_vmrg[hl]b.
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These defines are mainly for built-in function vec_merge{h,l}
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and some internal gen function needs. These functions should
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consider endianness, taking vec_mergeh as example, as PVIPR
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defines, vec_mergeh "Merges the first halves (in element order)
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of two vectors", it does note it's in element order. So it's
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mapped into vmrghb on BE while vmrglb on LE respectively.
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Although the mapped insns are different, as the discussion in
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PR106069, the RTL pattern should be still the same, it is
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conformed before commit r12-4496, but gets changed into
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different patterns on BE and LE starting from commit r12-4496.
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Similar to 32-bit element case in commit log of r15-1504, this
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8-bit element pattern on LE doesn't actually match what the
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underlying insn is intended to represent, once some optimization
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like combine does some changes basing on it, it would cause
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the unexpected consequence. The newly constructed test case
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pr106069-1.c is a typical example for this issue.
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So this patch is to fix the wrong RTL pattern, ensure the
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associated RTL patterns become the same as before which can
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have the same semantic as their mapped insns. With the
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proposed patch, the expanders like altivec_vmrghb expands
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into altivec_vmrghb_direct_be or altivec_vmrglb_direct_le
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depending on endianness, "direct" can easily show which
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insn would be generated, _be and _le are mainly for the
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different RTL patterns as endianness.
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Co-authored-by: Xionghu Luo <xionghuluo@tencent.com>
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PR target/106069
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PR target/115355
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gcc/ChangeLog:
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* config/rs6000/altivec.md (altivec_vmrghb_direct): Rename to ...
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(altivec_vmrghb_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.
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(altivec_vmrghb_direct_le): New define_insn.
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(altivec_vmrglb_direct): Rename to ...
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(altivec_vmrglb_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.
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(altivec_vmrglb_direct_le): New define_insn.
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(altivec_vmrghb): Adjust by calling gen_altivec_vmrghb_direct_be
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for BE and gen_altivec_vmrglb_direct_le for LE.
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(altivec_vmrglb): Adjust by calling gen_altivec_vmrglb_direct_be
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for BE and gen_altivec_vmrghb_direct_le for LE.
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* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
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CODE_FOR_altivec_vmrghb_direct by
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CODE_FOR_altivec_vmrghb_direct_be for BE and
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CODE_FOR_altivec_vmrghb_direct_le for LE. And replace
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CODE_FOR_altivec_vmrglb_direct by
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CODE_FOR_altivec_vmrglb_direct_be for BE and
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CODE_FOR_altivec_vmrglb_direct_le for LE.
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gcc/testsuite/ChangeLog:
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* gcc.target/powerpc/pr106069-1.c: New test.
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(cherry picked from commit 62520e4e9f7e2fe8a16ee57a4bd35da2e921ae22)
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diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
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index 92e2e4a4090..47664204bc5 100644
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--- a/gcc/config/rs6000/altivec.md
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+++ b/gcc/config/rs6000/altivec.md
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@@ -1152,15 +1152,16 @@ (define_expand "altivec_vmrghb"
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(use (match_operand:V16QI 2 "register_operand"))]
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"TARGET_ALTIVEC"
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{
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- rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrghb_direct
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- : gen_altivec_vmrglb_direct;
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- if (!BYTES_BIG_ENDIAN)
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- std::swap (operands[1], operands[2]);
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- emit_insn (fun (operands[0], operands[1], operands[2]));
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+ if (BYTES_BIG_ENDIAN)
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+ emit_insn (
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+ gen_altivec_vmrghb_direct_be (operands[0], operands[1], operands[2]));
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+ else
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+ emit_insn (
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+ gen_altivec_vmrglb_direct_le (operands[0], operands[2], operands[1]));
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DONE;
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})
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-(define_insn "altivec_vmrghb_direct"
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+(define_insn "altivec_vmrghb_direct_be"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(vec_select:V16QI
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(vec_concat:V32QI
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@@ -1174,7 +1175,25 @@ (define_insn "altivec_vmrghb_direct"
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(const_int 5) (const_int 21)
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(const_int 6) (const_int 22)
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(const_int 7) (const_int 23)])))]
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- "TARGET_ALTIVEC"
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+ "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
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+ "vmrghb %0,%1,%2"
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+ [(set_attr "type" "vecperm")])
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+
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+(define_insn "altivec_vmrghb_direct_le"
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+ [(set (match_operand:V16QI 0 "register_operand" "=v")
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+ (vec_select:V16QI
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+ (vec_concat:V32QI
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+ (match_operand:V16QI 2 "register_operand" "v")
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+ (match_operand:V16QI 1 "register_operand" "v"))
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+ (parallel [(const_int 8) (const_int 24)
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+ (const_int 9) (const_int 25)
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+ (const_int 10) (const_int 26)
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+ (const_int 11) (const_int 27)
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+ (const_int 12) (const_int 28)
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+ (const_int 13) (const_int 29)
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+ (const_int 14) (const_int 30)
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+ (const_int 15) (const_int 31)])))]
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+ "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
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"vmrghb %0,%1,%2"
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[(set_attr "type" "vecperm")])
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@@ -1274,15 +1293,16 @@ (define_expand "altivec_vmrglb"
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(use (match_operand:V16QI 2 "register_operand"))]
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"TARGET_ALTIVEC"
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{
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- rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrglb_direct
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- : gen_altivec_vmrghb_direct;
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- if (!BYTES_BIG_ENDIAN)
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- std::swap (operands[1], operands[2]);
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- emit_insn (fun (operands[0], operands[1], operands[2]));
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+ if (BYTES_BIG_ENDIAN)
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+ emit_insn (
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+ gen_altivec_vmrglb_direct_be (operands[0], operands[1], operands[2]));
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+ else
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+ emit_insn (
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+ gen_altivec_vmrghb_direct_le (operands[0], operands[2], operands[1]));
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DONE;
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})
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-(define_insn "altivec_vmrglb_direct"
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+(define_insn "altivec_vmrglb_direct_be"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(vec_select:V16QI
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(vec_concat:V32QI
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@@ -1296,7 +1316,25 @@ (define_insn "altivec_vmrglb_direct"
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(const_int 13) (const_int 29)
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(const_int 14) (const_int 30)
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(const_int 15) (const_int 31)])))]
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- "TARGET_ALTIVEC"
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+ "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
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+ "vmrglb %0,%1,%2"
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+ [(set_attr "type" "vecperm")])
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+
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+(define_insn "altivec_vmrglb_direct_le"
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+ [(set (match_operand:V16QI 0 "register_operand" "=v")
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+ (vec_select:V16QI
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+ (vec_concat:V32QI
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+ (match_operand:V16QI 2 "register_operand" "v")
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+ (match_operand:V16QI 1 "register_operand" "v"))
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+ (parallel [(const_int 0) (const_int 16)
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+ (const_int 1) (const_int 17)
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+ (const_int 2) (const_int 18)
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+ (const_int 3) (const_int 19)
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+ (const_int 4) (const_int 20)
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+ (const_int 5) (const_int 21)
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+ (const_int 6) (const_int 22)
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+ (const_int 7) (const_int 23)])))]
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+ "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
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"vmrglb %0,%1,%2"
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[(set_attr "type" "vecperm")])
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diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
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index b3d648312f1..10088033aa1 100644
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--- a/gcc/config/rs6000/rs6000.cc
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+++ b/gcc/config/rs6000/rs6000.cc
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@@ -23166,8 +23166,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
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CODE_FOR_altivec_vpkuwum_direct,
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{2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31}},
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{OPTION_MASK_ALTIVEC,
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- BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
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- : CODE_FOR_altivec_vmrglb_direct,
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+ BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct_be
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+ : CODE_FOR_altivec_vmrglb_direct_le,
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{0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}},
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{OPTION_MASK_ALTIVEC,
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BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
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@@ -23178,8 +23178,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
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: CODE_FOR_altivec_vmrglw_direct_v4si_le,
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{0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}},
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{OPTION_MASK_ALTIVEC,
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- BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
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- : CODE_FOR_altivec_vmrghb_direct,
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+ BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct_be
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+ : CODE_FOR_altivec_vmrghb_direct_le,
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{8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31}},
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{OPTION_MASK_ALTIVEC,
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BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
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diff --git a/gcc/testsuite/gcc.target/powerpc/pr106069-1.c b/gcc/testsuite/gcc.target/powerpc/pr106069-1.c
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new file mode 100644
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index 00000000000..4945d8fedfb
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/powerpc/pr106069-1.c
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@@ -0,0 +1,39 @@
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+/* { dg-do run } */
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+/* { dg-options "-O2" } */
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+/* { dg-require-effective-target vmx_hw } */
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+
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+/* Test vector merge for 8-bit element size,
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+ it will abort if the RTL pattern isn't expected. */
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+
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+#include "altivec.h"
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+
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+__attribute__((noipa))
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+signed char elem_6 (vector signed char a, vector signed char b)
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+{
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+ vector signed char c = vec_mergeh (a,b);
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+ return vec_extract (c, 6);
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+}
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+
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+__attribute__((noipa))
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+unsigned char elem_15 (vector unsigned char a, vector unsigned char b)
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+{
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+ vector unsigned char c = vec_mergel (a,b);
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+ return vec_extract (c, 15);
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+}
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+
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+int
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+main ()
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+{
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+ vector unsigned char v1
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+ = {3, 33, 22, 12, 34, 14, 5, 25, 30, 11, 0, 21, 17, 27, 38, 8};
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+ vector unsigned char v2
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+ = {81, 82, 83, 84, 68, 67, 66, 65, 99, 100, 101, 102, 250, 125, 0, 6};
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+ signed char x1 = elem_6 ((vector signed char) v1, (vector signed char) v2);
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+ unsigned char x2 = elem_15 (v1, v2);
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+
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+ if (x1 != 12 || x2 != 6)
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+ __builtin_abort ();
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+
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+ return 0;
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+}
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+
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