commit 82935703e4151219386c6caa53c989ffac96af49 Author: CentOS Sources Date: Tue Oct 5 07:55:04 2021 -0400 import gcc-toolset-11-valgrind-3.17.0-6.el8 diff --git a/.gcc-toolset-11-valgrind.metadata b/.gcc-toolset-11-valgrind.metadata new file mode 100644 index 0000000..c47f2af --- /dev/null +++ b/.gcc-toolset-11-valgrind.metadata @@ -0,0 +1 @@ +7770912c7465f93a90c5a9d5c1b1b036ebec04fd SOURCES/valgrind-3.17.0.tar.bz2 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..8036c6c --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +SOURCES/valgrind-3.17.0.tar.bz2 diff --git a/SOURCES/valgrind-3.16.0-some-Wl-z-now.patch b/SOURCES/valgrind-3.16.0-some-Wl-z-now.patch new file mode 100644 index 0000000..79c3662 --- /dev/null +++ b/SOURCES/valgrind-3.16.0-some-Wl-z-now.patch @@ -0,0 +1,72 @@ +commit d3c977726064ba09fed6dfc7daf22b16824c97b4 +Author: Mark Wielaard +Date: Fri May 24 18:24:56 2019 +0200 + + Add -Wl,-z,now to some binaries. + +diff --git a/auxprogs/Makefile.am b/auxprogs/Makefile.am +index 1b7842b..e211eec 100644 +--- a/auxprogs/Makefile.am ++++ b/auxprogs/Makefile.am +@@ -32,7 +32,7 @@ valgrind_listener_SOURCES = valgrind-listener.c + valgrind_listener_CPPFLAGS = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind + valgrind_listener_CFLAGS = $(AM_CFLAGS_PRI) -fstack-protector-strong + valgrind_listener_CCASFLAGS = $(AM_CCASFLAGS_PRI) +-valgrind_listener_LDFLAGS = $(AM_CFLAGS_PRI) ++valgrind_listener_LDFLAGS = $(AM_CFLAGS_PRI) -Wl,-z,now + if VGCONF_PLATVARIANT_IS_ANDROID + valgrind_listener_CFLAGS += -static + endif +@@ -51,7 +51,7 @@ valgrind_di_server_SOURCES = valgrind-di-server.c + valgrind_di_server_CPPFLAGS = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind + valgrind_di_server_CFLAGS = $(AM_CFLAGS_PRI) -fstack-protector-strong + valgrind_di_server_CCASFLAGS = $(AM_CCASFLAGS_PRI) +-valgrind_di_server_LDFLAGS = $(AM_CFLAGS_PRI) ++valgrind_di_server_LDFLAGS = $(AM_CFLAGS_PRI) -Wl,-z,now + if VGCONF_PLATVARIANT_IS_ANDROID + valgrind_di_server_CFLAGS += -static + endif +@@ -86,7 +86,7 @@ getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = getoff.c + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) -fstack-protector-strong + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CCASFLAGS = $(AM_CCASFLAGS_PRI) +-getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ ++getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ -Wl,-z,now + if HAVE_DLINFO_RTLD_DI_TLS_MODID + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = $(LDADD) -ldl + endif +diff --git a/cachegrind/Makefile.am b/cachegrind/Makefile.am +index f572741..1c07e50 100644 +--- a/cachegrind/Makefile.am ++++ b/cachegrind/Makefile.am +@@ -27,7 +27,7 @@ cg_merge_SOURCES = cg_merge.c + cg_merge_CPPFLAGS = $(AM_CPPFLAGS_PRI) + cg_merge_CFLAGS = $(AM_CFLAGS_PRI) -fstack-protector-strong + cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI) +-cg_merge_LDFLAGS = $(AM_CFLAGS_PRI) ++cg_merge_LDFLAGS = $(AM_CFLAGS_PRI) -Wl,-z,now + # If there is no secondary platform, and the platforms include x86-darwin, + # then the primary platform must be x86-darwin. Hence: + if ! VGCONF_HAVE_PLATFORM_SEC +diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am +index 3c73210..fb6b7bb 100644 +--- a/coregrind/Makefile.am ++++ b/coregrind/Makefile.am +@@ -57,7 +57,7 @@ RANLIB = ${LTO_RANLIB} + valgrind_CPPFLAGS = $(AM_CPPFLAGS_PRI) + valgrind_CFLAGS = $(AM_CFLAGS_PRI) $(LTO_CFLAGS) -fstack-protector-strong + valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI) +-valgrind_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ ++valgrind_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ -Wl,-z,now + # If there is no secondary platform, and the platforms include x86-darwin, + # then the primary platform must be x86-darwin. Hence: + if ! VGCONF_HAVE_PLATFORM_SEC +@@ -96,7 +96,7 @@ endif + vgdb_CPPFLAGS = $(AM_CPPFLAGS_PRI) + vgdb_CFLAGS = $(AM_CFLAGS_PRI) $(LTO_CFLAGS) -fstack-protector-strong + vgdb_CCASFLAGS = $(AM_CCASFLAGS_PRI) +-vgdb_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ ++vgdb_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ -Wl,-z,now + if VGCONF_PLATVARIANT_IS_ANDROID + vgdb_CFLAGS += -static + endif diff --git a/SOURCES/valgrind-3.16.0-some-stack-protector.patch b/SOURCES/valgrind-3.16.0-some-stack-protector.patch new file mode 100644 index 0000000..324c7d3 --- /dev/null +++ b/SOURCES/valgrind-3.16.0-some-stack-protector.patch @@ -0,0 +1,118 @@ +commit b73fb7a614e1b5d60af23fb0752b5cead995e02e +Author: Mark Wielaard +Date: Sun Apr 14 00:30:05 2019 +0200 + + Remove no-stack-protector, add stack-protector-strong to some. + +diff --git a/auxprogs/Makefile.am b/auxprogs/Makefile.am +index 56cc5ef..1b7842b 100644 +--- a/auxprogs/Makefile.am ++++ b/auxprogs/Makefile.am +@@ -30,7 +30,7 @@ bin_PROGRAMS = valgrind-listener valgrind-di-server + + valgrind_listener_SOURCES = valgrind-listener.c + valgrind_listener_CPPFLAGS = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind +-valgrind_listener_CFLAGS = $(AM_CFLAGS_PRI) ++valgrind_listener_CFLAGS = $(AM_CFLAGS_PRI) -fstack-protector-strong + valgrind_listener_CCASFLAGS = $(AM_CCASFLAGS_PRI) + valgrind_listener_LDFLAGS = $(AM_CFLAGS_PRI) + if VGCONF_PLATVARIANT_IS_ANDROID +@@ -49,7 +49,7 @@ endif + + valgrind_di_server_SOURCES = valgrind-di-server.c + valgrind_di_server_CPPFLAGS = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind +-valgrind_di_server_CFLAGS = $(AM_CFLAGS_PRI) ++valgrind_di_server_CFLAGS = $(AM_CFLAGS_PRI) -fstack-protector-strong + valgrind_di_server_CCASFLAGS = $(AM_CCASFLAGS_PRI) + valgrind_di_server_LDFLAGS = $(AM_CFLAGS_PRI) + if VGCONF_PLATVARIANT_IS_ANDROID +@@ -84,7 +84,7 @@ endif + + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = getoff.c + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +-getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) ++getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) -fstack-protector-strong + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CCASFLAGS = $(AM_CCASFLAGS_PRI) + getoff_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ + if HAVE_DLINFO_RTLD_DI_TLS_MODID +diff --git a/cachegrind/Makefile.am b/cachegrind/Makefile.am +index f8447a1..f572741 100644 +--- a/cachegrind/Makefile.am ++++ b/cachegrind/Makefile.am +@@ -25,7 +25,7 @@ bin_PROGRAMS = cg_merge + + cg_merge_SOURCES = cg_merge.c + cg_merge_CPPFLAGS = $(AM_CPPFLAGS_PRI) +-cg_merge_CFLAGS = $(AM_CFLAGS_PRI) ++cg_merge_CFLAGS = $(AM_CFLAGS_PRI) -fstack-protector-strong + cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI) + cg_merge_LDFLAGS = $(AM_CFLAGS_PRI) + # If there is no secondary platform, and the platforms include x86-darwin, +diff --git a/configure.ac b/configure.ac +index f8c798b..ccc8f52 100755 +--- a/configure.ac ++++ b/configure.ac +@@ -2352,24 +2352,24 @@ + AM_CONDITIONAL([HAVE_ALIGNED_CXX_ALLOC], [test x$ac_have_aligned_cxx_alloc = xyes]) + + # does this compiler support -fno-stack-protector ? +-AC_MSG_CHECKING([if gcc accepts -fno-stack-protector]) +- +-safe_CFLAGS=$CFLAGS +-CFLAGS="-fno-stack-protector -Werror" +- +-AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ +- return 0; +-]])], [ +-no_stack_protector=yes +-FLAG_FNO_STACK_PROTECTOR="-fno-stack-protector" +-AC_MSG_RESULT([yes]) +-], [ +-no_stack_protector=no ++#AC_MSG_CHECKING([if gcc accepts -fno-stack-protector]) ++# ++#safe_CFLAGS=$CFLAGS ++#CFLAGS="-fno-stack-protector -Werror" ++# ++#AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ ++# return 0; ++#]])], [ ++#no_stack_protector=yes ++#FLAG_FNO_STACK_PROTECTOR="-fno-stack-protector" ++#AC_MSG_RESULT([yes]) ++#], [ ++#no_stack_protector=no + FLAG_FNO_STACK_PROTECTOR="" +-AC_MSG_RESULT([no]) +-]) +-CFLAGS=$safe_CFLAGS +- ++#AC_MSG_RESULT([no]) ++#]) ++#CFLAGS=$safe_CFLAGS ++# + AC_SUBST(FLAG_FNO_STACK_PROTECTOR) + + # does this compiler support -finline-functions ? +diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am +index 94030fd..3c73210 100644 +--- a/coregrind/Makefile.am ++++ b/coregrind/Makefile.am +@@ -55,7 +55,7 @@ AR = ${LTO_AR} + RANLIB = ${LTO_RANLIB} + + valgrind_CPPFLAGS = $(AM_CPPFLAGS_PRI) +-valgrind_CFLAGS = $(AM_CFLAGS_PRI) $(LTO_CFLAGS) ++valgrind_CFLAGS = $(AM_CFLAGS_PRI) $(LTO_CFLAGS) -fstack-protector-strong + valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI) + valgrind_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ + # If there is no secondary platform, and the platforms include x86-darwin, +@@ -94,7 +94,7 @@ vgdb_SOURCES += vgdb-invoker-solaris.c + endif + + vgdb_CPPFLAGS = $(AM_CPPFLAGS_PRI) +-vgdb_CFLAGS = $(AM_CFLAGS_PRI) $(LTO_CFLAGS) ++vgdb_CFLAGS = $(AM_CFLAGS_PRI) $(LTO_CFLAGS) -fstack-protector-strong + vgdb_CCASFLAGS = $(AM_CCASFLAGS_PRI) + vgdb_LDFLAGS = $(AM_CFLAGS_PRI) @LIB_UBSAN@ + if VGCONF_PLATVARIANT_IS_ANDROID diff --git a/SOURCES/valgrind-3.17.0-clone-parent-res.patch b/SOURCES/valgrind-3.17.0-clone-parent-res.patch new file mode 100644 index 0000000..8d03cea --- /dev/null +++ b/SOURCES/valgrind-3.17.0-clone-parent-res.patch @@ -0,0 +1,21 @@ +commit e08a82991a9b9dc87c13f2b89273f25f97d14baf +Author: Tom Hughes +Date: Tue Apr 6 22:44:36 2021 +0100 + + Only process clone results in the parent thread + + Fixes BZ#423963 + +diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c +index 5ae4e6613..c59d8ee26 100644 +--- a/coregrind/m_syswrap/syswrap-linux.c ++++ b/coregrind/m_syswrap/syswrap-linux.c +@@ -940,7 +940,7 @@ PRE(sys_clone) + ("Valgrind does not support general clone()."); + } + +- if (SUCCESS) { ++ if (SUCCESS && RES != 0) { + if (ARG_FLAGS & (VKI_CLONE_PARENT_SETTID | VKI_CLONE_PIDFD)) + POST_MEM_WRITE(ARG3, sizeof(Int)); + if (ARG_FLAGS & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) diff --git a/SOURCES/valgrind-3.17.0-debuginfod.patch b/SOURCES/valgrind-3.17.0-debuginfod.patch new file mode 100644 index 0000000..5109a4b --- /dev/null +++ b/SOURCES/valgrind-3.17.0-debuginfod.patch @@ -0,0 +1,30 @@ +commit 93104368952c37268da724231487058ea3eaf1dc +Author: Tom Hughes +Date: Thu May 20 17:16:06 2021 +0100 + + Don't look for separate debuginfo if the image has a .debug_info section + + Fixes BZ#435908 + +diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c +index b0f062ddc..e424e3e7e 100644 +--- a/coregrind/m_debuginfo/readelf.c ++++ b/coregrind/m_debuginfo/readelf.c +@@ -2879,13 +2879,15 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) + /* Look for a build-id */ + HChar* buildid = find_buildid(mimg, False, False); + +- /* Look for a debug image that matches either the build-id or ++ /* If we don't have a .debug_info section in the main image then ++ look for a debug image that matches either the build-id or + the debuglink-CRC32 in the main image. If the main image + doesn't contain either of those then this won't even bother + to try looking. This looks in all known places, including + the --extra-debuginfo-path if specified and on the + --debuginfo-server if specified. */ +- if (buildid != NULL || debuglink_escn.img != NULL) { ++ if (debug_info_escn.img == NULL && ++ (buildid != NULL || debuglink_escn.img != NULL)) { + /* Do have a debuglink section? */ + if (debuglink_escn.img != NULL) { + UInt crc_offset diff --git a/SOURCES/valgrind-3.17.0-ppc64-isa-3.1-tests.patch b/SOURCES/valgrind-3.17.0-ppc64-isa-3.1-tests.patch new file mode 100644 index 0000000..b7f1a6c --- /dev/null +++ b/SOURCES/valgrind-3.17.0-ppc64-isa-3.1-tests.patch @@ -0,0 +1,1712 @@ +commit 4bcc6c8a97c10c4dd41b35bd3b3035ec4037d524 +Author: Carl Love +Date: Mon Nov 16 19:09:47 2020 -0600 + + VSX Permute Control Vector Generate Operation tests. + +diff --git a/NEWS b/NEWS +index aa398cf54..2e42e74b2 100644 +--- a/NEWS ++++ b/NEWS +@@ -154,6 +154,7 @@ where XXXXXX is the bug number as listed below. + 428909 helgrind: need to intercept duplicate libc definitions for Fedora 33 + 429352 PPC ISA 3.1 support is missing, part 7 + 429354 PPC ISA 3.1 support is missing, part 8 ++429375 PPC ISA 3.1 support is missing, part 9 + 429692 unhandled ppc64le-linux syscall: 147 (getsid) + 429864 s390x: C++ atomic test_and_set yields false-positive memcheck + diagnostics +diff --git a/none/tests/ppc64/test_isa_3_1_XT.c b/none/tests/ppc64/test_isa_3_1_XT.c +index c16ddedac..a54e8763a 100644 +--- a/none/tests/ppc64/test_isa_3_1_XT.c ++++ b/none/tests/ppc64/test_isa_3_1_XT.c +@@ -491,6 +491,54 @@ static void test_pstxv_4 (void) { + static void test_pstxv_0 (void) { + __asm__ __volatile__ ("pstxv %x0, 0(%1), 0" :: "wa" (vec_xs), "r" (ra) ); + } ++static void test_xxgenpcvbm_imm0 (void) { ++ __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvbm_imm1 (void) { ++ __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvbm_imm2 (void) { ++ __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvbm_imm3 (void) { ++ __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvhm_imm0 (void) { ++ __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvhm_imm1 (void) { ++ __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvhm_imm2 (void) { ++ __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvhm_imm3 (void) { ++ __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvwm_imm0 (void) { ++ __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvwm_imm1 (void) { ++ __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvwm_imm2 (void) { ++ __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvwm_imm3 (void) { ++ __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvdm_imm0 (void) { ++ __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvdm_imm1 (void) { ++ __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvdm_imm2 (void) { ++ __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); ++} ++static void test_xxgenpcvdm_imm3 (void) { ++ __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); ++} + + static test_list_t testgroup_generic[] = { + { &test_lxvkq_imm1, "lxvkq imm1", "XT,UIM"}, /* bcwp */ +@@ -592,6 +640,22 @@ static test_list_t testgroup_generic[] = { + { &test_xxblendvw, "xxblendvw", "XT,XA,XB,XC"}, /* bcs */ + { &test_xxeval_imm0, "xxeval imm0", "XT,XA,XB,XC,IMM"}, /* bcwp */ + { &test_xxeval_imm3, "xxeval imm3", "XT,XA,XB,XC,IMM"}, /* bcwp */ ++ { &test_xxgenpcvbm_imm0, "xxgenpcvbm imm0", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvbm_imm1, "xxgenpcvbm imm1", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvbm_imm2, "xxgenpcvbm imm2", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvbm_imm3, "xxgenpcvbm imm3", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvdm_imm0, "xxgenpcvdm imm0", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvdm_imm1, "xxgenpcvdm imm1", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvdm_imm2, "xxgenpcvdm imm2", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvdm_imm3, "xxgenpcvdm imm3", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvhm_imm0, "xxgenpcvhm imm0", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvhm_imm1, "xxgenpcvhm imm1", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvhm_imm2, "xxgenpcvhm imm2", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvhm_imm3, "xxgenpcvhm imm3", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvwm_imm0, "xxgenpcvwm imm0", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvwm_imm1, "xxgenpcvwm imm1", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvwm_imm2, "xxgenpcvwm imm2", "XT,VRB,IMM"}, /* bcwp */ ++ { &test_xxgenpcvwm_imm3, "xxgenpcvwm imm3", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxpermx_imm0, "xxpermx imm0", "XT,XA,XB,XC,UIM"}, /* bcwp */ + { &test_xxpermx_imm3, "xxpermx imm3", "XT,XA,XB,XC,UIM"}, /* bcwp */ + { &test_xxsplti32dx_ix0_imm0xa5a5a5a5, "xxsplti32dx ix0_imm0xa5a5a5a5", "XT,IX,IMM32"}, /* bcwp */ +diff --git a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp +index efa95884e..8b5f1d1a3 100644 +--- a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp ++++ b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp +@@ -4644,6 +4644,230 @@ xxeval imm3 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 + xxeval imm3 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => 8000000000000000 7f800000ff800000 + xxeval imm3 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => 8000000000000000 7f800000ff800000 + ++xxgenpcvbm imm0 7f800000ff800000,ff8000007f800000 => 18031a1b04051e1f 1121314021617 ++xxgenpcvbm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 5061a1b1c071e1f 11010214150304 ++xxgenpcvbm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 31904051c1d0607 1000121301021617 ++xxgenpcvbm imm0 0080000e8080000e,0180055e0180077e => 18021a1b03041e1f 1000121314011617 ++xxgenpcvbm imm0 0180055e0180077e,0000111e8000222e => 18011a1b1c021e1f 1011121300151617 ++xxgenpcvbm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b011d1e1f 1000121314151617 ++xxgenpcvbm imm0 7ff0000000000000,fff0000000000000 => 18021a1b1c1d1e1f 1121314151617 ++xxgenpcvbm imm0 fff0000000000000,2208400000000000 => 11a1b1c1d1e1f 1011121314151617 ++xxgenpcvbm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 ++xxgenpcvbm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1121302151617 ++xxgenpcvbm imm0 ffff000180000001,0000000000000000 => 11a1b021d1e1f 1011121314151617 ++xxgenpcvbm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 11121314151617 ++xxgenpcvbm imm0 8000000000000000,7f800000ff800000 => 3191a1b1c1d1e1f 1000121301021617 ++ ++xxgenpcvbm imm1 7f800000ff800000,ff8000007f800000 => 0 105090c0d0000 ++xxgenpcvbm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 0 203060708090d ++xxgenpcvbm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 10405080a0b0e0f ++xxgenpcvbm imm1 0080000e8080000e,0180055e0180077e => 0 105090c0d000000 ++xxgenpcvbm imm1 0180055e0180077e,0000111e8000222e => 0 4090d0000000000 ++xxgenpcvbm imm1 0000111e8000222e,7ff0000000000000 => 0 10c000000000000 ++xxgenpcvbm imm1 7ff0000000000000,fff0000000000000 => 0 1090000000000 ++xxgenpcvbm imm1 fff0000000000000,2208400000000000 => 0 809000000000000 ++xxgenpcvbm imm1 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvbm imm1 0000000000000009,ffff000180000001 => 0 1040000000000 ++xxgenpcvbm imm1 ffff000180000001,0000000000000000 => 0 8090c0000000000 ++xxgenpcvbm imm1 0000000000000000,8000000000000000 => 0 0 ++xxgenpcvbm imm1 8000000000000000,7f800000ff800000 => 0 104050800000000 ++ ++xxgenpcvbm imm2 7f800000ff800000,ff8000007f800000 => 1702151401001110 5041d1c1b031918 ++xxgenpcvbm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 201151413001110 71e06051b1a0403 ++xxgenpcvbm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 416030213120100 1f071d1c06051918 ++xxgenpcvbm imm2 0080000e8080000e,0180055e0180077e => 1702151401001110 1f041d1c1b031918 ++xxgenpcvbm imm2 0180055e0180077e,0000111e8000222e => 1701151413001110 1f1e1d1c021a1918 ++xxgenpcvbm imm2 0000111e8000222e,7ff0000000000000 => 1716151400121110 1f011d1c1b1a1918 ++xxgenpcvbm imm2 7ff0000000000000,fff0000000000000 => 1700151413121110 2011d1c1b1a1918 ++xxgenpcvbm imm2 fff0000000000000,2208400000000000 => 100151413121110 1f1e1d1c1b1a1918 ++xxgenpcvbm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 ++xxgenpcvbm imm2 0000000000000009,ffff000180000001 => 1716151413121110 2011d1c001a1918 ++xxgenpcvbm imm2 ffff000180000001,0000000000000000 => 201151400121110 1f1e1d1c1b1a1918 ++xxgenpcvbm imm2 0000000000000000,8000000000000000 => 1716151413121110 1e1d1c1b1a1918 ++xxgenpcvbm imm2 8000000000000000,7f800000ff800000 => 16151413121110 1f031d1c02011918 ++ ++xxgenpcvbm imm3 7f800000ff800000,ff8000007f800000 => f0e0a060302 0 ++xxgenpcvbm imm3 ff8000007f800000,ff7ffffe7f7ffffe => f0d0c0908070602 0 ++xxgenpcvbm imm3 ff7ffffe7f7ffffe,0080000e8080000e => e0b0a0705040100 0 ++xxgenpcvbm imm3 0080000e8080000e,0180055e0180077e => e0a060302 0 ++xxgenpcvbm imm3 0180055e0180077e,0000111e8000222e => b0602 0 ++xxgenpcvbm imm3 0000111e8000222e,7ff0000000000000 => e03 0 ++xxgenpcvbm imm3 7ff0000000000000,fff0000000000000 => f0e06 0 ++xxgenpcvbm imm3 fff0000000000000,2208400000000000 => 706 0 ++xxgenpcvbm imm3 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvbm imm3 0000000000000009,ffff000180000001 => f0e0b 0 ++xxgenpcvbm imm3 ffff000180000001,0000000000000000 => 70603 0 ++xxgenpcvbm imm3 0000000000000000,8000000000000000 => f 0 ++xxgenpcvbm imm3 8000000000000000,7f800000ff800000 => e0b0a07 0 ++ ++xxgenpcvdm imm0 7f800000ff800000,ff8000007f800000 => 18191a1b1c1d1e1f 1020304050607 ++xxgenpcvdm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 8090a0b0c0d0e0f 1020304050607 ++xxgenpcvdm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 1020304050607 1011121314151617 ++xxgenpcvdm imm0 0080000e8080000e,0180055e0180077e => 18191a1b1c1d1e1f 1011121314151617 ++xxgenpcvdm imm0 0180055e0180077e,0000111e8000222e => 18191a1b1c1d1e1f 1011121314151617 ++xxgenpcvdm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b1c1d1e1f 1011121314151617 ++xxgenpcvdm imm0 7ff0000000000000,fff0000000000000 => 18191a1b1c1d1e1f 1020304050607 ++xxgenpcvdm imm0 fff0000000000000,2208400000000000 => 1020304050607 1011121314151617 ++xxgenpcvdm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 ++xxgenpcvdm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1020304050607 ++xxgenpcvdm imm0 ffff000180000001,0000000000000000 => 1020304050607 1011121314151617 ++xxgenpcvdm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 1020304050607 ++xxgenpcvdm imm0 8000000000000000,7f800000ff800000 => 1020304050607 1011121314151617 ++ ++xxgenpcvdm imm1 7f800000ff800000,ff8000007f800000 => 0 1020304050607 ++xxgenpcvdm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 8090a0b0c0d0e0f 1020304050607 ++xxgenpcvdm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 8090a0b0c0d0e0f ++xxgenpcvdm imm1 0080000e8080000e,0180055e0180077e => 0 0 ++xxgenpcvdm imm1 0180055e0180077e,0000111e8000222e => 0 0 ++xxgenpcvdm imm1 0000111e8000222e,7ff0000000000000 => 0 0 ++xxgenpcvdm imm1 7ff0000000000000,fff0000000000000 => 0 1020304050607 ++xxgenpcvdm imm1 fff0000000000000,2208400000000000 => 0 8090a0b0c0d0e0f ++xxgenpcvdm imm1 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvdm imm1 0000000000000009,ffff000180000001 => 0 1020304050607 ++xxgenpcvdm imm1 ffff000180000001,0000000000000000 => 0 8090a0b0c0d0e0f ++xxgenpcvdm imm1 0000000000000000,8000000000000000 => 0 1020304050607 ++xxgenpcvdm imm1 8000000000000000,7f800000ff800000 => 0 8090a0b0c0d0e0f ++ ++xxgenpcvdm imm2 7f800000ff800000,ff8000007f800000 => 1716151413121110 706050403020100 ++xxgenpcvdm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 706050403020100 f0e0d0c0b0a0908 ++xxgenpcvdm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 706050403020100 1f1e1d1c1b1a1918 ++xxgenpcvdm imm2 0080000e8080000e,0180055e0180077e => 1716151413121110 1f1e1d1c1b1a1918 ++xxgenpcvdm imm2 0180055e0180077e,0000111e8000222e => 1716151413121110 1f1e1d1c1b1a1918 ++xxgenpcvdm imm2 0000111e8000222e,7ff0000000000000 => 1716151413121110 1f1e1d1c1b1a1918 ++xxgenpcvdm imm2 7ff0000000000000,fff0000000000000 => 1716151413121110 706050403020100 ++xxgenpcvdm imm2 fff0000000000000,2208400000000000 => 706050403020100 1f1e1d1c1b1a1918 ++xxgenpcvdm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 ++xxgenpcvdm imm2 0000000000000009,ffff000180000001 => 1716151413121110 706050403020100 ++xxgenpcvdm imm2 ffff000180000001,0000000000000000 => 706050403020100 1f1e1d1c1b1a1918 ++xxgenpcvdm imm2 0000000000000000,8000000000000000 => 1716151413121110 706050403020100 ++xxgenpcvdm imm2 8000000000000000,7f800000ff800000 => 706050403020100 1f1e1d1c1b1a1918 ++ ++xxgenpcvdm imm3 7f800000ff800000,ff8000007f800000 => f0e0d0c0b0a0908 0 ++xxgenpcvdm imm3 ff8000007f800000,ff7ffffe7f7ffffe => 706050403020100 f0e0d0c0b0a0908 ++xxgenpcvdm imm3 ff7ffffe7f7ffffe,0080000e8080000e => 706050403020100 0 ++xxgenpcvdm imm3 0080000e8080000e,0180055e0180077e => 0 0 ++xxgenpcvdm imm3 0180055e0180077e,0000111e8000222e => 0 0 ++xxgenpcvdm imm3 0000111e8000222e,7ff0000000000000 => 0 0 ++xxgenpcvdm imm3 7ff0000000000000,fff0000000000000 => f0e0d0c0b0a0908 0 ++xxgenpcvdm imm3 fff0000000000000,2208400000000000 => 706050403020100 0 ++xxgenpcvdm imm3 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvdm imm3 0000000000000009,ffff000180000001 => f0e0d0c0b0a0908 0 ++xxgenpcvdm imm3 ffff000180000001,0000000000000000 => 706050403020100 0 ++xxgenpcvdm imm3 0000000000000000,8000000000000000 => f0e0d0c0b0a0908 0 ++xxgenpcvdm imm3 8000000000000000,7f800000ff800000 => 706050403020100 0 ++ ++xxgenpcvhm imm0 7f800000ff800000,ff8000007f800000 => 18191a1b02031e1f 1121314151617 ++xxgenpcvhm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 6071a1b1c1d1e1f 1020314150405 ++xxgenpcvhm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 20304051c1d0607 1011121300011617 ++xxgenpcvhm imm0 0080000e8080000e,0180055e0180077e => 18191a1b00011e1f 1011121314151617 ++xxgenpcvhm imm0 0180055e0180077e,0000111e8000222e => 18191a1b1c1d1e1f 1011121300011617 ++xxgenpcvhm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b00011e1f 1011121314151617 ++xxgenpcvhm imm0 7ff0000000000000,fff0000000000000 => 18191a1b1c1d1e1f 1121314151617 ++xxgenpcvhm imm0 fff0000000000000,2208400000000000 => 11a1b1c1d1e1f 1011121314151617 ++xxgenpcvhm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 ++xxgenpcvhm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1121302031617 ++xxgenpcvhm imm0 ffff000180000001,0000000000000000 => 11a1b02031e1f 1011121314151617 ++xxgenpcvhm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 1121314151617 ++xxgenpcvhm imm0 8000000000000000,7f800000ff800000 => 2031a1b1c1d1e1f 1011121300011617 ++ ++xxgenpcvhm imm1 7f800000ff800000,ff8000007f800000 => 0 10c0d00000000 ++xxgenpcvhm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 0 1020306070809 ++xxgenpcvhm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 40508090a0b0e0f ++xxgenpcvhm imm1 0080000e8080000e,0180055e0180077e => 0 c0d000000000000 ++xxgenpcvhm imm1 0180055e0180077e,0000111e8000222e => 0 405000000000000 ++xxgenpcvhm imm1 0000111e8000222e,7ff0000000000000 => 0 c0d000000000000 ++xxgenpcvhm imm1 7ff0000000000000,fff0000000000000 => 0 1000000000000 ++xxgenpcvhm imm1 fff0000000000000,2208400000000000 => 0 809000000000000 ++xxgenpcvhm imm1 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvhm imm1 0000000000000009,ffff000180000001 => 0 1040500000000 ++xxgenpcvhm imm1 ffff000180000001,0000000000000000 => 0 8090c0d00000000 ++xxgenpcvhm imm1 0000000000000000,8000000000000000 => 0 1000000000000 ++xxgenpcvhm imm1 8000000000000000,7f800000ff800000 => 0 405080900000000 ++ ++xxgenpcvhm imm2 7f800000ff800000,ff8000007f800000 => 1716151401001110 3021d1c1b1a1918 ++xxgenpcvhm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 100151413121110 70605041b1a0302 ++xxgenpcvhm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 504030213120100 1f1e1d1c07061918 ++xxgenpcvhm imm2 0080000e8080000e,0180055e0180077e => 1716151401001110 1f1e1d1c1b1a1918 ++xxgenpcvhm imm2 0180055e0180077e,0000111e8000222e => 1716151413121110 1f1e1d1c01001918 ++xxgenpcvhm imm2 0000111e8000222e,7ff0000000000000 => 1716151401001110 1f1e1d1c1b1a1918 ++xxgenpcvhm imm2 7ff0000000000000,fff0000000000000 => 1716151413121110 1001d1c1b1a1918 ++xxgenpcvhm imm2 fff0000000000000,2208400000000000 => 100151413121110 1f1e1d1c1b1a1918 ++xxgenpcvhm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 ++xxgenpcvhm imm2 0000000000000009,ffff000180000001 => 1716151413121110 3021d1c01001918 ++xxgenpcvhm imm2 ffff000180000001,0000000000000000 => 302151401001110 1f1e1d1c1b1a1918 ++xxgenpcvhm imm2 0000000000000000,8000000000000000 => 1716151413121110 1001d1c1b1a1918 ++xxgenpcvhm imm2 8000000000000000,7f800000ff800000 => 100151413121110 1f1e1d1c03021918 ++ ++xxgenpcvhm imm3 7f800000ff800000,ff8000007f800000 => f0e0302 0 ++xxgenpcvhm imm3 ff8000007f800000,ff7ffffe7f7ffffe => f0e0d0c09080706 0 ++xxgenpcvhm imm3 ff7ffffe7f7ffffe,0080000e8080000e => b0a070605040100 0 ++xxgenpcvhm imm3 0080000e8080000e,0180055e0180077e => 302 0 ++xxgenpcvhm imm3 0180055e0180077e,0000111e8000222e => b0a 0 ++xxgenpcvhm imm3 0000111e8000222e,7ff0000000000000 => 302 0 ++xxgenpcvhm imm3 7ff0000000000000,fff0000000000000 => f0e 0 ++xxgenpcvhm imm3 fff0000000000000,2208400000000000 => 706 0 ++xxgenpcvhm imm3 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvhm imm3 0000000000000009,ffff000180000001 => f0e0b0a 0 ++xxgenpcvhm imm3 ffff000180000001,0000000000000000 => 7060302 0 ++xxgenpcvhm imm3 0000000000000000,8000000000000000 => f0e 0 ++xxgenpcvhm imm3 8000000000000000,7f800000ff800000 => b0a0706 0 ++ ++xxgenpcvwm imm0 7f800000ff800000,ff8000007f800000 => 18191a1b04050607 1020314151617 ++xxgenpcvwm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 40506071c1d1e1f 1020314151617 ++xxgenpcvwm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 40506071c1d1e1f 1011121300010203 ++xxgenpcvwm imm0 0080000e8080000e,0180055e0180077e => 18191a1b00010203 1011121314151617 ++xxgenpcvwm imm0 0180055e0180077e,0000111e8000222e => 18191a1b1c1d1e1f 1011121300010203 ++xxgenpcvwm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b00010203 1011121314151617 ++xxgenpcvwm imm0 7ff0000000000000,fff0000000000000 => 18191a1b1c1d1e1f 1020314151617 ++xxgenpcvwm imm0 fff0000000000000,2208400000000000 => 102031c1d1e1f 1011121314151617 ++xxgenpcvwm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 ++xxgenpcvwm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1020304050607 ++xxgenpcvwm imm0 ffff000180000001,0000000000000000 => 1020304050607 1011121314151617 ++xxgenpcvwm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 1020314151617 ++xxgenpcvwm imm0 8000000000000000,7f800000ff800000 => 40506071c1d1e1f 1011121300010203 ++ ++xxgenpcvwm imm1 7f800000ff800000,ff8000007f800000 => 0 102030c0d0e0f ++xxgenpcvwm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 0 1020308090a0b ++xxgenpcvwm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 405060708090a0b ++xxgenpcvwm imm1 0080000e8080000e,0180055e0180077e => 0 c0d0e0f00000000 ++xxgenpcvwm imm1 0180055e0180077e,0000111e8000222e => 0 405060700000000 ++xxgenpcvwm imm1 0000111e8000222e,7ff0000000000000 => 0 c0d0e0f00000000 ++xxgenpcvwm imm1 7ff0000000000000,fff0000000000000 => 0 1020300000000 ++xxgenpcvwm imm1 fff0000000000000,2208400000000000 => 0 8090a0b00000000 ++xxgenpcvwm imm1 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvwm imm1 0000000000000009,ffff000180000001 => 0 1020304050607 ++xxgenpcvwm imm1 ffff000180000001,0000000000000000 => 0 8090a0b0c0d0e0f ++xxgenpcvwm imm1 0000000000000000,8000000000000000 => 0 1020300000000 ++xxgenpcvwm imm1 8000000000000000,7f800000ff800000 => 0 405060708090a0b ++ ++xxgenpcvwm imm2 7f800000ff800000,ff8000007f800000 => 1716151403020100 70605041b1a1918 ++xxgenpcvwm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 302010013121110 70605041b1a1918 ++xxgenpcvwm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 302010013121110 1f1e1d1c07060504 ++xxgenpcvwm imm2 0080000e8080000e,0180055e0180077e => 1716151403020100 1f1e1d1c1b1a1918 ++xxgenpcvwm imm2 0180055e0180077e,0000111e8000222e => 1716151413121110 1f1e1d1c03020100 ++xxgenpcvwm imm2 0000111e8000222e,7ff0000000000000 => 1716151403020100 1f1e1d1c1b1a1918 ++xxgenpcvwm imm2 7ff0000000000000,fff0000000000000 => 1716151413121110 30201001b1a1918 ++xxgenpcvwm imm2 fff0000000000000,2208400000000000 => 302010013121110 1f1e1d1c1b1a1918 ++xxgenpcvwm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 ++xxgenpcvwm imm2 0000000000000009,ffff000180000001 => 1716151413121110 706050403020100 ++xxgenpcvwm imm2 ffff000180000001,0000000000000000 => 706050403020100 1f1e1d1c1b1a1918 ++xxgenpcvwm imm2 0000000000000000,8000000000000000 => 1716151413121110 30201001b1a1918 ++xxgenpcvwm imm2 8000000000000000,7f800000ff800000 => 302010013121110 1f1e1d1c07060504 ++ ++xxgenpcvwm imm3 7f800000ff800000,ff8000007f800000 => f0e0d0c03020100 0 ++xxgenpcvwm imm3 ff8000007f800000,ff7ffffe7f7ffffe => f0e0d0c07060504 0 ++xxgenpcvwm imm3 ff7ffffe7f7ffffe,0080000e8080000e => b0a090807060504 0 ++xxgenpcvwm imm3 0080000e8080000e,0180055e0180077e => 3020100 0 ++xxgenpcvwm imm3 0180055e0180077e,0000111e8000222e => b0a0908 0 ++xxgenpcvwm imm3 0000111e8000222e,7ff0000000000000 => 3020100 0 ++xxgenpcvwm imm3 7ff0000000000000,fff0000000000000 => f0e0d0c 0 ++xxgenpcvwm imm3 fff0000000000000,2208400000000000 => 7060504 0 ++xxgenpcvwm imm3 2208400000000000,0000000000000009 => 0 0 ++xxgenpcvwm imm3 0000000000000009,ffff000180000001 => f0e0d0c0b0a0908 0 ++xxgenpcvwm imm3 ffff000180000001,0000000000000000 => 706050403020100 0 ++xxgenpcvwm imm3 0000000000000000,8000000000000000 => f0e0d0c 0 ++xxgenpcvwm imm3 8000000000000000,7f800000ff800000 => b0a090807060504 0 ++ + xxpermx imm0 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffff0000ffff ffff0000ffff + xxpermx imm0 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffff0000ffff ffff0000ffff + xxpermx imm0 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffff0000ffff ffff0000ffff +@@ -7094,4 +7318,4 @@ xxspltiw imm3 => 300000003 300000003 + + xxspltiw imm8 => 800000008 800000008 + +-All done. Tested 142 different instruction groups ++All done. Tested 158 different instruction groups + +commit c8fa838be405d7ac43035dcf675bf490800c26ec +Author: root +Date: Fri Feb 12 15:59:32 2021 -0500 + + Reduced Precision bfloat16 outer product tests + +diff --git a/none/tests/ppc64/test_isa_3_1_AT.c b/none/tests/ppc64/test_isa_3_1_AT.c +index 1d6d42c61..fee76f8f4 100644 +--- a/none/tests/ppc64/test_isa_3_1_AT.c ++++ b/none/tests/ppc64/test_isa_3_1_AT.c +@@ -626,8 +626,228 @@ static void test_pmxvf64gernn_XM11_YM0 (void) { + static void test_pmxvf64gernn_XM11_YM1 (void) { + __asm__ __volatile__ ("pmxvf64gernn 4, 22, %x0, 11, 1" :: "wa" (vec_xa) ); + } ++static void test_xvbf16ger2 (void) { ++ __asm__ __volatile__ ("xvbf16ger2 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_xvbf16ger2nn (void) { ++ __asm__ __volatile__ ("xvbf16ger2nn 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_xvbf16ger2np (void) { ++ __asm__ __volatile__ ("xvbf16ger2np 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_xvbf16ger2pn (void) { ++ __asm__ __volatile__ ("xvbf16ger2pn 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_xvbf16ger2pp (void) { ++ __asm__ __volatile__ ("xvbf16ger2pp 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM0_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 0, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM0_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 0, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM11_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 11, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2_XM11_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2 4, %x0, %x1, 11, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM0_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 0, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM0_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 0, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM11_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 11, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2nn_XM11_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2nn 4, %x0, %x1, 11, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM0_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 0, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM0_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 0, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM11_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 11, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2np_XM11_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2np 4, %x0, %x1, 11, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM0_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 0, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM0_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 0, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM11_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 11, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pn_XM11_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pn 4, %x0, %x1, 11, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM0_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 0, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM0_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 0, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM11_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 11, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvbf16ger2pp_XM11_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 11, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} + + static test_list_t testgroup_generic[] = { ++ { &test_pmxvbf16ger2nn_XM0_YM0_PM0, "pmxvbf16ger2nn XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2nn_XM0_YM0_PM1, "pmxvbf16ger2nn XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2nn_XM0_YM13_PM0, "pmxvbf16ger2nn XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2nn_XM0_YM13_PM1, "pmxvbf16ger2nn XM0_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2nn_XM11_YM0_PM0, "pmxvbf16ger2nn XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2nn_XM11_YM0_PM1, "pmxvbf16ger2nn XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2nn_XM11_YM13_PM0, "pmxvbf16ger2nn XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2nn_XM11_YM13_PM1, "pmxvbf16ger2nn XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM0_YM0_PM0, "pmxvbf16ger2np XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM0_YM0_PM1, "pmxvbf16ger2np XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM0_YM13_PM0, "pmxvbf16ger2np XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM0_YM13_PM1, "pmxvbf16ger2np XM0_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM11_YM0_PM0, "pmxvbf16ger2np XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM11_YM0_PM1, "pmxvbf16ger2np XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM11_YM13_PM0, "pmxvbf16ger2np XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2np_XM11_YM13_PM1, "pmxvbf16ger2np XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM0_YM0_PM0, "pmxvbf16ger2pn XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM0_YM0_PM1, "pmxvbf16ger2pn XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM0_YM13_PM0, "pmxvbf16ger2pn XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM0_YM13_PM1, "pmxvbf16ger2pn XM0_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM11_YM0_PM0, "pmxvbf16ger2pn XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM11_YM0_PM1, "pmxvbf16ger2pn XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM11_YM13_PM0, "pmxvbf16ger2pn XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pn_XM11_YM13_PM1, "pmxvbf16ger2pn XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM0_YM0_PM0, "pmxvbf16ger2pp XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM0_YM0_PM1, "pmxvbf16ger2pp XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM0_YM13_PM0, "pmxvbf16ger2pp XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM0_YM13_PM1, "pmxvbf16ger2pp XM0_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM11_YM0_PM0, "pmxvbf16ger2pp XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM11_YM0_PM1, "pmxvbf16ger2pp XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM11_YM13_PM0, "pmxvbf16ger2pp XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2pp_XM11_YM13_PM1, "pmxvbf16ger2pp XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM0_YM0_PM0, "pmxvbf16ger2 XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM0_YM0_PM1, "pmxvbf16ger2 XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM0_YM13_PM0, "pmxvbf16ger2 XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM0_YM13_PM1, "pmxvbf16ger2 XM0_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM11_YM0_PM0, "pmxvbf16ger2 XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM11_YM0_PM1, "pmxvbf16ger2 XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM11_YM13_PM0, "pmxvbf16ger2 XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ ++ { &test_pmxvbf16ger2_XM11_YM13_PM1, "pmxvbf16ger2 XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ + { &test_pmxvf16ger2nn_XM0_YM0_PM0, "pmxvf16ger2nn XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ + { &test_pmxvf16ger2nn_XM0_YM0_PM1, "pmxvf16ger2nn XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ + { &test_pmxvf16ger2nn_XM0_YM13_PM0, "pmxvf16ger2nn XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ +@@ -756,6 +976,11 @@ static test_list_t testgroup_generic[] = { + { &test_pmxvi16ger2s_XM11_YM0_PM1, "pmxvi16ger2s XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi16ger2s_XM11_YM13_PM0, "pmxvi16ger2s XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi16ger2s_XM11_YM13_PM1, "pmxvi16ger2s XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_xvbf16ger2nn, "xvbf16ger2nn", "AT,XA,XB", 0b00001111}, /* bcs */ ++ { &test_xvbf16ger2np, "xvbf16ger2np", "AT,XA,XB", 0b00001111}, /* bcs */ ++ { &test_xvbf16ger2pn, "xvbf16ger2pn", "AT,XA,XB", 0b00001111}, /* bcs */ ++ { &test_xvbf16ger2pp, "xvbf16ger2pp", "AT,XA,XB", 0b00001111}, /* bcs */ ++ { &test_xvbf16ger2, "xvbf16ger2", "AT,XA,XB", 0b00001111}, /* bcs */ + { &test_xvf16ger2nn, "xvf16ger2nn", "AT,XA,XB", 0b00001111}, /* bcs */ + { &test_xvf16ger2np, "xvf16ger2np", "AT,XA,XB", 0b00001111}, /* bcs */ + { &test_xvf16ger2pn, "xvf16ger2pn", "AT,XA,XB", 0b00001111}, /* bcs */ +diff --git a/none/tests/ppc64/test_isa_3_1_AT.stdout.exp b/none/tests/ppc64/test_isa_3_1_AT.stdout.exp +index 5ea998563..be3f17ec3 100644 +--- a/none/tests/ppc64/test_isa_3_1_AT.stdout.exp ++++ b/none/tests/ppc64/test_isa_3_1_AT.stdout.exp +@@ -1,3 +1,403 @@ ++pmxvbf16ger2nn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2nn XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2nn XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2nn XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM0_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2nn XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2nn XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2nn XM11_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2nn XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++ ++pmxvbf16ger2nn XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -3.63717e-28 -1.14437e-28 +Zero -1.14437e-28 -4.71628e-18 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2nn XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++ ++pmxvbf16ger2np XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2np XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2np XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2np XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM0_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2np XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2np XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2np XM11_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2np XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++ ++pmxvbf16ger2np XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 -1.34843e-28 1.14437e-28 +Zero 1.14437e-28 -4.71628e-18 1.14437e-28) ++pmxvbf16ger2np XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2np XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++ ++pmxvbf16ger2pn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pn XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pn XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pn XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM0_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pn XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pn XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pn XM11_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pn XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++ ++pmxvbf16ger2pn XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 1.34843e-28 -1.14437e-28 +Zero -1.14437e-28 4.71628e-18 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++pmxvbf16ger2pn XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero +Zero +Zero +Zero +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28 +Zero -1.14437e-28 -1.14437e-28 -1.14437e-28) ++ ++pmxvbf16ger2pp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pp XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pp XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM0_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pp XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2pp XM11_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2pp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++ ++pmxvbf16ger2pp XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 3.63717e-28 1.14437e-28 +Zero 1.14437e-28 4.71628e-18 1.14437e-28) ++pmxvbf16ger2pp XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++pmxvbf16ger2pp XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero 1.14437e-28 * * +Zero +Zero +Zero +Zero +Zero 1.14437e-28 * * +Zero 1.14437e-28 * *) ++ ++pmxvbf16ger2 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2 XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2 XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2 XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM0_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2 XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2 XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2 XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ ++pmxvbf16ger2 XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero NaN NaN NaN +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero 2.49280e-28 +Zero +Zero +Zero 4.71628e-18 +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => ( +Zero +Zero +Den +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Den +Zero) ++pmxvbf16ger2 XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++ + pmxvf16ger2nn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) + pmxvf16ger2nn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) + pmxvf16ger2nn XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) +@@ -1558,6 +1958,91 @@ pmxvi16ger2s XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,01 + pmxvi16ger2s XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000400000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0002400000000000] + pmxvi16ger2s XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + ++xvbf16ger2nn 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ( +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf) ++xvbf16ger2nn 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ( +Inf +Inf NaN NaN -Inf -Inf NaN NaN -Inf -Inf NaN NaN +Inf +Inf NaN NaN) ++xvbf16ger2nn 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ( +Inf NaN NaN NaN -Inf NaN NaN NaN -Inf NaN NaN NaN +Inf NaN NaN NaN) ++xvbf16ger2nn 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => ( NaN NaN +Inf -Inf NaN NaN -Inf +Inf NaN NaN -Inf +Inf NaN NaN +Inf -Inf) ++xvbf16ger2nn 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN -Inf +Inf +Inf -Inf -Inf +Inf +Inf -Inf) ++xvbf16ger2nn 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => ( -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2nn 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => ( -3.63717e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -4.71628e-18 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14438e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2nn 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => ( -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 -Inf +Inf -1.14437e-28 -1.14437e-28 -Inf +Inf) ++xvbf16ger2nn 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN -Inf +Inf +Inf -Inf NaN NaN NaN NaN) ++xvbf16ger2nn 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => ( -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14438e-28 -3.63717e-28 -4.71628e-18 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2nn 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => ( -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -4.00000e+00 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2nn 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => ( -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 -Inf +Inf -1.14437e-28 -1.14437e-28 NaN NaN) ++xvbf16ger2nn 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => ( -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf NaN NaN NaN NaN NaN NaN NaN NaN) ++xvbf16ger2nn 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => ( -Inf -Inf NaN NaN +Inf +Inf NaN NaN -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2nn 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => ( -Inf NaN NaN NaN +Inf NaN NaN NaN -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2nn 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => ( NaN NaN -Inf +Inf NaN NaN +Inf -Inf -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 NaN NaN) ++ ++xvbf16ger2np 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ( +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf) ++xvbf16ger2np 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ( +Inf +Inf NaN NaN -Inf -Inf NaN NaN -Inf -Inf NaN NaN +Inf +Inf NaN NaN) ++xvbf16ger2np 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ( +Inf NaN NaN NaN -Inf NaN NaN NaN -Inf NaN NaN NaN +Inf NaN NaN NaN) ++xvbf16ger2np 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => ( NaN NaN +Inf -Inf NaN NaN -Inf +Inf NaN NaN -Inf +Inf NaN NaN +Inf -Inf) ++xvbf16ger2np 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN -Inf +Inf +Inf -Inf -Inf +Inf +Inf -Inf) ++xvbf16ger2np 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => ( * * * * * * * * * * * * * * * *) ++xvbf16ger2np 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => ( -1.34843e-28 1.14437e-28 * * -4.71628e-18 1.14437e-28 * * 1.14437e-28 1.14437e-28 * * 1.14437e-28 1.14437e-28 * *) ++xvbf16ger2np 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => ( * * NaN NaN * * NaN NaN * * -Inf +Inf * * -Inf +Inf) ++xvbf16ger2np 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN -Inf +Inf +Inf -Inf NaN NaN NaN NaN) ++xvbf16ger2np 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => ( * * * * * * * * 1.14437e-28 1.14437e-28 -1.34843e-28 -4.71628e-18 * * * *) ++xvbf16ger2np 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => ( * * * * * * * * -4.00000e+00 1.14437e-28 * * * * * *) ++xvbf16ger2np 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => ( * * NaN NaN * * NaN NaN * * -Inf +Inf * * NaN NaN) ++xvbf16ger2np 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => ( -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf NaN NaN NaN NaN NaN NaN NaN NaN) ++xvbf16ger2np 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => ( -Inf -Inf NaN NaN +Inf +Inf NaN NaN * * * * * * * *) ++xvbf16ger2np 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => ( -Inf NaN NaN NaN +Inf NaN NaN NaN * * * * * * * *) ++xvbf16ger2np 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => ( NaN NaN -Inf +Inf NaN NaN +Inf -Inf * * NaN NaN * * NaN NaN) ++ ++xvbf16ger2pn 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ( -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf) ++xvbf16ger2pn 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ( -Inf -Inf NaN NaN +Inf +Inf NaN NaN +Inf +Inf NaN NaN -Inf -Inf NaN NaN) ++xvbf16ger2pn 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ( -Inf NaN NaN NaN +Inf NaN NaN NaN +Inf NaN NaN NaN -Inf NaN NaN NaN) ++xvbf16ger2pn 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => ( NaN NaN -Inf +Inf NaN NaN +Inf -Inf NaN NaN +Inf -Inf NaN NaN -Inf +Inf) ++xvbf16ger2pn 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN +Inf -Inf -Inf +Inf +Inf -Inf -Inf +Inf) ++xvbf16ger2pn 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => ( -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2pn 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => ( 1.34843e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 4.71628e-18 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2pn 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => ( -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 +Inf -Inf -1.14437e-28 -1.14437e-28 +Inf -Inf) ++xvbf16ger2pn 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN +Inf -Inf -Inf +Inf NaN NaN NaN NaN) ++xvbf16ger2pn 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => ( -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 1.34843e-28 4.71628e-18 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2pn 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => ( -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 4.00000e+00 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2pn 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => ( -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 +Inf -Inf -1.14437e-28 -1.14437e-28 NaN NaN) ++xvbf16ger2pn 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => ( +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf NaN NaN NaN NaN NaN NaN NaN NaN) ++xvbf16ger2pn 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => ( +Inf +Inf NaN NaN -Inf -Inf NaN NaN -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2pn 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => ( +Inf NaN NaN NaN -Inf NaN NaN NaN -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28 -1.14437e-28) ++xvbf16ger2pn 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => ( NaN NaN +Inf -Inf NaN NaN -Inf +Inf -1.14437e-28 -1.14437e-28 NaN NaN -1.14437e-28 -1.14437e-28 NaN NaN) ++ ++xvbf16ger2pp 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ( -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf) ++xvbf16ger2pp 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ( -Inf -Inf NaN NaN +Inf +Inf NaN NaN +Inf +Inf NaN NaN -Inf -Inf NaN NaN) ++xvbf16ger2pp 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ( -Inf NaN NaN NaN +Inf NaN NaN NaN +Inf NaN NaN NaN -Inf NaN NaN NaN) ++xvbf16ger2pp 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => ( NaN NaN -Inf +Inf NaN NaN +Inf -Inf NaN NaN +Inf -Inf NaN NaN -Inf +Inf) ++xvbf16ger2pp 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN +Inf -Inf -Inf +Inf +Inf -Inf -Inf +Inf) ++xvbf16ger2pp 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => ( * * * * * * * * * * * * * * * *) ++xvbf16ger2pp 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => ( 3.63717e-28 1.14437e-28 * * 4.71628e-18 1.14437e-28 * * 1.14437e-28 1.14437e-28 * * 1.14438e-28 1.14437e-28 * *) ++xvbf16ger2pp 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => ( * * NaN NaN * * NaN NaN * * +Inf -Inf * * +Inf -Inf) ++xvbf16ger2pp 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN +Inf -Inf -Inf +Inf NaN NaN NaN NaN) ++xvbf16ger2pp 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => ( * * * * * * * * 1.14437e-28 1.14438e-28 3.63717e-28 4.71628e-18 * * * *) ++xvbf16ger2pp 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => ( * * * * * * * * 4.00000e+00 1.14437e-28 * * * * * *) ++xvbf16ger2pp 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => ( * * NaN NaN * * NaN NaN * * +Inf -Inf * * NaN NaN) ++xvbf16ger2pp 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => ( +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf NaN NaN NaN NaN NaN NaN NaN NaN) ++xvbf16ger2pp 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => ( +Inf +Inf NaN NaN -Inf -Inf NaN NaN * * * * * * * *) ++xvbf16ger2pp 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => ( +Inf NaN NaN NaN -Inf NaN NaN NaN * * * * * * * *) ++xvbf16ger2pp 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => ( NaN NaN +Inf -Inf NaN NaN -Inf +Inf * * NaN NaN * * NaN NaN) ++ ++xvbf16ger2 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ( -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf) ++xvbf16ger2 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ( -Inf -Inf NaN NaN +Inf +Inf NaN NaN +Inf +Inf NaN NaN -Inf -Inf NaN NaN) ++xvbf16ger2 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ( -Inf NaN NaN NaN +Inf NaN NaN NaN +Inf NaN NaN NaN -Inf NaN NaN NaN) ++xvbf16ger2 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => ( NaN NaN -Inf +Inf NaN NaN +Inf -Inf NaN NaN +Inf -Inf NaN NaN -Inf +Inf) ++xvbf16ger2 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN +Inf -Inf -Inf +Inf +Inf -Inf -Inf +Inf) ++xvbf16ger2 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero 5.56082e-36 +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++xvbf16ger2 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => ( 2.49280e-28 +Zero +Zero +Zero 4.71628e-18 +Zero +Zero +Zero 2.08768e-35 +Zero +Zero +Zero 3.82177e-34 +Zero +Zero +Zero) ++xvbf16ger2 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => ( +Zero +Zero NaN NaN +Zero +Zero NaN NaN +Zero +Zero +Inf -Inf +Zero +Zero +Inf -Inf) ++xvbf16ger2 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN +Inf -Inf -Inf +Inf NaN NaN NaN NaN) ++xvbf16ger2 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => ( +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero 2.08768e-35 3.82177e-34 2.49280e-28 4.71628e-18 +Zero +Zero +Zero +Zero) ++xvbf16ger2 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => ( +Zero +Zero +Zero +Zero +Den +Zero +Zero +Zero 4.00000e+00 +Zero +Zero +Den +Zero +Zero +Zero +Zero) ++xvbf16ger2 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => ( +Zero +Zero NaN NaN +Zero +Zero NaN NaN +Zero +Zero +Inf -Inf +Zero +Zero NaN NaN) ++xvbf16ger2 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => ( +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf NaN NaN NaN NaN NaN NaN NaN NaN) ++xvbf16ger2 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => ( +Inf +Inf NaN NaN -Inf -Inf NaN NaN +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++xvbf16ger2 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => ( +Inf NaN NaN NaN -Inf NaN NaN NaN +Zero +Zero +Zero +Zero +Zero +Zero +Zero +Zero) ++xvbf16ger2 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => ( NaN NaN +Inf -Inf NaN NaN -Inf +Inf +Zero +Zero NaN NaN +Zero +Zero NaN NaN) ++ + xvf16ger2nn 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ( NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN) + xvf16ger2nn 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ( NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN) + xvf16ger2nn 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ( NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN) +@@ -1921,4 +2406,4 @@ xxmtacc => [ 7f800000ff800000 ff8000007f800000 ff7ffffe7f7ffffe 0080000e8080000e + + xxsetaccz => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + +-All done. Tested 152 different instruction groups ++All done. Tested 197 different instruction groups +diff --git a/none/tests/ppc64/test_isa_3_1_XT.c b/none/tests/ppc64/test_isa_3_1_XT.c +index a54e8763a..905c17951 100644 +--- a/none/tests/ppc64/test_isa_3_1_XT.c ++++ b/none/tests/ppc64/test_isa_3_1_XT.c +@@ -491,6 +491,16 @@ static void test_pstxv_4 (void) { + static void test_pstxv_0 (void) { + __asm__ __volatile__ ("pstxv %x0, 0(%1), 0" :: "wa" (vec_xs), "r" (ra) ); + } ++static void test_xvcvspbf16 (void) { ++SET_FPSCR_ZERO; ++ __asm__ __volatile__ ("xvcvspbf16 %x0, %x1" ++ : "=wa" (vec_xt) : "wa" (vec_xb) ); ++GET_FPSCR(current_fpscr); ++} ++static void test_xvcvbf16spn (void) { ++ __asm__ __volatile__ ("xvcvbf16spn %x0, %x1" ++ : "=wa" (vec_xt) : "wa" (vec_xb) ); ++} + static void test_xxgenpcvbm_imm0 (void) { + __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); + } +@@ -634,6 +644,8 @@ static test_list_t testgroup_generic[] = { + { &test_stxvrdx, "stxvrdx", "XS,RA,RB"}, /* bcs */ + { &test_stxvrhx, "stxvrhx", "XS,RA,RB"}, /* bcs */ + { &test_stxvrwx, "stxvrwx", "XS,RA,RB"}, /* bcs */ ++ { &test_xvcvbf16spn, "xvcvbf16spn", "XT,XB"}, /* bcs */ ++ { &test_xvcvspbf16, "xvcvspbf16", "XT,XB", 0b0101010100000000}, /* bcs */ + { &test_xxblendvb, "xxblendvb", "XT,XA,XB,XC"}, /* bcs */ + { &test_xxblendvd, "xxblendvd", "XT,XA,XB,XC"}, /* bcs */ + { &test_xxblendvh, "xxblendvh", "XT,XA,XB,XC"}, /* bcs */ +diff --git a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp +index 8b5f1d1a3..b9d6cb7a8 100644 +--- a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp ++++ b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp +@@ -244,6 +244,34 @@ stxvrwx 18 (&buffer) 0000111e8000222e,0180055e0180077e => [ - - - 7f0000008 + stxvrwx 20 (&buffer) 7ff0000000000000,0000111e8000222e => [ - - - - 5a05a05a00000000 - - - ] + stxvrwx 28 (&buffer) fff0000000000000,7ff0000000000000 => [ - - - - - 0102030400000000 - - ] + ++xvcvbf16spn 7f800000ff800000,ff8000007f800000 => 0 0 ++xvcvbf16spn ff8000007f800000,ff7ffffe7f7ffffe => 0 fffe0000fffe0000 ++xvcvbf16spn ff7ffffe7f7ffffe,0080000e8080000e => fffe0000fffe0000 e0000000e0000 ++xvcvbf16spn 0080000e8080000e,0180055e0180077e => e0000000e0000 55e0000077e0000 ++xvcvbf16spn 0180055e0180077e,0000111e8000222e => 55e0000077e0000 111e0000222e0000 ++xvcvbf16spn 0000111e8000222e,7ff0000000000000 => 111e0000222e0000 0 ++xvcvbf16spn 7ff0000000000000,fff0000000000000 => 0 0 ++xvcvbf16spn fff0000000000000,2208400000000000 => 0 4000000000000000 ++xvcvbf16spn 2208400000000000,0000000000000009 => 4000000000000000 90000 ++xvcvbf16spn 0000000000000009,ffff000180000001 => 90000 1000000010000 ++xvcvbf16spn ffff000180000001,0000000000000000 => 1000000010000 0 ++xvcvbf16spn 0000000000000000,8000000000000000 => 0 0 ++xvcvbf16spn 8000000000000000,7f800000ff800000 => 0 0 ++ ++xvcvspbf16 7f800000ff800000,ff8000007f800000 => +Inf -Inf -Inf +Inf ++xvcvspbf16 ff8000007f800000,ff7ffffe7f7ffffe => -Inf +Inf -Inf +Inf ++xvcvspbf16 ff7ffffe7f7ffffe,0080000e8080000e => -Inf +Inf 0x0080 0x8080 ++xvcvspbf16 0080000e8080000e,0180055e0180077e => 0x0080 0x8080 0x0180 0x0180 ++xvcvspbf16 0180055e0180077e,0000111e8000222e => 0x0180 0x0180 +Zero -Zero ++xvcvspbf16 0000111e8000222e,7ff0000000000000 => +Zero -Zero NaN +Zero ++xvcvspbf16 7ff0000000000000,fff0000000000000 => NaN +Zero NaN +Zero ++xvcvspbf16 fff0000000000000,2208400000000000 => NaN +Zero 0x2208 +Zero ++xvcvspbf16 2208400000000000,0000000000000009 => 0x2208 +Zero +Zero +Zero ++xvcvspbf16 0000000000000009,ffff000180000001 => +Zero +Zero NaN -Zero ++xvcvspbf16 ffff000180000001,0000000000000000 => NaN -Zero +Zero +Zero ++xvcvspbf16 0000000000000000,8000000000000000 => +Zero +Zero -Zero +Zero ++xvcvspbf16 8000000000000000,7f800000ff800000 => -Zero +Zero +Inf -Inf ++ + xxblendvb 7f800000ff800000,ff8000007f800000 0000000000000000,00000000ffffffff 7f800000ff800000,ff8000007f800000 => 7f800000ff800000 ff8000007f800000 + xxblendvb 7f800000ff800000,ff8000007f800000 ffffffff55555555,5555aaaaaaaa5555 7f800000ff800000,ff8000007f800000 => 7f800000ff800000 ff8000007f800000 + xxblendvb 7f800000ff800000,ff8000007f800000 aaaa00000000aaaa,0000000000000000 7f800000ff800000,ff8000007f800000 => 7f800000ff800000 ff8000007f800000 +@@ -7318,4 +7346,4 @@ xxspltiw imm3 => 300000003 300000003 + + xxspltiw imm8 => 800000008 800000008 + +-All done. Tested 158 different instruction groups ++All done. Tested 160 different instruction groups + +commit c589b652939655090c005a982a71f50c489fb5ce +Author: root +Date: Fri Feb 12 16:00:53 2021 -0500 + + Reduced precision Missing Integer based outer tests + +diff --git a/NEWS b/NEWS +index 2e42e74b2..52a51fd9e 100644 +--- a/NEWS ++++ b/NEWS +@@ -176,6 +176,7 @@ where XXXXXX is the bug number as listed below. + 433500 DRD regtest faulures when libstdc++ and libgcc debuginfo are installed + 433629 valgrind/README has type "abd" instead of "and" + 433641 Rust std::sys::unix::fs::try_statx Syscall param fstatat(file_name) ++433801 PPC ISA 3.1 support is missing, part 10 (ISA 3.1 support complete) + 433898 arm64: Handle sp, lr, fp as DwReg in CfiExpr + 434193 GCC 9+ inlined strcmp causes "Conditional jump or move [..] value" report + n-i-bz helgrind: If hg_cli__realloc fails, return NULL. +diff --git a/none/tests/ppc64/test_isa_3_1_AT.c b/none/tests/ppc64/test_isa_3_1_AT.c +index fee76f8f4..e9db9cc9a 100644 +--- a/none/tests/ppc64/test_isa_3_1_AT.c ++++ b/none/tests/ppc64/test_isa_3_1_AT.c +@@ -806,6 +806,114 @@ static void test_pmxvbf16ger2pp_XM11_YM13_PM1 (void) { + __asm__ __volatile__ ("pmxvbf16ger2pp 4, %x0, %x1, 11, 13, 1" + :: "wa" (vec_xa), "wa" (vec_xb) ); + } ++static void test_xvi8ger4spp (void) { ++ __asm__ __volatile__ ("xvi8ger4spp 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM0_YM0_PM5 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 0, 0, 5" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM0_YM13_PM5 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 0, 13, 5" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM11_YM0_PM5 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 11, 0, 5" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi8ger4spp_XM11_YM13_PM5 (void) { ++ __asm__ __volatile__ ("pmxvi8ger4spp 4, %x0, %x1, 11, 13, 5" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_xvi16ger2 (void) { ++ __asm__ __volatile__ ("xvi16ger2 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_xvi16ger2pp (void) { ++ __asm__ __volatile__ ("xvi16ger2pp 4, %x0, %x1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM0_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 0, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM0_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 0, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM11_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 11, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2_XM11_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2 4, %x0, %x1, 11, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM0_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 0, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM0_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 0, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM0_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 0, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM0_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 0, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM11_YM0_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 11, 0, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM11_YM0_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 11, 0, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM11_YM13_PM0 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 11, 13, 0" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} ++static void test_pmxvi16ger2pp_XM11_YM13_PM1 (void) { ++ __asm__ __volatile__ ("pmxvi16ger2pp 4, %x0, %x1, 11, 13, 1" ++ :: "wa" (vec_xa), "wa" (vec_xb) ); ++} + + static test_list_t testgroup_generic[] = { + { &test_pmxvbf16ger2nn_XM0_YM0_PM0, "pmxvbf16ger2nn XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK", 0b00001111}, /* bcwp */ +@@ -952,6 +1060,14 @@ static test_list_t testgroup_generic[] = { + { &test_pmxvi8ger4pp_XM11_YM0_PM5, "pmxvi8ger4pp XM11_YM0_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi8ger4pp_XM11_YM13_PM0, "pmxvi8ger4pp XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi8ger4pp_XM11_YM13_PM5, "pmxvi8ger4pp XM11_YM13_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM0_YM0_PM0, "pmxvi8ger4spp XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM0_YM0_PM5, "pmxvi8ger4spp XM0_YM0_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM0_YM13_PM0, "pmxvi8ger4spp XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM0_YM13_PM5, "pmxvi8ger4spp XM0_YM13_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM11_YM0_PM0, "pmxvi8ger4spp XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM11_YM0_PM5, "pmxvi8ger4spp XM11_YM0_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM11_YM13_PM0, "pmxvi8ger4spp XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi8ger4spp_XM11_YM13_PM5, "pmxvi8ger4spp XM11_YM13_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi8ger4_XM0_YM0_PM0, "pmxvi8ger4 XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi8ger4_XM0_YM0_PM5, "pmxvi8ger4 XM0_YM0_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi8ger4_XM0_YM13_PM0, "pmxvi8ger4 XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ +@@ -960,6 +1076,14 @@ static test_list_t testgroup_generic[] = { + { &test_pmxvi8ger4_XM11_YM0_PM5, "pmxvi8ger4 XM11_YM0_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi8ger4_XM11_YM13_PM0, "pmxvi8ger4 XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi8ger4_XM11_YM13_PM5, "pmxvi8ger4 XM11_YM13_PM5", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM0_YM0_PM0, "pmxvi16ger2pp XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM0_YM0_PM1, "pmxvi16ger2pp XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM0_YM13_PM0, "pmxvi16ger2pp XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM0_YM13_PM1, "pmxvi16ger2pp XM0_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM11_YM0_PM0, "pmxvi16ger2pp XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM11_YM0_PM1, "pmxvi16ger2pp XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM11_YM13_PM0, "pmxvi16ger2pp XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2pp_XM11_YM13_PM1, "pmxvi16ger2pp XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi16ger2spp_XM0_YM0_PM0, "pmxvi16ger2spp XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi16ger2spp_XM0_YM0_PM1, "pmxvi16ger2spp XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi16ger2spp_XM0_YM13_PM0, "pmxvi16ger2spp XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ +@@ -976,6 +1100,14 @@ static test_list_t testgroup_generic[] = { + { &test_pmxvi16ger2s_XM11_YM0_PM1, "pmxvi16ger2s XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi16ger2s_XM11_YM13_PM0, "pmxvi16ger2s XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_pmxvi16ger2s_XM11_YM13_PM1, "pmxvi16ger2s XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM0_YM0_PM0, "pmxvi16ger2 XM0_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM0_YM0_PM1, "pmxvi16ger2 XM0_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM0_YM13_PM0, "pmxvi16ger2 XM0_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM0_YM13_PM1, "pmxvi16ger2 XM0_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM11_YM0_PM0, "pmxvi16ger2 XM11_YM0_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM11_YM0_PM1, "pmxvi16ger2 XM11_YM0_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM11_YM13_PM0, "pmxvi16ger2 XM11_YM13_PM0", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ ++ { &test_pmxvi16ger2_XM11_YM13_PM1, "pmxvi16ger2 XM11_YM13_PM1", "AT,XA,XB,XMSK,YMSK,PMSK"}, /* bcwp */ + { &test_xvbf16ger2nn, "xvbf16ger2nn", "AT,XA,XB", 0b00001111}, /* bcs */ + { &test_xvbf16ger2np, "xvbf16ger2np", "AT,XA,XB", 0b00001111}, /* bcs */ + { &test_xvbf16ger2pn, "xvbf16ger2pn", "AT,XA,XB", 0b00001111}, /* bcs */ +@@ -999,9 +1131,12 @@ static test_list_t testgroup_generic[] = { + { &test_xvi4ger8pp, "xvi4ger8pp", "AT,XA,XB"}, /* bcs */ + { &test_xvi4ger8, "xvi4ger8", "AT,XA,XB"}, /* bcs */ + { &test_xvi8ger4pp, "xvi8ger4pp", "AT,XA,XB"}, /* bcs */ ++ { &test_xvi8ger4spp, "xvi8ger4spp", "AT,XA,XB"}, /* bcs */ + { &test_xvi8ger4, "xvi8ger4", "AT,XA,XB"}, /* bcs */ ++ { &test_xvi16ger2pp, "xvi16ger2pp", "AT,XA,XB"}, /* bcs */ + { &test_xvi16ger2spp, "xvi16ger2spp", "AT,XA,XB"}, /* bcs */ + { &test_xvi16ger2s, "xvi16ger2s", "AT,XA,XB"}, /* bcs */ ++ { &test_xvi16ger2, "xvi16ger2", "AT,XA,XB"}, /* bcs */ + { &test_xxmfacc, "xxmfacc", "AS"}, /* bcs */ + { &test_xxmtacc, "xxmtacc", "AT"}, /* bcs */ + { &test_xxsetaccz, "xxsetaccz", "AT"}, /* bcs */ +diff --git a/none/tests/ppc64/test_isa_3_1_AT.stdout.exp b/none/tests/ppc64/test_isa_3_1_AT.stdout.exp +index be3f17ec3..8d1be35b1 100644 +--- a/none/tests/ppc64/test_isa_3_1_AT.stdout.exp ++++ b/none/tests/ppc64/test_isa_3_1_AT.stdout.exp +@@ -1718,6 +1718,86 @@ pmxvi8ger4pp XM11_YM13_PM5 0000000000000009,ffff000180000001 0080000e8080000e,01 + pmxvi8ger4pp XM11_YM13_PM5 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000011111111 1111110911111111 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] + pmxvi8ger4pp XM11_YM13_PM5 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] + ++pmxvi8ger4spp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi8ger4spp XM0_YM0_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM0_PM5 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi8ger4spp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi8ger4spp XM0_YM13_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM0_YM13_PM5 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi8ger4spp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi8ger4spp XM11_YM0_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi8ger4spp XM11_YM0_PM5 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi8ger4spp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++ ++pmxvi8ger4spp XM11_YM13_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000011115075 11114fd511114f95 0000000000000000 0000000000000000 000000001110d111 1110d1111110d111 000000001110d111 1110d1111110d111] ++pmxvi8ger4spp XM11_YM13_PM5 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000011111111 1111150911111111 0000000000000000 0000000000000000 0000000011111111 11110d1111111111 0000000011111111 11110d1111111111] ++pmxvi8ger4spp XM11_YM13_PM5 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM5 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000011110911 1111091111110911 0000000000000000 0000000000000000 00000000111112b5 11111c1511111fd5 0000000011111395 111121f5111127b5] ++pmxvi8ger4spp XM11_YM13_PM5 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000011111111 1111109111111111 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM5 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM5 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 000000001111109f 111110ef1111110f 0000000000000000 0000000000000000 0000000011111111 * 000000001111118f 1111145f1111157f] ++pmxvi8ger4spp XM11_YM13_PM5 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000011111111 1111110911111111 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi8ger4spp XM11_YM13_PM5 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++ + pmxvi8ger4 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + pmxvi8ger4 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + pmxvi8ger4 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] +@@ -1798,6 +1878,86 @@ pmxvi8ger4 XM11_YM13_PM5 0000000000000009,ffff000180000001 0080000e8080000e,0180 + pmxvi8ger4 XM11_YM13_PM5 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 fffffff800000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + pmxvi8ger4 XM11_YM13_PM5 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + ++pmxvi16ger2pp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2pp XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2pp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2pp XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM0_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2pp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2pp XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2pp XM11_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2pp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++ ++pmxvi16ger2pp XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 00000000111110f5 1111065511110215 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000011111111 1110911111111111 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000011111111 * 0000000000000000 0000000000000000 00000000111200b5 116cf01511914fd5 000000001112ef95 11c883f5121125b5] ++pmxvi16ger2pp XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 1558911111111111 0000000011111111 199c911111111111] ++pmxvi16ger2pp XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++pmxvi16ger2pp XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 000000001111111f 1111166f1111188f 0000000000000000 0000000000000000 0000000011111111 * 000000001111118f 1111415f1111547f] ++pmxvi16ger2pp XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000011111111 1111511111111111 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 1113511111111111] ++pmxvi16ger2pp XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000011111111 * 0000000000000000 0000000000000000 0000000011111111 * 0000000011111111 *] ++ + pmxvi16ger2spp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + pmxvi16ger2spp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + pmxvi16ger2spp XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] +@@ -1958,6 +2118,86 @@ pmxvi16ger2s XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,01 + pmxvi16ger2s XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000400000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0002400000000000] + pmxvi16ger2s XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + ++pmxvi16ger2 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2 XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2 XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2 XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM0_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2 XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2 XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM0_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2 XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM0 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ ++pmxvi16ger2 XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [ 00000000ffffffe4 fffff544fffff104 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [ 0000000000000000 ffff800000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM1 ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 000000000000efa4 005bdf0400803ec4 000000000001de84 00b772e4010014a4] ++pmxvi16ger2 XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0447800000000000 0000000000000000 088b800000000000] ++pmxvi16ger2 XM11_YM13_PM1 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++pmxvi16ger2 XM11_YM13_PM1 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [ 000000000000000e 0000055e0000077e 0000000000000000 0000000000000000 0000000000000000 0000000000000000 000000000000007e 0000304e0000436e] ++pmxvi16ger2 XM11_YM13_PM1 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [ 0000000000000000 0000400000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0002400000000000] ++pmxvi16ger2 XM11_YM13_PM1 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] ++ + xvbf16ger2nn 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ( +Inf -Inf -Inf +Inf -Inf +Inf +Inf -Inf -Inf +Inf +Inf -Inf +Inf -Inf -Inf +Inf) + xvbf16ger2nn 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ( +Inf +Inf NaN NaN -Inf -Inf NaN NaN -Inf -Inf NaN NaN +Inf +Inf NaN NaN) + xvbf16ger2nn 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ( +Inf NaN NaN NaN -Inf NaN NaN NaN -Inf NaN NaN NaN +Inf NaN NaN NaN) +@@ -2349,6 +2589,23 @@ xvi8ger4pp 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e = + xvi8ger4pp 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [ 11111def11111111 * 11110cef11111111 * 1111001111111111 * * *] + xvi8ger4pp 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [ 1111509111111111 1111101211114f92 1111109111111111 1110d0921110d012 1110d11111111111 1110d19111109191 * *] + ++xvi8ger4spp 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [ 1110d0921110d012 1110d0121110d092 1111101211114f92 11114f9211111012 1111101211114f92 11114f9211111012 1110d0921110d012 1110d0121110d092] ++xvi8ger4spp 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [ 1110d1101110d110 1111111111111091 1110d1901110d190 1111111111115091 1110d1901110d190 1111111111115091 1110d1101110d110 1111111111111091] ++xvi8ger4spp 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [ 11110cef11111111 * 11111def11111111 * 11111def11111111 * 11110cef11111111 *] ++xvi8ger4spp 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => [ 1111109111111111 1110d0921110d012 1111509111111111 1111101211114f92 1111509111111111 1111101211114f92 1111109111111111 1110d0921110d012] ++xvi8ger4spp 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => [ * * 1110d19111109191 111091911110d191 1110d1901110d210 1110d2101110d190 1110d1901110d210 1110d2101110d190] ++xvi8ger4spp 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => [ 11111c6a1111204c 111115b6111118b7 1111221f11112823 111118b71110ddd9 1110f3af1110ff79 11111c6a1111231f 1110ff7911110f47 1111204c11112923] ++xvi8ger4spp 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => [ 1111155111111111 111111111111121f 1111089111111111 11111111111112af 11110e7311111111 111111111111145f 11110ef311111111 111111111111157f] ++xvi8ger4spp 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => [ * * 1110d11111111111 1110d19111109191 1111119111111111 1110d1901110d210 1111119111111111 1110d1901110d210] ++xvi8ger4spp 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => [ * * * * 111125ef111136ef 111136ef111125ef * *] ++xvi8ger4spp 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => [ * * 1111145f1111157f 1111121f111112af 11111673111116f3 1111155111112a91 * *] ++xvi8ger4spp 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => [ * * * 1111111111111162 111125d511111111 * * *] ++xvi8ger4spp 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => [ * * * * 1111221111111111 111125ef111136ef * *] ++xvi8ger4spp 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => [ 1111101211114f92 11114f9211111012 1110d0921110d012 1110d0121110d092 1110d19111109191 111091911110d191 * *] ++xvi8ger4spp 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => [ 1110d1901110d190 1111111111115091 1110d1101110d110 1111111111111091 1111109111111091 111111111110d111 * *] ++xvi8ger4spp 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [ 11111def11111111 * 11110cef11111111 * 1111001111111111 * * *] ++xvi8ger4spp 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [ 1111509111111111 1111101211114f92 1111109111111111 1110d0921110d012 1110d11111111111 1110d19111109191 * *] ++ + xvi8ger4 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [ ffffbf81ffffbf01 ffffbf01ffffbf81 ffffff0100003e81 00003e81ffffff01 ffffff0100003e81 00003e81ffffff01 ffffbf81ffffbf01 ffffbf01ffffbf81] + xvi8ger4 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [ ffffbfffffffbfff 00000000ffffff80 ffffc07fffffc07f 0000000000003f80 ffffc07fffffc07f 0000000000003f80 ffffbfffffffbfff 00000000ffffff80] + xvi8ger4 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [ fffffbde00000000 0000000000000000 00000cde00000000 0000000000000000 00000cde00000000 0000000000000000 fffffbde00000000 0000000000000000] +@@ -2366,6 +2623,23 @@ xvi8ger4 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => + xvi8ger4 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [ 00000cde00000000 0000000000000000 fffffbde00000000 0000000000000000 ffffef0000000000 0000000000000000 0000000000000000 0000000000000000] + xvi8ger4 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [ 00003f8000000000 ffffff0100003e81 ffffff8000000000 ffffbf81ffffbf01 ffffc00000000000 ffffc080ffff8080 0000000000000000 0000000000000000] + ++xvi16ger2pp 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [ 10d1511111115111 1111511110d15111 5091511110d15111 10d1511150915111 5091511110d15111 10d1511150915111 10d1511111115111 1111511110d15111] ++xvi16ger2pp 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [ 1110511111105111 1111111111511111 11d0511111d05111 11111111d1511111 11d0511111d05111 11111111d1511111 1110511111105111 1111111111511111] ++xvi16ger2pp 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [ 11000d1111111111 * 22040d1111111111 * 22040d1111111111 * 11000d1111111111 *] ++xvi16ger2pp 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => [ 1151111111111111 10d1511111115111 d151111111111111 5091511110d15111 d151111111111111 5091511110d15111 1151111111111111 10d1511111115111] ++xvi16ger2pp 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => [ * * d151111111511111 11511111d1511111 11d0511111105111 1110511111d05111 11d0511111105111 1110511111d05111] ++xvi16ger2pp 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => [ 116cf01511914fd5 12361095135a2075 110883f5115125b5 135a207555a15155 11301f95113b8755 116cf015110883f5 113b8755114b7315 11914fd5115125b5] ++xvi16ger2pp 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => [ 1558911111111111 111111111111ab1f 0898911111111111 11111111111244af 129b9d1111111111 111111111111415f 13239d1111111111 111111111111547f] ++xvi16ger2pp 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => [ * * 5111111111111111 d151111111511111 1051111111111111 11d0511111105111 1051111111111111 11d0511111105111] ++xvi16ger2pp 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => [ * * * * 22040d1111000d11 11000d1122040d11 * *] ++xvi16ger2pp 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => [ * * 1111415f1111547f 1111ab1f111244af 129b9d1113239d11 1558911108989111 * *] ++xvi16ger2pp 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => [ * * 1113511111111111 1111111111111162 2597315111111111 1111111111135111 * *] ++xvi16ger2pp 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => [ * * * * 000d111111111111 22040d1111000d11 * *] ++xvi16ger2pp 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => [ 5091511110d15111 10d1511150915111 10d1511111115111 1111511110d15111 d151111111511111 11511111d1511111 * *] ++xvi16ger2pp 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => [ 11d0511111d05111 11111111d1511111 1110511111105111 1111111111511111 1051111110511111 1111111151111111 * *] ++xvi16ger2pp 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [ 22040d1111111111 * 11000d1111111111 * 000d111111111111 * * *] ++xvi16ger2pp 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [ d151111111111111 5091511110d15111 1151111111111111 10d1511111115111 5111111111111111 d151111111511111 * *] ++ + xvi16ger2spp 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [ 10d1511111115111 1111511110d15111 5091511110d15111 10d1511150915111 5091511110d15111 10d1511150915111 10d1511111115111 1111511110d15111] + xvi16ger2spp 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [ 1110511111105111 1111111111511111 11d0511111d05111 11111111d1511111 11d0511111d05111 11111111d1511111 1110511111105111 1111111111511111] + xvi16ger2spp 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [ 11000d1111111111 * 22040d1111111111 * 22040d1111111111 * 11000d1111111111 *] +@@ -2400,10 +2674,27 @@ xvi16ger2s 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e = + xvi16ger2s 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [ 10f2fc0000000000 0000000000000000 ffeefc0000000000 0000000000000000 eefc000000000000 0000000000000000 0000000000000000 0000000000000000] + xvi16ger2s 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [ c040000000000000 3f804000ffc04000 0040000000000000 ffc0400000004000 4000000000000000 c040000000400000 0000000000000000 0000000000000000] + ++xvi16ger2 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [ ffc0400000004000 00004000ffc04000 3f804000ffc04000 ffc040003f804000 3f804000ffc04000 ffc040003f804000 ffc0400000004000 00004000ffc04000] ++xvi16ger2 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [ ffff4000ffff4000 0000000000400000 00bf400000bf4000 00000000c0400000 00bf400000bf4000 00000000c0400000 ffff4000ffff4000 0000000000400000] ++xvi16ger2 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [ ffeefc0000000000 0000000000000000 10f2fc0000000000 0000000000000000 10f2fc0000000000 0000000000000000 ffeefc0000000000 0000000000000000] ++xvi16ger2 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => [ 0040000000000000 ffc0400000004000 c040000000000000 3f804000ffc04000 c040000000000000 3f804000ffc04000 0040000000000000 ffc0400000004000] ++xvi16ger2 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => [ 0000000000000000 0000000000000000 c040000000400000 00400000c0400000 00bf4000ffff4000 ffff400000bf4000 00bf4000ffff4000 ffff400000bf4000] ++xvi16ger2 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => [ 005bdf0400803ec4 0124ff8402490f64 fff772e4004014a4 02490f6444904044 001f0e84002a7644 005bdf04fff772e4 002a7644003a6204 00803ec4004014a4] ++xvi16ger2 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => [ 0447800000000000 0000000000009a0e f787800000000000 000000000001339e 018a8c0000000000 000000000000304e 02128c0000000000 000000000000436e] ++xvi16ger2 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => [ 0000000000000000 0000000000000000 4000000000000000 c040000000400000 ff40000000000000 00bf4000ffff4000 ff40000000000000 00bf4000ffff4000] ++xvi16ger2 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 10f2fc00ffeefc00 ffeefc0010f2fc00 0000000000000000 0000000000000000] ++xvi16ger2 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => [ 0000000000000000 0000000000000000 0000304e0000436e 00009a0e0001339e 018a8c0002128c00 04478000f7878000 0000000000000000 0000000000000000] ++xvi16ger2 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => [ 0000000000000000 0000000000000000 0002400000000000 0000000000000051 1486204000000000 0000000000024000 0000000000000000 0000000000000000] ++xvi16ger2 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 eefc000000000000 10f2fc00ffeefc00 0000000000000000 0000000000000000] ++xvi16ger2 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => [ 3f804000ffc04000 ffc040003f804000 ffc0400000004000 00004000ffc04000 c040000000400000 00400000c0400000 0000000000000000 0000000000000000] ++xvi16ger2 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => [ 00bf400000bf4000 00000000c0400000 ffff4000ffff4000 0000000000400000 ff400000ff400000 0000000040000000 0000000000000000 0000000000000000] ++xvi16ger2 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [ 10f2fc0000000000 0000000000000000 ffeefc0000000000 0000000000000000 eefc000000000000 0000000000000000 0000000000000000 0000000000000000] ++xvi16ger2 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [ c040000000000000 3f804000ffc04000 0040000000000000 ffc0400000004000 4000000000000000 c040000000400000 0000000000000000 0000000000000000] ++ + xxmfacc [ 7f800000ff800000 ff8000007f800000 ff7ffffe7f7ffffe 0080000e8080000e 0180055e0180077e 0000111e8000222e 7ff0000000000000 fff0000000000000] => [ 7f800000ff800000 ff8000007f800000 ff7ffffe7f7ffffe 0080000e8080000e 0180055e0180077e 0000111e8000222e 7ff0000000000000 fff0000000000000] + + xxmtacc => [ 7f800000ff800000 ff8000007f800000 ff7ffffe7f7ffffe 0080000e8080000e 0180055e0180077e 0000111e8000222e 7ff0000000000000 fff0000000000000] + + xxsetaccz => [ 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000] + +-All done. Tested 197 different instruction groups ++All done. Tested 224 different instruction groups diff --git a/SOURCES/valgrind-3.17.0-ppc64-isa-3.1.patch b/SOURCES/valgrind-3.17.0-ppc64-isa-3.1.patch new file mode 100644 index 0000000..fb8fa50 --- /dev/null +++ b/SOURCES/valgrind-3.17.0-ppc64-isa-3.1.patch @@ -0,0 +1,1720 @@ +commit 3cc0232c46a5905b4a6c2fbd302b58bf5f90b3d5 +Author: Carl Love +Date: Mon Jan 11 16:00:57 2021 -0600 + + PPC64: ISA 3.1 VSX PCV Generate Operations + + xgenpcvbm VSX Vector Generate PCV from Byte Mask + xxgenpcvdmVSX Vector Generate PCV from Doubleword Mask + xxgenpcvhmVSX Vector Generate PCV from Halfword Mask + xxgenpcvwmVSX Vector Generate PCV from Word Mask + +diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h +index deda4dfce..54ce923a9 100644 +--- a/VEX/priv/guest_ppc_defs.h ++++ b/VEX/priv/guest_ppc_defs.h +@@ -169,6 +169,23 @@ void write_ACC_entry (VexGuestPPC64State* gst, UInt offset, UInt acc, + void get_ACC_entry (VexGuestPPC64State* gst, UInt offset, UInt acc, + UInt reg, UInt *result); + ++extern void vector_gen_pvc_byte_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ++ ULong src_lo, ++ UInt rtn_val, UInt IMM ); ++extern void vector_gen_pvc_hword_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ++ ULong src_lo, ++ UInt rtn_val, UInt IMM ); ++extern void vector_gen_pvc_word_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ++ ULong src_lo, ++ UInt rtn_val, UInt IMM ); ++extern void vector_gen_pvc_dword_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ++ ULong src_lo, ++ UInt rtn_val, UInt IMM ); ++ + /* 8-bit XO value from instruction description */ + #define XVI4GER8 0b00100011 + #define XVI4GER8PP 0b00100010 +diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c +index c24191ef3..75497abb9 100644 +--- a/VEX/priv/guest_ppc_helpers.c ++++ b/VEX/priv/guest_ppc_helpers.c +@@ -701,6 +701,738 @@ ULong vector_evaluate64_helper( ULong srcA, ULong srcB, ULong srcC, + #undef MAX_IMM_BITS + } + ++/*--------------------------------------------------*/ ++/*---- VSX Vector Generate PCV from Mask helpers ---*/ ++/*--------------------------------------------------*/ ++static void write_VSX_entry (VexGuestPPC64State* gst, UInt reg_offset, ++ ULong *vsx_entry) ++{ ++ U128* pU128_dst; ++ pU128_dst = (U128*) (((UChar*) gst) + reg_offset); ++ ++ /* The U128 type is defined as an array of unsigned intetgers. */ ++ /* Writing in LE order */ ++ (*pU128_dst)[0] = (UInt)(vsx_entry[1] & 0xFFFFFFFF); ++ (*pU128_dst)[1] = (UInt)(vsx_entry[1] >> 32); ++ (*pU128_dst)[2] = (UInt)(vsx_entry[0] & 0xFFFFFFFF); ++ (*pU128_dst)[3] = (UInt)(vsx_entry[0] >> 32); ++ return; ++} ++ ++/* CALLED FROM GENERATED CODE */ ++void vector_gen_pvc_byte_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ULong src_lo, ++ UInt reg_offset, UInt imm ) { ++ /* The function computes the 128-bit result then writes it directly ++ into the guest state VSX register. */ ++ ++ UInt i, shift_by, sel_shift_by, half_sel; ++ ULong index, src, result[2]; ++ ULong j; ++ ++ result[0] = 0; ++ result[1] = 0; ++ j = 0; ++ ++ /* The algorithm in the ISA is written with IBM numbering zero on left and ++ N-1 on right. The loop index is converted to "i" to match the algorithm ++ for claritiy of matching the C code to the algorithm in the ISA. */ ++ ++ if (imm == 0b00) { // big endian expansion ++ for( index = 0; index < 16; index++) { ++ i = 15 - index; ++ ++ shift_by = i*8; ++ ++ if ( i >= 8) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 7; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ result[half_sel] |= j << shift_by; ++ j++; ++ } else { ++ result[half_sel] |= (index + (unsigned long long)0x10) << shift_by; ++ } ++ } ++ ++ ++ } else if (imm == 0b01) { // big endian compression ++ /* If IMM=0b00001, let pcv be the permute control vector required to ++ enable a left-indexed permute (vperm or xxperm) to implement a ++ compression of the sparse byte elements in a source vector specified ++ by the byte-element mask in VSR[VRB+32] into the leftmost byte ++ elements of a result vector. ++ */ ++ for( index = 0; index < 16; index++) { ++ i = 15 - index; ++ shift_by = i*8; ++ ++ if ( i >= 8) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 7; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ if (j >= 8) ++ result[1] |= (index) << (15 - j)*8; ++ else ++ result[0] |= (index) << (7 - j)*8; ++ j++; ++ } ++ } ++ /* The algorithim says set to undefined, leave as 0 ++ for( index = 3 - j; index < 4; index++) { ++ result |= (0 << (index*8)); ++ } ++ */ ++ ++ } else if (imm == 0b10) { //little-endian expansion ++ /* If IMM=0b00010, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement an ++ expansion of the rightmost byte elements of a source vector into the ++ byte elements of a result vector specified by the byte-element mask ++ in VSR[VRB+32]. */ ++ for( index = 0; index < 16; index++) { ++ i = index; ++ ++ shift_by = i*8; ++ ++ if ( i >= 8) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 7; ++ ++ /* mod shift amount by 8 since src is either the upper or lower ++ 64-bits. */ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ result[half_sel] |= j << shift_by; ++ j++; ++ } else { ++ result[half_sel] |= (index + (unsigned long long)0x10) << shift_by; ++ } ++ } ++ ++ } else if (imm == 0b11) { //little-endian compression ++ /* If IMM=0b00011, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement a ++ compression of the sparse byte elements in a source vector specified ++ by the byte-element mask in VSR[VRB+32] into the rightmost byte ++ elements of a result vector. */ ++ ++ for( index = 0; index < 16; index++) { ++ i = index; ++ ++ shift_by = i*8; ++ ++ if ( i >= 8) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 7; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ if (j >= 8) ++ result[0] |= (index) << (j-8)*8; ++ else ++ result[1] |= (index) << j*8; ++ j++; ++ } ++ } ++ ++ /* The algorithim says set to undefined, leave as 0 ++ for( index = 3 - j; index < 4; index++) { ++ result |= (0 << (index*8)); ++ } ++ */ ++ ++ } else { ++ vex_printf("ERROR, vector_gen_pvc_byte_mask_dirty_helper, imm value %u not supported.\n", ++ imm); ++ vassert(0); ++ } ++ write_VSX_entry( gst, reg_offset, result); ++} ++ ++/* CALLED FROM GENERATED CODE */ ++void vector_gen_pvc_hword_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ULong src_lo, ++ UInt reg_offset, ++ UInt imm ) { ++ /* The function computes the 128-bit result then writes it directly ++ into the guest state VSX register. */ ++ UInt i, shift_by, sel_shift_by, half_sel; ++ ULong index, src, result[2]; ++ ULong j; ++ ++ result[0] = 0; ++ result[1] = 0; ++ j = 0; ++ ++ /* The algorithm in the ISA is written with IBM numbering zero on left and ++ N-1 on right. The loop index is converted to "i" to match the algorithm ++ for claritiy of matching the C code to the algorithm in the ISA. */ ++ ++ if (imm == 0b00) { // big endian expansion ++ /* If IMM=0b00000, let pcv be the permute control vector required to ++ enable a left-indexed permute (vperm or xxperm) to implement an ++ expansion of the leftmost halfword elements of a source vector into ++ the halfword elements of a result vector specified by the halfword- ++ element mask in VSR[VRB+32]. ++ */ ++ for( index = 0; index < 8; index++) { ++ i = 7 - index; ++ ++ shift_by = i*16; ++ ++ if ( i >= 4) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 15; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ // half-word i, byte 0 ++ result[half_sel] |= (2*j + 0x0) << (shift_by+8); ++ // half-word i, byte 1 ++ result[half_sel] |= (2*j + 0x1) << shift_by; ++ j++; ++ } else { ++ result[half_sel] |= (2*index + 0x10) << (shift_by+8); ++ result[half_sel] |= (2*index + 0x11) << shift_by; ++ } ++ } ++ ++ } else if (imm == 0b01) { // big endian expansion ++ /* If IMM=0b00001,let pcv be the permute control vector required to ++ enable a left-indexed permute (vperm or xxperm) to implement a ++ compression of the sparse halfword elements in a source vector ++ specified by the halfword-element mask in VSR[VRB+32] into the ++ leftmost halfword elements of a result vector. ++ */ ++ for( index = 0; index < 8; index++) { ++ i = 7 - index; ++ ++ shift_by = i*16; ++ ++ if ( i >= 4) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 15; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ if (j >= 4) { ++ // half-word i, byte 0 ++ result[1] |= (2*index + 0x0) << ((7 - j)*16 + 8); ++ // half-word i, byte 1 ++ result[1] |= (2*index + 0x1) << ((7 - j)*16); ++ } else { ++ // half-word i, byte 0 ++ result[0] |= (2*index + 0x0) << ((3 - j)*16 + 8); ++ // half-word i, byte 1 ++ result[0] |= (2*index + 0x1) << ((3 - j)*16); ++ } ++ j++; ++ } ++ } ++ ++ } else if (imm == 0b10) { //little-endian expansion ++ /* If IMM=0b00010, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement an ++ expansion of the rightmost halfword elements of a source vector into ++ the halfword elements of a result vector specified by the halfword- ++ element mask in VSR[VRB+32]. ++ */ ++ for( index = 0; index < 8; index++) { ++ i = index; ++ shift_by = i*16; ++ ++ if ( i >= 4) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 15; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ // half-word i, byte 0 ++ result[half_sel] |= (2*j + 0x00) << shift_by; ++ // half-word i, byte 1 ++ result[half_sel] |= (2*j + 0x01) << (shift_by+8); ++ j++; ++ ++ } else { ++ // half-word i, byte 0 ++ result[half_sel] |= (2*index + 0x10) << shift_by; ++ // half-word i, byte 1 ++ result[half_sel] |= (2*index + 0x11) << (shift_by+8); ++ } ++ } ++ ++ } else if (imm == 0b11) { //little-endian compression ++ /* If IMM=0b00011, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement a ++ compression of the sparse halfword elements in a source vector ++ specified by the halfword-element mask in VSR[VRB+32] into the ++ rightmost halfword elements of a result vector. */ ++ for( index = 0; index < 8; index++) { ++ i = index; ++ shift_by = i*16; ++ ++ if ( i >= 4) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 15; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ if (j >= 4) { ++ // half-word j, byte 0 ++ result[0] |= (2*index + 0x0) << ((j-4)*16); ++ // half-word j, byte 1 ++ result[0] |= (2*index + 0x1) << ((j-4)*16+8); ++ } else { ++ // half-word j, byte 0 ++ result[1] |= (2*index + 0x0) << (j*16); ++ // half-word j, byte 1 ++ result[1] |= (2*index + 0x1) << ((j*16)+8); ++ } ++ j++; ++ } ++ } ++ ++ } else { ++ vex_printf("ERROR, vector_gen_pvc_hword_dirty_mask_helper, imm value %u not supported.\n", ++ imm); ++ vassert(0); ++ } ++ write_VSX_entry( gst, reg_offset, result); ++} ++ ++/* CALLED FROM GENERATED CODE */ ++void vector_gen_pvc_word_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ULong src_lo, ++ UInt reg_offset, UInt imm ) { ++ /* The function computes the 128-bit result then writes it directly ++ into the guest state VSX register. */ ++ UInt i, shift_by, sel_shift_by, half_sel; ++ ULong index, src, result[2]; ++ ULong j; ++ ++ result[0] = 0; ++ result[1] = 0; ++ j = 0; ++ ++ /* The algorithm in the ISA is written with IBM numbering zero on left and ++ N-1 on right. The loop index is converted to "i" to match the algorithm ++ for claritiy of matching the C code to the algorithm in the ISA. */ ++ ++ if (imm == 0b00) { // big endian expansion ++ /* If IMM=0b00000, let pcv be the permute control vector required to ++ enable a left-indexed permute (vperm or xxperm) to implement an ++ expansion of the leftmost word elements of a source vector into the ++ word elements of a result vector specified by the word-element mask ++ in VSR[VRB+32]. ++ */ ++ for( index = 0; index < 4; index++) { ++ i = 3 - index; ++ ++ shift_by = i*32; ++ ++ if ( i >= 2) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 31; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ result[half_sel] |= (4*j+0) << (shift_by+24); // word i, byte 0 ++ result[half_sel] |= (4*j+1) << (shift_by+16); // word i, byte 1 ++ result[half_sel] |= (4*j+2) << (shift_by+8); // word i, byte 2 ++ result[half_sel] |= (4*j+3) << shift_by; // word i, byte 3 ++ j++; ++ } else { ++ result[half_sel] |= (4*index + 0x10) << (shift_by+24); ++ result[half_sel] |= (4*index + 0x11) << (shift_by+16); ++ result[half_sel] |= (4*index + 0x12) << (shift_by+8); ++ result[half_sel] |= (4*index + 0x13) << shift_by; ++ } ++ } ++ ++ } else if (imm == 0b01) { // big endian compression ++ /* If IMM=0b00001, let pcv be the permute control vector required to ++ enable a left-indexed permute (vperm or xxperm) to implement a ++ compression of the sparse word elements in a source vector specified ++ by the word-element mask in VSR[VRB+32] into the leftmost word ++ elements of a result vector. ++ */ ++ for( index = 0; index < 4; index++) { ++ i = 3 - index; ++ ++ shift_by = i*32; ++ ++ if ( i >= 2) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 31; ++ ++ if (((src >> sel_shift_by) & 0x1) == 1) { ++ if (j >= 2) { ++ // word j, byte 0 ++ result[1] |= (4*index+0) << ((3 - j)*32 + 24); ++ // word j, byte 1 ++ result[1] |= (4*index+1) << ((3 - j)*32 + 16); ++ // word j, byte 2 ++ result[1] |= (4*index+2) << ((3 - j)*32 + 8); ++ // word j, byte 3 ++ result[1] |= (4*index+3) << ((3 - j)*32 + 0); ++ } else { ++ result[0] |= (4*index+0) << ((1 - j)*32 + 24); ++ result[0] |= (4*index+1) << ((1 - j)*32 + 16); ++ result[0] |= (4*index+2) << ((1 - j)*32 + 8); ++ result[0] |= (4*index+3) << ((1 - j)*32 + 0); ++ } ++ j++; ++ } ++ } ++ ++ } else if (imm == 0b10) { //little-endian expansion ++ /* If IMM=0b00010, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement an ++ expansion of the rightmost word elements of a source vector into the ++ word elements of a result vector specified by the word-element mask ++ in VSR[VRB+32]. ++ */ ++ for( index = 0; index < 4; index++) { ++ i = index; ++ ++ shift_by = i*32; ++ ++ if ( i >= 2) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 31; ++ ++ if (((src >> sel_shift_by) & 0x1) == 1) { ++ result[half_sel] |= (4*j+0) << (shift_by + 0); // word j, byte 0 ++ result[half_sel] |= (4*j+1) << (shift_by + 8); // word j, byte 1 ++ result[half_sel] |= (4*j+2) << (shift_by + 16); // word j, byte 2 ++ result[half_sel] |= (4*j+3) << (shift_by + 24); // word j, byte 3 ++ j++; ++ } else { ++ result[half_sel] |= (4*index + 0x10) << (shift_by + 0); ++ result[half_sel] |= (4*index + 0x11) << (shift_by + 8); ++ result[half_sel] |= (4*index + 0x12) << (shift_by + 16); ++ result[half_sel] |= (4*index + 0x13) << (shift_by + 24); ++ } ++ } ++ ++ } else if (imm == 0b11) { //little-endian compression ++ /* If IMM=0b00011, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement a ++ compression of the sparse word elements in a source vector specified ++ by the word-element mask in VSR[VRB+32] into the rightmost word ++ elements of a result vector. */ ++ for( index = 0; index < 4; index++) { ++ i =index; ++ ++ shift_by = i*32; ++ ++ if ( i >= 2) { ++ src = src_hi; ++ shift_by = shift_by - 64; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = shift_by + 31; ++ ++ if (((src >> sel_shift_by) & 0x1) == 1) { ++ if (j >= 2){ ++ // word j, byte 0 ++ result[0] |= (4*index + 0x0) << ((j-2)*32+0); ++ // word j, byte 1 ++ result[0] |= (4*index + 0x1) << ((j-2)*32+8); ++ // word j, byte 2 ++ result[0] |= (4*index + 0x2) << ((j-2)*32+16); ++ // word j, byte 3 ++ result[0] |= (4*index + 0x3) << ((j-2)*32+24); ++ } else { ++ result[1] |= (4*index + 0x0) << (j*32+0); ++ result[1] |= (4*index + 0x1) << (j*32+8); ++ result[1] |= (4*index + 0x2) << (j*32+16); ++ result[1] |= (4*index + 0x3) << (j*32+24); ++ } ++ j++; ++ } ++ } ++ } else { ++ vex_printf("ERROR, vector_gen_pvc_word_mask_dirty_helper, imm value %u not supported.\n", ++ imm); ++ vassert(0); ++ } ++ ++ write_VSX_entry( gst, reg_offset, result); ++} ++ ++/* CALLED FROM GENERATED CODE */ ++void vector_gen_pvc_dword_mask_dirty_helper( VexGuestPPC64State* gst, ++ ULong src_hi, ULong src_lo, ++ UInt reg_offset, UInt imm ) { ++ /* The function computes the 128-bit result then writes it directly ++ into the guest state VSX register. */ ++ UInt sel_shift_by, half_sel; ++ ULong index, src, result[2]; ++ ULong j, i; ++ ++ result[0] = 0; ++ result[1] = 0; ++ j = 0; ++ ++ /* The algorithm in the ISA is written with IBM numbering zero on left and ++ N-1 on right. The loop index is converted to "i" to match the algorithm ++ for claritiy of matching the C code to the algorithm in the ISA. */ ++ ++ if (imm == 0b00) { // big endian expansion ++ /* If IMM=0b00000, let pcv be the permute control vector required to ++ enable a left-indexed permute (vperm or xxperm) to implement an ++ expansion of the leftmost doubleword elements of a source vector into ++ the doubleword elements of a result vector specified by the ++ doubleword-element mask in VSR[VRB+32]. ++ */ ++ for( index = 0; index < 2; index++) { ++ i = 1 - index; ++ ++ if ( i == 1) { ++ src = src_hi; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = 63; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ result[half_sel] |= (8*j + 0x0) << 56; // dword i, byte 0 ++ result[half_sel] |= (8*j + 0x1) << 48; // dword i, byte 1 ++ result[half_sel] |= (8*j + 0x2) << 40; // dword i, byte 2 ++ result[half_sel] |= (8*j + 0x3) << 32; // dword i, byte 3 ++ result[half_sel] |= (8*j + 0x4) << 24; // dword i, byte 4 ++ result[half_sel] |= (8*j + 0x5) << 16; // dword i, byte 5 ++ result[half_sel] |= (8*j + 0x6) << 8; // dword i, byte 6 ++ result[half_sel] |= (8*j + 0x7) << 0; // dword i, byte 7 ++ j++; ++ } else { ++ result[half_sel] |= (8*index + 0x10) << 56; ++ result[half_sel] |= (8*index + 0x11) << 48; ++ result[half_sel] |= (8*index + 0x12) << 40; ++ result[half_sel] |= (8*index + 0x13) << 32; ++ result[half_sel] |= (8*index + 0x14) << 24; ++ result[half_sel] |= (8*index + 0x15) << 16; ++ result[half_sel] |= (8*index + 0x16) << 8; ++ result[half_sel] |= (8*index + 0x17) << 0; ++ } ++ } ++ } else if (imm == 0b01) { // big endian compression ++ /* If IMM=0b00001, let pcv be the the permute control vector required to ++ enable a left-indexed permute (vperm or xxperm) to implement a ++ compression of the sparse doubleword elements in a source vector ++ specified by the doubleword-element mask in VSR[VRB+32] into the ++ leftmost doubleword elements of a result vector. ++ */ ++ for( index = 0; index < 2; index++) { ++ i = 1 - index; ++ ++ if ( i == 1) { ++ src = src_hi; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = 63; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ if (j == 1) { ++ result[1] |= (8*index + 0x0) << 56; // double-word j, byte 0 ++ result[1] |= (8*index + 0x1) << 48; // double-word j, byte 1 ++ result[1] |= (8*index + 0x2) << 40; // double-word j, byte 2 ++ result[1] |= (8*index + 0x3) << 32; // double-word j, byte 3 ++ result[1] |= (8*index + 0x4) << 24; // double-word j, byte 4 ++ result[1] |= (8*index + 0x5) << 16; // double-word j, byte 5 ++ result[1] |= (8*index + 0x6) << 8; // double-word j, byte 6 ++ result[1] |= (8*index + 0x7) << 0; // double-word j, byte 7 ++ } else { ++ result[0] |= (8*index + 0x0) << 56; // double-word j, byte 0 ++ result[0] |= (8*index + 0x1) << 48; // double-word j, byte 1 ++ result[0] |= (8*index + 0x2) << 40; // double-word j, byte 2 ++ result[0] |= (8*index + 0x3) << 32; // double-word j, byte 3 ++ result[0] |= (8*index + 0x4) << 24; // double-word j, byte 4 ++ result[0] |= (8*index + 0x5) << 16; // double-word j, byte 5 ++ result[0] |= (8*index + 0x6) << 8; // double-word j, byte 6 ++ result[0] |= (8*index + 0x7) << 0; // double-word j, byte 7 ++ } ++ j++; ++ } ++ } ++ } else if (imm == 0b10) { //little-endian expansion ++ /* If IMM=0b00010, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement an ++ expansion of the rightmost doubleword elements of a source vector ++ into the doubleword elements of a result vector specified by the ++ doubleword-element mask in VSR[VRB+32]. ++ */ ++ ++ for( index = 0; index < 2; index++) { ++ i = index; ++ ++ if ( i == 1) { ++ src = src_hi; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = 63; ++ ++ if ( ((src >> sel_shift_by) & 0x1) == 1) { ++ result[half_sel] |= (8*j+0) << 0; // double-word i, byte 0 ++ result[half_sel] |= (8*j+1) << 8; // double-word i, byte 1 ++ result[half_sel] |= (8*j+2) << 16; // double-word i, byte 2 ++ result[half_sel] |= (8*j+3) << 24; // double-word i, byte 3 ++ result[half_sel] |= (8*j+4) << 32; // double-word i, byte 4 ++ result[half_sel] |= (8*j+5) << 40; // double-word i, byte 5 ++ result[half_sel] |= (8*j+6) << 48; // double-word i, byte 6 ++ result[half_sel] |= (8*j+7) << 56; // double-word i, byte 7 ++ j++; ++ } else { ++ result[half_sel] |= (8*index + 0x10) << 0; ++ result[half_sel] |= (8*index + 0x11) << 8; ++ result[half_sel] |= (8*index + 0x12) << 16; ++ result[half_sel] |= (8*index + 0x13) << 24; ++ result[half_sel] |= (8*index + 0x14) << 32; ++ result[half_sel] |= (8*index + 0x15) << 40; ++ result[half_sel] |= (8*index + 0x16) << 48; ++ result[half_sel] |= (8*index + 0x17) << 56; ++ } ++ } ++ ++ } else if (imm == 0b11) { //little-endian compression ++ /* If IMM=0b00011, let pcv be the permute control vector required to ++ enable a right-indexed permute (vpermr or xxpermr) to implement a ++ compression of the sparse doubleword elements in a source vector ++ specified by the doubleword-element mask in VSR[VRB+32] into the ++ rightmost doubleword elements of a result vector. */ ++ for( index = 0; index < 2; index++) { ++ i = index; ++ ++ if ( i == 1) { ++ src = src_hi; ++ half_sel = 0; ++ } else { ++ src = src_lo; ++ half_sel = 1; ++ } ++ ++ sel_shift_by = 63; ++ ++ if (((src >> sel_shift_by) & 0x1) == 1) { ++ if (j == 1) { ++ result[0] |= (8*index + 0x0) << 0; // double-word j, byte 0 ++ result[0] |= (8*index + 0x1) << 8; // double-word j, byte 1 ++ result[0] |= (8*index + 0x2) << 16; // double-word j, byte 2 ++ result[0] |= (8*index + 0x3) << 24; // double-word j, byte 3 ++ result[0] |= (8*index + 0x4) << 32; // double-word j, byte 4 ++ result[0] |= (8*index + 0x5) << 40; // double-word j, byte 5 ++ result[0] |= (8*index + 0x6) << 48; // double-word j, byte 6 ++ result[0] |= (8*index + 0x7) << 56; // double-word j, byte 7 ++ } else { ++ result[1] |= (8*index + 0x0) << 0; ++ result[1] |= (8*index + 0x1) << 8; ++ result[1] |= (8*index + 0x2) << 16; ++ result[1] |= (8*index + 0x3) << 24; ++ result[1] |= (8*index + 0x4) << 32; ++ result[1] |= (8*index + 0x5) << 40; ++ result[1] |= (8*index + 0x6) << 48; ++ result[1] |= (8*index + 0x7) << 56; ++ } ++ j++; ++ } ++ } ++ } else { ++ vex_printf("ERROR, vector_gen_pvc_dword_mask_helper, imm value %u not supported.\n", ++ imm); ++ vassert(0); ++ } ++ ++ write_VSX_entry( gst, reg_offset, result); ++} + + /*------------------------------------------------*/ + /*---- VSX Matrix signed integer GER functions ---*/ +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index bcabf69dd..354be6b53 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -3322,6 +3322,7 @@ static IRExpr * locate_vector_ele_eq ( IRTemp src, IRExpr *value, + #define DFORM_IMMASK 0xffffffff + #define DSFORM_IMMASK 0xfffffffc + #define DQFORM_IMMASK 0xfffffff0 ++#define DA8LSFORM_IMMASK 0x3fffffff // Algebraic 8LS Dform + + #define ISA_3_1_PREFIX_CHECK if (prefix) {if (!allow_isa_3_1) goto decode_noIsa3_1;} + +@@ -6109,6 +6110,87 @@ static void vsx_matrix_64bit_float_ger ( const VexAbiInfo* vbi, + stmt( IRStmt_Dirty(d) ); + } + ++static void vector_gen_pvc_mask ( const VexAbiInfo* vbi, ++ IRExpr *src, UInt IMM, ++ UInt opc2, UInt VSX_addr ) { ++ /* The function takes a 64-bit source and an immediate value. The function ++ calls a helper to execute the xxgenpcvbm, xxgenpcvhm, xxgenpcvwm, ++ xxgenpcvdm instruction. The instructions are not practical to do with ++ Iops. The instruction is implemented with a dirty helper that ++ calculates the 128-bit result and writes it directly into the guest ++ state VSX register. ++ */ ++ IRTemp src_hi = newTemp( Ity_I64); ++ IRTemp src_lo = newTemp( Ity_I64); ++ ++ IRDirty* d; ++ ++ vassert( (VSX_addr >= 0) && (VSX_addr < 64) ); ++ UInt reg_offset = offsetofPPCGuestState( guest_VSR0 ) ++ + sizeof(U128) * VSX_addr; ++ ++ assign( src_hi, unop( Iop_V128HIto64, src ) ); ++ assign( src_lo, unop( Iop_V128to64, src ) ); ++ ++ IRExpr** args = mkIRExprVec_5( ++ IRExpr_GSPTR(), ++ mkexpr( src_hi ), ++ mkexpr( src_lo ), ++ mkU32( reg_offset ), ++ mkU64( IMM ) ); ++ ++ switch( opc2 ) { ++ case 0x394: // xxgenpcvbm ++ d = unsafeIRDirty_0_N ( ++ 0 /*regparms*/, ++ "vector_gen_pvc_byte_mask_dirty_helper", ++ fnptr_to_fnentry( vbi, ++ &vector_gen_pvc_byte_mask_dirty_helper ), ++ args); ++ break; ++ ++ case 0x395: // xxgenpcvhm ++ d = unsafeIRDirty_0_N ( ++ 0 /*regparms*/, ++ "vector_gen_pvc_hword_mask_dirty_helper", ++ fnptr_to_fnentry( vbi, ++ &vector_gen_pvc_hword_mask_dirty_helper ), ++ args); ++ break; ++ ++ case 0x3B4: // xxgenpcvwm ++ d = unsafeIRDirty_0_N ( ++ 0 /*regparms*/, ++ "vector_gen_pvc_word_mask_dirty_helper", ++ fnptr_to_fnentry( vbi, ++ &vector_gen_pvc_word_mask_dirty_helper ), ++ args); ++ break; ++ ++ case 0x3B5: // xxgenpcvdm ++ d = unsafeIRDirty_0_N ( ++ 0 /*regparms*/, ++ "vector_gen_pvc_dword_mask_dirty_helper", ++ fnptr_to_fnentry( vbi, ++ &vector_gen_pvc_dword_mask_dirty_helper ), ++ args); ++ break; ++ default: ++ vex_printf("ERROR: Unkown instruction = %u in vector_gen_pvc_mask()\n", ++ opc2); ++ return; ++ } ++ ++ d->nFxState = 1; ++ vex_bzero(&d->fxState, sizeof(d->fxState)); ++ d->fxState[0].fx = Ifx_Modify; ++ d->fxState[0].size = sizeof(U128); ++ d->fxState[0].offset = reg_offset; ++ ++ /* execute the dirty call, side-effecting guest state */ ++ stmt( IRStmt_Dirty(d) ); ++} ++ + static IRExpr * UNSIGNED_CMP_GT_V128 ( IRExpr *vA, IRExpr *vB ) { + /* This function does an unsigned compare of two V128 values. The + * function is for use in 32-bit mode only as it is expensive. The +@@ -35227,6 +35309,54 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, + return True; + } + ++static Bool dis_vector_generate_pvc_from_mask ( UInt prefix, ++ UInt theInstr, ++ const VexAbiInfo* vbi ) ++{ ++ UChar XT_addr = ifieldRegXT(theInstr); ++ UChar vB_addr = ifieldRegB(theInstr); ++ IRTemp vB = newTemp( Ity_V128 ); ++ UInt opc2 = ifieldOPClo10(theInstr); ++ UInt IMM = IFIELD(theInstr, (31-15), 5); // bits[11:15] ++ ++ assign( vB, getVReg( vB_addr ) ); ++ ++ switch( opc2 ) { ++ case 0x394: ++ DIP("xxgenpcvbm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); ++ /* vector_gen_pvc_mask uses a dirty helper to calculate the result and ++ write it to the VSX result register. */ ++ vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); ++ break; ++ ++ case 0x395: ++ DIP("xxgenpcvhm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); ++ /* vector_gen_pvc_mask uses a dirty helper to calculate the result and ++ write it to the VSX result register. */ ++ vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); ++ break; ++ ++ case 0x3B4: ++ DIP("xxgenpcvwm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); ++ /* vector_gen_pvc_mask uses a dirty helper to calculate the result and ++ write it to the VSX result register. */ ++ vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); ++ break; ++ ++ case 0x3B5: ++ DIP("xxgenpcvdm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); ++ /* vector_gen_pvc_mask uses a dirty helper to calculate the result and ++ write it to the VSX result register. */ ++ vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); ++ break; ++ ++ default: ++ return False; ++ } ++ ++ return True; ++} ++ + static Int dis_nop_prefix ( UInt prefix, UInt theInstr ) + { + Bool is_prefix = prefix_instruction( prefix ); +@@ -35748,14 +35878,9 @@ DisResult disInstr_PPC_WRK ( + } + goto decode_failure; + +- case 0x31: // lfsu, stxv ++ case 0x31: // lfsu + if (!allow_F) goto decode_noF; +- if (prefix_instruction( prefix )) { // stxv +- if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; +- if (dis_fp_pair_prefix( prefix, theInstr )) goto decode_success; +- } else { // lfsu +- if (dis_fp_load( prefix, theInstr )) goto decode_success; +- } ++ if (dis_fp_load( prefix, theInstr )) goto decode_success; + goto decode_failure; + + case 0x32: +@@ -35842,7 +35967,6 @@ DisResult disInstr_PPC_WRK ( + case 0x39: // pld, lxsd, lxssp, lfdp + { + UInt opc2tmp = ifieldOPC0o2(theInstr); +- + if (!allow_F) goto decode_noF; + if (prefix_instruction( prefix )) { // pld + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; +@@ -36125,12 +36249,6 @@ DisResult disInstr_PPC_WRK ( + goto decode_failure; + } + +- /* The vsxOpc2 returned is the "normalized" value, representing the +- * instructions secondary opcode as taken from the standard secondary +- * opcode field [21:30] (IBM notatition), even if the actual field +- * is non-standard. These normalized values are given in the opcode +- * appendices of the ISA 2.06 document. +- */ + if ( ( opc2 == 0x168 ) && ( IFIELD( theInstr, 19, 2 ) == 0 ) )// xxspltib + { + /* This is a special case of the XX1 form where the RA, RB +@@ -36153,6 +36271,23 @@ DisResult disInstr_PPC_WRK ( + goto decode_failure; + } + ++ if ( ( opc2 == 0x394 ) || // xxgenpcvbm ++ ( opc2 == 0x395 ) || // xxgenpcvwm ++ ( opc2 == 0x3B4 ) || // xxgenpcvhm ++ ( opc2 == 0x3B5 ) ) { // xxgenpcvdm ++ if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; ++ if (dis_vector_generate_pvc_from_mask( prefix, theInstr, ++ abiinfo )) ++ goto decode_success; ++ goto decode_failure; ++ } ++ ++ /* The vsxOpc2 returned is the "normalized" value, representing the ++ * instructions secondary opcode as taken from the standard secondary ++ * opcode field [21:30] (IBM notatition), even if the actual field ++ * is non-standard. These normalized values are given in the opcode ++ * appendices of the ISA 2.06 document. ++ */ + vsxOpc2 = get_VSX60_opc2(opc2, theInstr); + + switch (vsxOpc2) { +commit 078f89e99b6f62e043f6138c6a7ae238befc1f2a +Author: Carl Love +Date: Fri Feb 26 15:46:55 2021 -0600 + + PPC64: Reduced-Precision - bfloat16 Outer Product & Format Conversion Operations + + Add support for: + + pmxvbf16ger2 Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) + pmxvbf16ger2pp Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive + multiply, Positive accumulate + pmxvbf16ger2pn Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive + multiply, Negative accumulate + pmxvbf16ger2np Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative + multiply, Positive accumulate + pmxvbf16ger2nn Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative + multiply, Negative accumulate + xvbf16ger2VSX Vector bfloat16 GER (Rank-2 Update) + xvbf16ger2pp VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive + accumulate + xvbf16ger2pn VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative + accumulate + xvbf16ger2np VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive + accumulate + xvbf16ger2nn VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative + accumulate + xvcvbf16sp VSX Vector Convert bfloat16 to Single-Precision format + xvcvspbf16 VSX Vector Convert with round Single-Precision to bfloat16 format + +diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h +index 54ce923a9..d36d6c07d 100644 +--- a/VEX/priv/guest_ppc_defs.h ++++ b/VEX/priv/guest_ppc_defs.h +@@ -150,6 +150,8 @@ extern ULong convert_to_zoned_helper( ULong src_hi, ULong src_low, + ULong return_upper ); + extern ULong convert_to_national_helper( ULong src, ULong return_upper ); + extern ULong convert_from_zoned_helper( ULong src_hi, ULong src_low ); ++extern ULong convert_from_floattobf16_helper( ULong src ); ++extern ULong convert_from_bf16tofloat_helper( ULong src ); + extern ULong convert_from_national_helper( ULong src_hi, ULong src_low ); + extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src ); + extern ULong extract_bits_under_mask_helper( ULong src, ULong mask, +@@ -201,6 +203,11 @@ extern void vector_gen_pvc_dword_mask_dirty_helper( VexGuestPPC64State* gst, + #define XVF16GER2PN 0b10010010 + #define XVF16GER2NP 0b01010010 + #define XVF16GER2NN 0b11010010 ++#define XVBF16GER2 0b00110011 ++#define XVBF16GER2PP 0b00110010 ++#define XVBF16GER2PN 0b10110010 ++#define XVBF16GER2NP 0b01110010 ++#define XVBF16GER2NN 0b11110010 + #define XVF32GER 0b00011011 + #define XVF32GERPP 0b00011010 + #define XVF32GERPN 0b10011010 +diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c +index 75497abb9..6bcee966d 100644 +--- a/VEX/priv/guest_ppc_helpers.c ++++ b/VEX/priv/guest_ppc_helpers.c +@@ -1905,6 +1905,125 @@ static Double conv_f16_to_double( ULong input ) + # endif + } + ++#define BF16_SIGN_MASK 0x8000 ++#define BF16_EXP_MASK 0x7F80 ++#define BF16_FRAC_MASK 0x007F ++#define BF16_BIAS 127 ++#define BF16_MAX_UNBIASED_EXP 127 ++#define BF16_MIN_UNBIASED_EXP -126 ++#define FLOAT_SIGN_MASK 0x80000000 ++#define FLOAT_EXP_MASK 0x7F800000 ++#define FLOAT_FRAC_MASK 0x007FFFFF ++#define FLOAT_FRAC_BIT8 0x00008000 ++#define FLOAT_BIAS 127 ++ ++static Float conv_bf16_to_float( UInt input ) ++{ ++ /* input is 16-bit bfloat. ++ bias +127, exponent 8-bits, fraction 7-bits ++ ++ output is 32-bit float. ++ bias +127, exponent 8-bits, fraction 22-bits ++ */ ++ ++ UInt input_exp, input_fraction, unbiased_exp; ++ UInt output_exp, output_fraction; ++ UInt sign; ++ union convert_t conv; ++ ++ sign = (UInt)(input & BF16_SIGN_MASK); ++ input_exp = input & BF16_EXP_MASK; ++ unbiased_exp = (input_exp >> 7) - (UInt)BF16_BIAS; ++ input_fraction = input & BF16_FRAC_MASK; ++ ++ if (((input_exp & BF16_EXP_MASK) == BF16_EXP_MASK) && ++ (input_fraction != 0)) { ++ /* input is NaN or SNaN, exp all 1's, fraction != 0 */ ++ output_exp = FLOAT_EXP_MASK; ++ output_fraction = input_fraction; ++ ++ } else if(((input_exp & BF16_EXP_MASK) == BF16_EXP_MASK) && ++ ( input_fraction == 0)) { ++ /* input is infinity, exp all 1's, fraction = 0 */ ++ output_exp = FLOAT_EXP_MASK; ++ output_fraction = 0; ++ ++ } else if((input_exp == 0) && (input_fraction == 0)) { ++ /* input is zero */ ++ output_exp = 0; ++ output_fraction = 0; ++ ++ } else if((input_exp == 0) && (input_fraction != 0)) { ++ /* input is denormal */ ++ output_fraction = input_fraction; ++ output_exp = (-(Int)BF16_BIAS + (Int)FLOAT_BIAS ) << 23; ++ ++ } else { ++ /* result is normal */ ++ output_exp = (unbiased_exp + FLOAT_BIAS) << 23; ++ output_fraction = input_fraction; ++ } ++ ++ conv.u32 = sign << (31 - 15) | output_exp | (output_fraction << (23-7)); ++ return conv.f; ++} ++ ++static UInt conv_float_to_bf16( UInt input ) ++{ ++ /* input is 32-bit float stored as unsigned 32-bit. ++ bias +127, exponent 8-bits, fraction 23-bits ++ ++ output is 16-bit bfloat. ++ bias +127, exponent 8-bits, fraction 7-bits ++ ++ If the unbiased exponent of the input is greater than the max floating ++ point unbiased exponent value, the result of the floating point 16-bit ++ value is infinity. ++ */ ++ ++ UInt input_exp, input_fraction; ++ UInt output_exp, output_fraction; ++ UInt result, sign; ++ ++ sign = input & FLOAT_SIGN_MASK; ++ input_exp = input & FLOAT_EXP_MASK; ++ input_fraction = input & FLOAT_FRAC_MASK; ++ ++ if (((input_exp & FLOAT_EXP_MASK) == FLOAT_EXP_MASK) && ++ (input_fraction != 0)) { ++ /* input is NaN or SNaN, exp all 1's, fraction != 0 */ ++ output_exp = BF16_EXP_MASK; ++ output_fraction = (ULong)input_fraction >> (23 - 7); ++ } else if (((input_exp & FLOAT_EXP_MASK) == FLOAT_EXP_MASK) && ++ ( input_fraction == 0)) { ++ /* input is infinity, exp all 1's, fraction = 0 */ ++ output_exp = BF16_EXP_MASK; ++ output_fraction = 0; ++ } else if ((input_exp == 0) && (input_fraction == 0)) { ++ /* input is zero */ ++ output_exp = 0; ++ output_fraction = 0; ++ } else if ((input_exp == 0) && (input_fraction != 0)) { ++ /* input is denormal */ ++ output_exp = 0; ++ output_fraction = (ULong)input_fraction >> (23 - 7); ++ } else { ++ /* result is normal */ ++ output_exp = (input_exp - BF16_BIAS + FLOAT_BIAS) >> (23 - 7); ++ output_fraction = (ULong)input_fraction >> (23 - 7); ++ ++ /* Round result. Look at the 8th bit position of the 32-bit floating ++ pointt fraction. The F16 fraction is only 7 bits wide so if the 8th ++ bit of the F32 is a 1 we need to round up by adding 1 to the output ++ fraction. */ ++ if ((input_fraction & FLOAT_FRAC_BIT8) == FLOAT_FRAC_BIT8) ++ /* Round the F16 fraction up by 1 */ ++ output_fraction = output_fraction + 1; ++ } ++ ++ result = sign >> (31 - 15) | output_exp | output_fraction; ++ return result; ++} + + static Float conv_double_to_float( Double src ) + { +@@ -1942,6 +2061,36 @@ static Float negate_float( Float input ) + return -input; + } + ++/* This C-helper takes a vector of two 32-bit floating point values ++ * and returns a vector containing two 16-bit bfloats. ++ input: word0 word1 ++ output 0x0 hword1 0x0 hword3 ++ Called from generated code. ++ */ ++ULong convert_from_floattobf16_helper( ULong src ) { ++ ULong resultHi, resultLo; ++ ++ resultHi = (ULong)conv_float_to_bf16( (UInt)(src >> 32)); ++ resultLo = (ULong)conv_float_to_bf16( (UInt)(src & 0xFFFFFFFF)); ++ return (resultHi << 32) | resultLo; ++ ++} ++ ++/* This C-helper takes a vector of two 16-bit bfloating point values ++ * and returns a vector containing one 32-bit float. ++ input: 0x0 hword1 0x0 hword3 ++ output: word0 word1 ++ */ ++ULong convert_from_bf16tofloat_helper( ULong src ) { ++ ULong result; ++ union convert_t conv; ++ conv.f = conv_bf16_to_float( (UInt)(src >> 32) ); ++ result = (ULong) conv.u32; ++ conv.f = conv_bf16_to_float( (UInt)(src & 0xFFFFFFFF)); ++ result = (result << 32) | (ULong) conv.u32; ++ return result; ++ } ++ + void vsx_matrix_16bit_float_ger_dirty_helper( VexGuestPPC64State* gst, + UInt offset_ACC, + ULong srcA_hi, ULong srcA_lo, +@@ -2002,24 +2151,44 @@ void vsx_matrix_16bit_float_ger_dirty_helper( VexGuestPPC64State* gst, + srcB_word[0][j] = (UInt)((srcB_lo >> (16-16*j)) & mask); + } + ++ /* Note the isa is not consistent in the src naming. Will use the ++ naming src10, src11, src20, src21 used with xvf16ger2 instructions. ++ */ + for( j = 0; j < 4; j++) { + if (((pmsk >> 1) & 0x1) == 0) { + src10 = 0; + src20 = 0; + } else { +- src10 = conv_f16_to_double((ULong)srcA_word[i][0]); +- src20 = conv_f16_to_double((ULong)srcB_word[j][0]); ++ if (( inst == XVF16GER2 ) || ( inst == XVF16GER2PP ) ++ || ( inst == XVF16GER2PN ) || ( inst == XVF16GER2NP ) ++ || ( inst == XVF16GER2NN )) { ++ src10 = conv_f16_to_double((ULong)srcA_word[i][0]); ++ src20 = conv_f16_to_double((ULong)srcB_word[j][0]); ++ } else { ++ /* Input is in bfloat format, result is stored in the ++ "traditional" 64-bit float format. */ ++ src10 = (double)conv_bf16_to_float((ULong)srcA_word[i][0]); ++ src20 = (double)conv_bf16_to_float((ULong)srcB_word[j][0]); ++ } + } + + if ((pmsk & 0x1) == 0) { + src11 = 0; + src21 = 0; + } else { +- src11 = conv_f16_to_double((ULong)srcA_word[i][1]); +- src21 = conv_f16_to_double((ULong)srcB_word[j][1]); ++ if (( inst == XVF16GER2 ) || ( inst == XVF16GER2PP ) ++ || ( inst == XVF16GER2PN ) || ( inst == XVF16GER2NP ) ++ || ( inst == XVF16GER2NN )) { ++ src11 = conv_f16_to_double((ULong)srcA_word[i][1]); ++ src21 = conv_f16_to_double((ULong)srcB_word[j][1]); ++ } else { ++ /* Input is in bfloat format, result is stored in the ++ "traditional" 64-bit float format. */ ++ src11 = (double)conv_bf16_to_float((ULong)srcA_word[i][1]); ++ src21 = (double)conv_bf16_to_float((ULong)srcB_word[j][1]); ++ } + } + +- + prod = src10 * src20; + msum = prod + src11 * src21; + +@@ -2027,26 +2196,26 @@ void vsx_matrix_16bit_float_ger_dirty_helper( VexGuestPPC64State* gst, + /* Note, we do not track the exception handling bits + ox, ux, xx, si, mz, vxsnan and vximz in the FPSCR. */ + +- if ( inst == XVF16GER2 ) ++ if (( inst == XVF16GER2 ) || ( inst == XVBF16GER2 ) ) + result[j] = reinterpret_float_as_int( + conv_double_to_float(msum) ); + +- else if ( inst == XVF16GER2PP ) ++ else if (( inst == XVF16GER2PP ) || (inst == XVBF16GER2PP )) + result[j] = reinterpret_float_as_int( + conv_double_to_float(msum) + + acc_word[j] ); + +- else if ( inst == XVF16GER2PN ) ++ else if (( inst == XVF16GER2PN ) || ( inst == XVBF16GER2PN )) + result[j] = reinterpret_float_as_int( + conv_double_to_float(msum) + + negate_float( acc_word[j] ) ); + +- else if ( inst == XVF16GER2NP ) ++ else if (( inst == XVF16GER2NP ) || ( inst == XVBF16GER2NP )) + result[j] = reinterpret_float_as_int( + conv_double_to_float( negate_double( msum ) ) + + acc_word[j] ); + +- else if ( inst == XVF16GER2NN ) ++ else if (( inst == XVF16GER2NN ) || ( inst == XVBF16GER2NN )) + result[j] = reinterpret_float_as_int( + conv_double_to_float( negate_double( msum ) ) + + negate_float( acc_word[j] ) ); +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 354be6b53..20553a539 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -5688,6 +5688,57 @@ static IRExpr * convert_from_national ( const VexAbiInfo* vbi, IRExpr *src ) { + return mkexpr( result ); + } + ++static IRExpr * vector_convert_floattobf16 ( const VexAbiInfo* vbi, ++ IRExpr *src ) { ++ /* The function takes 128-bit value containing four 32-bit floats and ++ returns a 128-bit value containint four 16-bit bfloats in the lower ++ halfwords. */ ++ ++ IRTemp resultHi = newTemp( Ity_I64); ++ IRTemp resultLo = newTemp( Ity_I64); ++ ++ assign( resultHi, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "vector_convert_floattobf16_helper", ++ fnptr_to_fnentry( vbi, ++ &convert_from_floattobf16_helper ), ++ mkIRExprVec_1( unop( Iop_V128HIto64, src ) ) ) ); ++ ++ assign( resultLo, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "vector_convert_floattobf16_helper", ++ fnptr_to_fnentry( vbi, ++ &convert_from_floattobf16_helper ), ++ mkIRExprVec_1( unop( Iop_V128to64, src ) ) ) ); ++ ++ return binop( Iop_64HLtoV128, mkexpr( resultHi ), mkexpr( resultLo ) ); ++} ++ ++static IRExpr * vector_convert_bf16tofloat ( const VexAbiInfo* vbi, ++ IRExpr *src ) { ++ /* The function takes 128-bit value containing four 16-bit bfloats in ++ the lower halfwords and returns a 128-bit value containint four ++ 32-bit floats. */ ++ IRTemp resultHi = newTemp( Ity_I64); ++ IRTemp resultLo = newTemp( Ity_I64); ++ ++ assign( resultHi, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "vector_convert_bf16tofloat_helper", ++ fnptr_to_fnentry( vbi, ++ &convert_from_bf16tofloat_helper ), ++ mkIRExprVec_1( unop( Iop_V128HIto64, src ) ) ) ); ++ ++ assign( resultLo, ++ mkIRExprCCall( Ity_I64, 0 /*regparms*/, ++ "vector_convert_bf16tofloat_helper", ++ fnptr_to_fnentry( vbi, ++ &convert_from_bf16tofloat_helper ), ++ mkIRExprVec_1( unop( Iop_V128to64, src ) ) ) ); ++ ++ return binop( Iop_64HLtoV128, mkexpr( resultHi ), mkexpr( resultLo ) ); ++} ++ + static IRExpr * popcnt64 ( const VexAbiInfo* vbi, + IRExpr *src ){ + /* The function takes a 64-bit source and counts the number of bits in the +@@ -5936,6 +5987,7 @@ static void vsx_matrix_ger ( const VexAbiInfo* vbi, + case XVI16GER2: + case XVI16GER2S: + case XVF16GER2: ++ case XVBF16GER2: + case XVF32GER: + AT_fx = Ifx_Write; + break; +@@ -5943,6 +5995,10 @@ static void vsx_matrix_ger ( const VexAbiInfo* vbi, + case XVI8GER4PP: + case XVI16GER2PP: + case XVI16GER2SPP: ++ case XVBF16GER2PP: ++ case XVBF16GER2PN: ++ case XVBF16GER2NP: ++ case XVBF16GER2NN: + case XVF16GER2PP: + case XVF16GER2PN: + case XVF16GER2NP: +@@ -23899,6 +23955,24 @@ dis_vxs_misc( UInt prefix, UInt theInstr, const VexAbiInfo* vbi, UInt opc2, + mkexpr( sub_element1 ), + mkexpr( sub_element0 ) ) ) ); + ++ } else if ((inst_select == 16) && !prefix) { ++ IRTemp result = newTemp(Ity_V128); ++ UChar xT_addr = ifieldRegXT ( theInstr ); ++ UChar xB_addr = ifieldRegXB ( theInstr ); ++ /* Convert 16-bit bfloat to 32-bit float, not a prefix inst */ ++ DIP("xvcvbf16sp v%u,v%u\n", xT_addr, xB_addr); ++ assign( result, vector_convert_bf16tofloat( vbi, mkexpr( vB ) ) ); ++ putVSReg( XT, mkexpr( result) ); ++ ++ } else if ((inst_select == 17) && !prefix) { ++ IRTemp result = newTemp(Ity_V128); ++ UChar xT_addr = ifieldRegXT ( theInstr ); ++ UChar xB_addr = ifieldRegXB ( theInstr ); ++ /* Convert 32-bit float to 16-bit bfloat, not a prefix inst */ ++ DIP("xvcvspbf16 v%u,v%u\n", xT_addr, xB_addr); ++ assign( result, vector_convert_floattobf16( vbi, mkexpr( vB ) ) ); ++ putVSReg( XT, mkexpr( result) ); ++ + } else if (inst_select == 23) { + DIP("xxbrd v%u, v%u\n", (UInt)XT, (UInt)XB); + +@@ -34956,6 +35030,41 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, + getVSReg( rB_addr ), AT, + ( ( inst_prefix << 8 ) | XO ) ); + break; ++ case XVBF16GER2: ++ DIP("xvbf16ger2 %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), AT, ++ ( ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2PP: ++ DIP("xvbf16ger2pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), AT, ++ ( ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2PN: ++ DIP("xvbf16ger2pn %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), AT, ++ ( ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2NP: ++ DIP("xvbf16ger2np %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), AT, ++ ( ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2NN: ++ DIP("xvbf16ger2nn %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), AT, ++ ( ( inst_prefix << 8 ) | XO ) ); ++ break; + case XVF32GER: + DIP("xvf32ger %u,r%u, r%u\n", AT, rA_addr, rB_addr); + vsx_matrix_ger( vbi, MATRIX_32BIT_FLOAT_GER, +@@ -35106,6 +35215,61 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, + AT, + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + break; ++ case XVBF16GER2: ++ PMSK = IFIELD( prefix, 14, 2); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvbf16ger2 %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), ++ AT, ( (MASKS << 9 ) ++ | ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2PP: ++ PMSK = IFIELD( prefix, 14, 2); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvbf16ger2pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), ++ AT, ( (MASKS << 9 ) ++ | ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2PN: ++ PMSK = IFIELD( prefix, 14, 2); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvbf16ger2pn %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), ++ AT, ( (MASKS << 9 ) ++ | ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2NP: ++ PMSK = IFIELD( prefix, 14, 2); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvbf16ger2np %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), ++ AT, ( (MASKS << 9 ) ++ | ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVBF16GER2NN: ++ PMSK = IFIELD( prefix, 14, 2); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvbf16ger2nn %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, ++ getVSReg( rA_addr ), ++ getVSReg( rB_addr ), ++ AT, ( (MASKS << 9 ) ++ | ( inst_prefix << 8 ) | XO ) ); ++ break; + case XVF16GER2: + PMSK = IFIELD( prefix, 14, 2); + XMSK = IFIELD( prefix, 4, 4); +@@ -36181,6 +36345,11 @@ DisResult disInstr_PPC_WRK ( + (opc2 == XVI4GER8PP) || // xvi4ger8pp + (opc2 == XVI8GER4) || // xvi8ger4 + (opc2 == XVI8GER4PP) || // xvi8ger4pp ++ (opc2 == XVBF16GER2) || // xvbf16ger2 ++ (opc2 == XVBF16GER2PP) || // xvbf16ger2pp ++ (opc2 == XVBF16GER2PN) || // xvbf16ger2pn ++ (opc2 == XVBF16GER2NP) || // xvbf16ger2np ++ (opc2 == XVBF16GER2NN) || // xvbf16ger2nn + (opc2 == XVF16GER2) || // xvf16ger2 + (opc2 == XVF16GER2PP) || // xvf16ger2pp + (opc2 == XVF16GER2PN) || // xvf16ger2pn +commit e09fdaf569b975717465ed8043820d0198d4d47d +Author: Carl Love +Date: Fri Feb 26 16:05:12 2021 -0600 + + PPC64: Reduced-Precision: Missing Integer-based Outer Product Operations + + Add support for: + + pmxvi16ger2 VSX Vector 16-bit Signed Integer GER (rank-2 update), Prefixed + Masked + pmxvi16ger2pp VSX Vector 16-bit Signed Integer GER (rank-2 update) (Positive + multiply, Positive accumulate), Prefixed Masked + pmxvi8ger4spp VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with + Saturation (Positive multiply, Positive accumulate), Prefixed Masked + xvi16ger2 VSX Vector 16-bit Signed Integer GER (rank-2 update) + xvi16ger2pp VSX Vector 16-bit Signed Integer GER (rank-2 update) (Positive + multiply, Positive accumulate) + xvi8ger4spp VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with + Saturation (Positive multiply, Positive accumulate) + +diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c +index 6bcee966d..d8131eb60 100644 +--- a/VEX/priv/guest_ppc_helpers.c ++++ b/VEX/priv/guest_ppc_helpers.c +@@ -1446,16 +1446,16 @@ static UInt exts4( UInt src) + return src & 0xF; /* make sure high order bits are zero */ + } + +-static UInt exts8( UInt src) ++static ULong exts8( UInt src) + { +- /* Input is an 8-bit value. Extend bit 7 to bits [31:8] */ ++ /* Input is an 8-bit value. Extend bit 7 to bits [63:8] */ + if (( src >> 7 ) & 0x1) +- return src | 0xFFFFFF00; /* sign bit is a 1, extend */ ++ return src | 0xFFFFFFFFFFFFFF00ULL; /* sign bit is a 1, extend */ + else + return src & 0xFF; /* make sure high order bits are zero */ + } + +-static UInt extz8( UInt src) ++static ULong extz8( UInt src) + { + /* Input is an 8-bit value. Extend src on the left with zeros. */ + return src & 0xFF; /* make sure high order bits are zero */ +@@ -1662,12 +1662,12 @@ void vsx_matrix_8bit_ger_dirty_helper( VexGuestPPC64State* gst, + ULong srcB_hi, ULong srcB_lo, + UInt masks_inst ) + { +- UInt i, j, mask, sum, inst, acc_entry, prefix_inst; ++ UInt i, j, mask, inst, acc_entry, prefix_inst; + + UInt srcA_bytes[4][4]; /* word, byte */ + UInt srcB_bytes[4][4]; /* word, byte */ + UInt acc_word[4]; +- UInt prod0, prod1, prod2, prod3; ++ ULong prod0, prod1, prod2, prod3, sum; + UInt result[4]; + UInt pmsk = 0; + UInt xmsk = 0; +@@ -1742,10 +1742,13 @@ void vsx_matrix_8bit_ger_dirty_helper( VexGuestPPC64State* gst, + sum = prod0 + prod1 + prod2 + prod3; + + if ( inst == XVI8GER4 ) +- result[j] = sum; ++ result[j] = chop64to32( sum ); + + else if ( inst == XVI8GER4PP ) +- result[j] = sum + acc_word[j]; ++ result[j] = chop64to32( sum + acc_word[j] ); ++ ++ else if ( inst == XVI8GER4SPP ) ++ result[j] = clampS64toS32(sum + acc_word[j]); + + } else { + result[j] = 0; +@@ -1821,7 +1824,7 @@ void vsx_matrix_16bit_ger_dirty_helper( VexGuestPPC64State* gst, + else + prod1 = exts16to64( srcA_word[i][1] ) + * exts16to64( srcB_word[j][1] ); +- /* sum is UInt so the result is choped to 32-bits */ ++ + sum = prod0 + prod1; + + if ( inst == XVI16GER2 ) +@@ -1830,13 +1833,11 @@ void vsx_matrix_16bit_ger_dirty_helper( VexGuestPPC64State* gst, + else if ( inst == XVI16GER2S ) + result[j] = clampS64toS32( sum ); + +- else if ( inst == XVI16GER2PP ) { ++ else if ( inst == XVI16GER2PP ) + result[j] = chop64to32( sum + acc_word[j] ); +- } + +- else if ( inst == XVI16GER2SPP ) { ++ else if ( inst == XVI16GER2SPP ) + result[j] = clampS64toS32( sum + acc_word[j] ); +- } + + } else { + result[j] = 0; +diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c +index 20553a539..e54f0f389 100644 +--- a/VEX/priv/guest_ppc_toIR.c ++++ b/VEX/priv/guest_ppc_toIR.c +@@ -5993,6 +5993,7 @@ static void vsx_matrix_ger ( const VexAbiInfo* vbi, + break; + case XVI4GER8PP: + case XVI8GER4PP: ++ case XVI8GER4SPP: + case XVI16GER2PP: + case XVI16GER2SPP: + case XVBF16GER2PP: +@@ -34983,6 +34984,12 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, + getVSReg( rA_addr ), getVSReg( rB_addr ), + AT, ( ( inst_prefix << 8 ) | XO ) ); + break; ++ case XVI8GER4SPP: ++ DIP("xvi8ger4spp %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, ++ getVSReg( rA_addr ), getVSReg( rB_addr ), ++ AT, ( ( inst_prefix << 8 ) | XO ) ); ++ break; + case XVI16GER2S: + DIP("xvi16ger2s %u,r%u, r%u\n", AT, rA_addr, rB_addr); + vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, +@@ -34995,6 +35002,19 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, + getVSReg( rA_addr ), getVSReg( rB_addr ), + AT, ( ( inst_prefix << 8 ) | XO ) ); + break; ++ case XVI16GER2: ++ DIP("xvi16ger2 %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, ++ getVSReg( rA_addr ), getVSReg( rB_addr ), ++ AT, ( ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVI16GER2PP: ++ DIP("xvi16ger2pp %u,r%u, r%u\n", AT, rA_addr, rB_addr); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, ++ getVSReg( rA_addr ), getVSReg( rB_addr ), ++ AT, ( ( inst_prefix << 8 ) | XO ) ); ++ break; ++ + case XVF16GER2: + DIP("xvf16ger2 %u,r%u, r%u\n", AT, rA_addr, rB_addr); + vsx_matrix_ger( vbi, MATRIX_16BIT_FLOAT_GER, +@@ -35193,6 +35213,39 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, + AT, + ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); + break; ++ case XVI8GER4SPP: ++ PMSK = IFIELD( prefix, 12, 4); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvi8ger4spp %u,r%u, r%u,%u,%u,%u\n", ++ AT, rA_addr, rB_addr, XMSK, YMSK, PMSK); ++ vsx_matrix_ger( vbi, MATRIX_8BIT_INT_GER, ++ getVSReg( rA_addr ), getVSReg( rB_addr ), ++ AT, ++ ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVI16GER2: ++ PMSK = IFIELD( prefix, 12, 4); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvi16ger2 %u,r%u, r%u,%u,%u,%u\n", ++ AT, rA_addr, rB_addr, XMSK, YMSK, PMSK); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, ++ getVSReg( rA_addr ), getVSReg( rB_addr ), ++ AT, ++ ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); ++ break; ++ case XVI16GER2PP: ++ PMSK = IFIELD( prefix, 12, 4); ++ XMSK = IFIELD( prefix, 4, 4); ++ YMSK = IFIELD( prefix, 0, 4); ++ DIP("pmxvi16ger2pp %u,r%u, r%u,%u,%u,%u\n", ++ AT, rA_addr, rB_addr, XMSK, YMSK, PMSK); ++ vsx_matrix_ger( vbi, MATRIX_16BIT_INT_GER, ++ getVSReg( rA_addr ), getVSReg( rB_addr ), ++ AT, ++ ( (MASKS << 9 ) | ( inst_prefix << 8 ) | XO ) ); ++ break; + case XVI16GER2S: + PMSK = IFIELD( prefix, 14, 2); + XMSK = IFIELD( prefix, 4, 4); +@@ -36345,6 +36398,9 @@ DisResult disInstr_PPC_WRK ( + (opc2 == XVI4GER8PP) || // xvi4ger8pp + (opc2 == XVI8GER4) || // xvi8ger4 + (opc2 == XVI8GER4PP) || // xvi8ger4pp ++ (opc2 == XVI8GER4SPP) || // xvi8ger4spp ++ (opc2 == XVI16GER2) || // xvi16ger2 ++ (opc2 == XVI16GER2PP) || // xvi16ger2pp + (opc2 == XVBF16GER2) || // xvbf16ger2 + (opc2 == XVBF16GER2PP) || // xvbf16ger2pp + (opc2 == XVBF16GER2PN) || // xvbf16ger2pn diff --git a/SOURCES/valgrind-3.17.0-s390_insn_as_string.patch b/SOURCES/valgrind-3.17.0-s390_insn_as_string.patch new file mode 100644 index 0000000..39c956c --- /dev/null +++ b/SOURCES/valgrind-3.17.0-s390_insn_as_string.patch @@ -0,0 +1,54 @@ +commit 45873298ff2d17accc65654d64758360616aade5 +Author: Andreas Arnez +Date: Tue Mar 30 18:10:43 2021 +0200 + + s390x: Add missing UNOP insns to s390_insn_as_string + + Some unary operator insns are not handled by s390_insn_as_string(). If + they are encountered while the appropriate trace flag is set, a vpanic + occurs. Fix this: add handling for the missing insns. + +diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c +index 8762975b2..6e0734ae0 100644 +--- a/VEX/priv/host_s390_defs.c ++++ b/VEX/priv/host_s390_defs.c +@@ -7860,12 +7860,24 @@ s390_insn_as_string(const s390_insn *insn) + op = "v-vunpacku"; + break; + +- case S390_VEC_FLOAT_NEG: +- op = "v-vfloatneg"; ++ case S390_VEC_ABS: ++ op = "v-vabs"; + break; + +- case S390_VEC_FLOAT_SQRT: +- op = "v-vfloatsqrt"; ++ case S390_VEC_COUNT_LEADING_ZEROES: ++ op = "v-vclz"; ++ break; ++ ++ case S390_VEC_COUNT_TRAILING_ZEROES: ++ op = "v-vctz"; ++ break; ++ ++ case S390_VEC_COUNT_ONES: ++ op = "v-vpopct"; ++ break; ++ ++ case S390_VEC_FLOAT_NEG: ++ op = "v-vfloatneg"; + break; + + case S390_VEC_FLOAT_ABS: +@@ -7876,6 +7888,10 @@ s390_insn_as_string(const s390_insn *insn) + op = "v-vfloatnabs"; + break; + ++ case S390_VEC_FLOAT_SQRT: ++ op = "v-vfloatsqrt"; ++ break; ++ + default: + goto fail; + } diff --git a/SOURCES/valgrind-3.9.0-cachegrind-improvements.patch b/SOURCES/valgrind-3.9.0-cachegrind-improvements.patch new file mode 100644 index 0000000..c2680b1 --- /dev/null +++ b/SOURCES/valgrind-3.9.0-cachegrind-improvements.patch @@ -0,0 +1,54 @@ +--- valgrind-3.8.1/cachegrind/cg_sim.c.jj 2011-10-26 23:24:32.000000000 +0200 ++++ valgrind-3.8.1/cachegrind/cg_sim.c 2011-12-09 17:31:19.256023683 +0100 +@@ -42,27 +42,30 @@ typedef struct { + Int size; /* bytes */ + Int assoc; + Int line_size; /* bytes */ +- Int sets; + Int sets_min_1; + Int line_size_bits; + Int tag_shift; +- HChar desc_line[128]; /* large enough */ + UWord* tags; +-} cache_t2; ++ HChar desc_line[128]; ++} cache_t2 ++#ifdef __GNUC__ ++__attribute__ ((aligned (8 * sizeof (Int)))) ++#endif ++; + + /* By this point, the size/assoc/line_size has been checked. */ + static void cachesim_initcache(cache_t config, cache_t2* c) + { +- Int i; ++ Int sets; + + c->size = config.size; + c->assoc = config.assoc; + c->line_size = config.line_size; + +- c->sets = (c->size / c->line_size) / c->assoc; +- c->sets_min_1 = c->sets - 1; ++ sets = (c->size / c->line_size) / c->assoc; ++ c->sets_min_1 = sets - 1; + c->line_size_bits = VG_(log2)(c->line_size); +- c->tag_shift = c->line_size_bits + VG_(log2)(c->sets); ++ c->tag_shift = c->line_size_bits + VG_(log2)(sets); + + if (c->assoc == 1) { + VG_(sprintf)(c->desc_line, "%d B, %d B, direct-mapped", +@@ -72,11 +75,8 @@ static void cachesim_initcache(cache_t c + c->size, c->line_size, c->assoc); + } + +- c->tags = VG_(malloc)("cg.sim.ci.1", +- sizeof(UWord) * c->sets * c->assoc); +- +- for (i = 0; i < c->sets * c->assoc; i++) +- c->tags[i] = 0; ++ c->tags = VG_(calloc)("cg.sim.ci.1", ++ sizeof(UWord), sets * c->assoc); + } + + /* This attribute forces GCC to inline the function, getting rid of a diff --git a/SOURCES/valgrind-3.9.0-helgrind-race-supp.patch b/SOURCES/valgrind-3.9.0-helgrind-race-supp.patch new file mode 100644 index 0000000..759d151 --- /dev/null +++ b/SOURCES/valgrind-3.9.0-helgrind-race-supp.patch @@ -0,0 +1,15 @@ +--- valgrind/glibc-2.34567-NPTL-helgrind.supp.jj 2009-08-19 15:37:48.000000000 +0200 ++++ valgrind/glibc-2.34567-NPTL-helgrind.supp 2009-10-21 16:46:31.000000000 +0200 +@@ -88,6 +88,12 @@ + obj:*/lib*/libpthread-2.*so* + } + { ++ helgrind-glibc2X-102a ++ Helgrind:Race ++ fun:mythread_wrapper ++ obj:*vgpreload_helgrind*.so ++} ++{ + helgrind-glibc2X-103 + Helgrind:Race + fun:pthread_cond_*@@GLIBC_2.* diff --git a/SOURCES/valgrind-3.9.0-ldso-supp.patch b/SOURCES/valgrind-3.9.0-ldso-supp.patch new file mode 100644 index 0000000..d7a42c7 --- /dev/null +++ b/SOURCES/valgrind-3.9.0-ldso-supp.patch @@ -0,0 +1,28 @@ +--- valgrind/glibc-2.X.supp.in.jj 2011-10-26 23:24:45.000000000 +0200 ++++ valgrind/glibc-2.X.supp.in 2012-05-07 10:55:20.395942656 +0200 +@@ -124,7 +124,7 @@ + glibc-2.5.x-on-SUSE-10.2-(PPC)-2a + Memcheck:Cond + fun:index +- obj:*ld-@GLIBC_VERSION@.*.so ++ obj:*ld-@GLIBC_VERSION@*.so + } + { + glibc-2.5.x-on-SuSE-10.2-(PPC)-2b +@@ -136,14 +136,14 @@ + glibc-2.5.5-on-SuSE-10.2-(PPC)-2c + Memcheck:Addr4 + fun:index +- obj:*ld-@GLIBC_VERSION@.*.so ++ obj:*ld-@GLIBC_VERSION@*.so + } + { + glibc-2.3.5-on-SuSE-10.1-(PPC)-3 + Memcheck:Addr4 + fun:*wordcopy_fwd_dest_aligned* + fun:mem*cpy +- obj:*lib*@GLIBC_VERSION@.*.so ++ obj:*lib*@GLIBC_VERSION@*.so + } + + { diff --git a/SPECS/valgrind.spec b/SPECS/valgrind.spec new file mode 100644 index 0000000..2497a1b --- /dev/null +++ b/SPECS/valgrind.spec @@ -0,0 +1,1970 @@ +# For RHEL8 we need this before using any scl macro. +%global __python /usr/bin/python3 + +%{?scl:%scl_package valgrind} + +Summary: Tool for finding memory management bugs in programs +Name: %{?scl_prefix}valgrind +Version: 3.17.0 +Release: 6%{?dist} +Epoch: 1 +License: GPLv2+ +URL: http://www.valgrind.org/ + +# Only necessary for RHEL, will be ignored on Fedora + +# Are we building for a Software Collection? +%{?scl:%global is_scl 1} +%{!?scl:%global is_scl 0} + +# We never want the openmpi subpackage when building a software collecton. +# We always want it for fedora. +# We only want it for older rhel. But not s390x for too old rhel. +%if %{is_scl} + %global build_openmpi 0 +%else + %if 0%{?fedora} + %global build_openmpi 1 + %endif + %if 0%{?rhel} + %if 0%{?rhel} > 7 + %global build_openmpi 0 + %else + %ifarch s390x + %global build_openmpi (%{?rhel} > 6) + %else + %global build_openmpi 1 + %endif + %endif + %endif +%endif + +# We only want to build the valgrind-tools-devel package for Fedora proper +# as convenience. But not for DTS or RHEL. +%if %{is_scl} + %global build_tools_devel 0 +%else + %if 0%{?rhel} + %global build_tools_devel 0 + %else + %global build_tools_devel 1 + %endif +%endif + +# Whether to run the full regtest or only a limited set +# The full regtest includes gdb_server integration tests +# and experimental tools. +# Only run full regtests on fedora, but not on older rhel +# or when creating scl, the gdb_server tests might hang. +%if %{is_scl} + %global run_full_regtest 0 +%else + %if 0%{?fedora} + %global run_full_regtest 1 + %endif + %if 0%{?rhel} + %global run_full_regtest (%rhel >= 7) + %endif +%endif + +# Remove any pkgconfig provides for SCL devel packages. +# These should only be provided by the base packages. +%if %{is_scl} +%define __provides_exclude_from ^%{_libdir}/pkgconfig/.*.pc$ +%endif + +# Generating minisymtabs doesn't really work for the staticly linked +# tools. Note (below) that we don't strip the vgpreload libraries at all +# because valgrind might read and need the debuginfo in those (client) +# libraries for better error reporting and sometimes correctly unwinding. +# So those will already have their full symbol table. +%undefine _include_minidebuginfo + +Source0: ftp://sourceware.org/pub/valgrind/valgrind-%{version}.tar.bz2 + +# Needs investigation and pushing upstream +Patch1: valgrind-3.9.0-cachegrind-improvements.patch + +# KDE#211352 - helgrind races in helgrind's own mythread_wrapper +Patch2: valgrind-3.9.0-helgrind-race-supp.patch + +# Make ld.so supressions slightly less specific. +Patch3: valgrind-3.9.0-ldso-supp.patch + +# Add some stack-protector +Patch4: valgrind-3.16.0-some-stack-protector.patch + +# Add some -Wl,z,now. +Patch5: valgrind-3.16.0-some-Wl-z-now.patch + +# Upstream commits that provide additional ppc64le ISA 3.1 support +# commit 3cc0232c46a5905b4a6c2fbd302b58bf5f90b3d5 +# PPC64: ISA 3.1 VSX PCV Generate Operations +# commit 078f89e99b6f62e043f6138c6a7ae238befc1f2a +# PPC64: Reduced-Precision bfloat16 Outer Product & Format Conversion Operations +# commit e09fdaf569b975717465ed8043820d0198d4d47d +# PPC64: Reduced-Precision: Missing Integer-based Outer Product Operations +Patch6: valgrind-3.17.0-ppc64-isa-3.1.patch + +# Upstream commits that provide extra tests for ppc64le ISA 3.1 support +# commit c8fa838be405d7ac43035dcf675bf490800c26ec +# Reduced Precision bfloat16 outer product tests +# commit 4bcc6c8a97c10c4dd41b35bd3b3035ec4037d524 +# VSX Permute Control Vector Generate Operation tests. +# commit c589b652939655090c005a982a71f50c489fb5ce +# Reduced precision Missing Integer based outer tests +Patch7: valgrind-3.17.0-ppc64-isa-3.1-tests.patch + +# commit 45873298ff2d17accc65654d64758360616aade5 +# s390x: Add missing UNOP insns to s390_insn_as_string +Patch8: valgrind-3.17.0-s390_insn_as_string.patch + +# KDE#435908 Don't look for separate debuginfo if image already has .debug_info +Patch9: valgrind-3.17.0-debuginfod.patch + +# KDE#423963 Only process clone results in the parent thread +Patch10: valgrind-3.17.0-clone-parent-res.patch + +BuildRequires: make +BuildRequires: glibc-devel + +%if %{build_openmpi} +BuildRequires: openmpi-devel +%endif + +%if %{run_full_regtest} +BuildRequires: gdb +%endif + +# gdbserver_tests/filter_make_empty uses ps in test +BuildRequires: procps + +# Some testcases require g++ to build +BuildRequires: gcc-c++ + +# check_headers_and_includes uses Getopt::Long +%if 0%{?fedora} +BuildRequires: perl-generators +%endif +BuildRequires: perl(Getopt::Long) + +# We always autoreconf +BuildRequires: automake +BuildRequires: autoconf + +# For make check validating the documentation +BuildRequires: docbook-dtds + +# configure might use which +BuildRequires: which + +# For testing debuginfod-find +%if 0%{?fedora} > 29 || 0%{?rhel} > 7 +BuildRequires: elfutils-debuginfod-client +# For using debuginfod at runtime +Recommends: elfutils-debuginfod-client +%endif + +%{?scl:Requires:%scl_runtime} + +# We need to fixup selinux file context when doing a scl build. +# In RHEL6 we might need to fix up the labels even though the +# meta package sets up a fs equivalence. See post. +%if 0%{?rhel} == 6 +%{?scl:Requires(post): /sbin/restorecon} +%endif + +# We could use %%valgrind_arches as defined in redhat-rpm-config +# But that is really for programs using valgrind, it defines the +# set of architectures that valgrind works correctly on. +ExclusiveArch: %{ix86} x86_64 ppc ppc64 ppc64le s390x armv7hl aarch64 + +# Define valarch, the architecture name that valgrind uses +# And only_arch, the configure option to only build for that arch. +%ifarch %{ix86} +%define valarch x86 +%define only_arch --enable-only32bit +%endif +%ifarch x86_64 +%define valarch amd64 +%define only_arch --enable-only64bit +%endif +%ifarch ppc +%define valarch ppc32 +%define only_arch --enable-only32bit +%endif +%ifarch ppc64 +%define valarch ppc64be +%define only_arch --enable-only64bit +%endif +%ifarch ppc64le +%define valarch ppc64le +%define only_arch --enable-only64bit +%endif +%ifarch s390x +%define valarch s390x +%define only_arch --enable-only64bit +%endif +%ifarch armv7hl +%define valarch arm +%define only_arch --enable-only32bit +%endif +%ifarch aarch64 +%define valarch arm64 +%define only_arch --enable-only64bit +%endif + +%description +Valgrind is an instrumentation framework for building dynamic analysis +tools. There are Valgrind tools that can automatically detect many +memory management and threading bugs, and profile your programs in +detail. You can also use Valgrind to build new tools. The Valgrind +distribution currently includes six production-quality tools: a memory +error detector (memcheck, the default tool), two thread error +detectors (helgrind and drd), a cache and branch-prediction profiler +(cachegrind), a call-graph generating cache and branch-prediction +profiler (callgrind), and a heap profiler (massif). + +%package devel +Summary: Development files for valgrind aware programs +Requires: %{?scl_prefix}valgrind = %{epoch}:%{version}-%{release} + +%description devel +Header files and libraries for development of valgrind aware programs. + +%if %{build_tools_devel} +%package tools-devel +Summary: Development files for building valgrind tools. +Requires: %{?scl_prefix}valgrind-devel = %{epoch}:%{version}-%{release} +Provides: %{name}-static = %{epoch}:%{version}-%{release} + +%description tools-devel +Header files and libraries for development of valgrind tools. +%endif + +%if %{build_openmpi} +%package openmpi +Summary: OpenMPI support for valgrind +Requires: %{?scl_prefix}valgrind = %{epoch}:%{version}-%{release} + +%description openmpi +A wrapper library for debugging OpenMPI parallel programs with valgrind. +See the section on Debugging MPI Parallel Programs with Valgrind in the +Valgrind User Manual for details. +%endif + +%prep +%setup -q -n %{?scl:%{pkg_name}}%{!?scl:%{name}}-%{version} + +%patch1 -p1 +%patch2 -p1 +%patch3 -p1 + +# Old rhel gcc doesn't have -fstack-protector-strong. +%if 0%{?fedora} || 0%{?rhel} >= 7 +%patch4 -p1 +%patch5 -p1 +%endif + +%patch6 -p1 +%patch7 -p1 + +%patch8 -p1 +%patch9 -p1 +%patch10 -p1 + +%build + +# Some patches (might) touch Makefile.am or configure.ac files. +# Just always autoreconf so we don't need patches to prebuild files. +./autogen.sh + +# Old openmpi-devel has version depended paths for mpicc. +%if %{build_openmpi} +%if 0%{?fedora} >= 13 || 0%{?rhel} >= 6 +%define mpiccpath %{!?scl:%{_libdir}}%{?scl:%{_root_libdir}}/openmpi/bin/mpicc +%else +%define mpiccpath %{!?scl:%{_libdir}}%{?scl:%{_root_libdir}}/openmpi/*/bin/mpicc +%endif +%else +# We explicitly don't want the libmpi wrapper. So make sure that configure +# doesn't pick some random mpi compiler that happens to be installed. +%define mpiccpath /bin/false +%endif + +# Filter out "hardening" flags that don't make sense for valgrind. +# -fstack-protector just cannot work (valgrind would have to implement +# its own version since it doesn't link with glibc and handles stack +# setup itself). We patch some flags back in just for those helper +# programs where it does make sense. +# +# -Wl,-z,now doesn't make sense for static linked tools +# and would prevent using the vgpreload libraries on binaries that +# don't link themselves against libraries (like pthread) which symbols +# are needed (but only if the inferior itself would use them). +# +# -O2 doesn't work for the vgpreload libraries either. They are meant +# to not be optimized to show precisely what happened. valgrind adds +# -O2 itself wherever suitable. +# +# On ppc64[be] -fexceptions is troublesome. +# It might cause an undefined reference to `_Unwind_Resume' +# in libcoregrind-ppc64be-linux.a(libcoregrind_ppc64be_linux_a-readelf.o): +# In function `read_elf_symtab__ppc64be_linux. +# +# Also disable strict symbol checks because the vg_preload library +# will use hidden/undefined symbols from glibc like __libc_freeres. +%undefine _strict_symbol_defs_build + +%ifarch ppc64 +CFLAGS="`echo " %{optflags} " | sed 's/ -fstack-protector\([-a-z]*\) / / g;s/ -O2 / /g;s/ -fexceptions / /g;'`" +%else +CFLAGS="`echo " %{optflags} " | sed 's/ -fstack-protector\([-a-z]*\) / / g;s/ -O2 / /g;'`" +%endif +export CFLAGS + +# Older Fedora/RHEL only had __global_ldflags. +# Even older didn't even have that (so we don't need to scrub them). +%if 0%{?build_ldflags:1} +LDFLAGS="`echo " %{build_ldflags} " | sed 's/ -Wl,-z,now / / g;'`" +%else +%if 0%{?__global_ldflags:1} +LDFLAGS="`echo " %{__global_ldflags} " | sed 's/ -Wl,-z,now / / g;'`" +%endif +%endif +export LDFLAGS + +%configure \ + --with-mpicc=%{mpiccpath} \ + %{only_arch} \ + GDB=%{_bindir}/gdb + +make %{?_smp_mflags} + +%install +rm -rf $RPM_BUILD_ROOT +make DESTDIR=$RPM_BUILD_ROOT install +mkdir docs/installed +mv $RPM_BUILD_ROOT%{_datadir}/doc/valgrind/* docs/installed/ +rm -f docs/installed/*.ps + +# We want the MPI wrapper installed under the openmpi libdir so the script +# generating the MPI library requires picks them up and sets up the right +# openmpi libmpi.so requires. Install symlinks in the original/upstream +# location for backwards compatibility. +%if %{build_openmpi} +pushd $RPM_BUILD_ROOT%{_libdir} +mkdir -p openmpi/valgrind +cd valgrind +mv libmpiwrap-%{valarch}-linux.so ../openmpi/valgrind/ +ln -s ../openmpi/valgrind/libmpiwrap-%{valarch}-linux.so +popd +%endif + +%if %{build_tools_devel} +%ifarch %{ix86} x86_64 +# To avoid multilib clashes in between i?86 and x86_64, +# tweak installed a little bit. +for i in HAVE_PTHREAD_CREATE_GLIBC_2_0 HAVE_PTRACE_GETREGS HAVE_AS_AMD64_FXSAVE64; do + sed -i -e 's,^\(#define '$i' 1\|/\* #undef '$i' \*/\)$,#ifdef __x86_64__\n# define '$i' 1\n#endif,' \ + $RPM_BUILD_ROOT%{_includedir}/valgrind/config.h +done +%endif +%else +# Remove files we aren't going to package. +# See tools-devel files. +rm $RPM_BUILD_ROOT%{_includedir}/valgrind/config.h +rm $RPM_BUILD_ROOT%{_includedir}/valgrind/libvex*h +rm $RPM_BUILD_ROOT%{_includedir}/valgrind/pub_tool_*h +rm -rf $RPM_BUILD_ROOT%{_includedir}/valgrind/vki +rm $RPM_BUILD_ROOT%{_libdir}/valgrind/*.a +%endif + +# We don't want debuginfo generated for the vgpreload libraries. +# Turn off execute bit so they aren't included in the debuginfo.list. +# We'll turn the execute bit on again in %%files. +chmod 644 $RPM_BUILD_ROOT%{_libexecdir}/valgrind/vgpreload*-%{valarch}-*so + +%check +# Make sure some info about the system is in the build.log +# Add || true because rpm on copr EPEL6 acts weirdly and we don't want +# to break the build. +uname -a +rpm -q glibc gcc binutils || true +%if %{run_full_regtest} +rpm -q gdb || true +%endif + +LD_SHOW_AUXV=1 /bin/true +cat /proc/cpuinfo + +# Make sure a basic binary runs. There should be no errors. +./vg-in-place --error-exitcode=1 /bin/true --help + +# Build the test files with the software collection compiler if available. +%{?scl:PATH=%{_bindir}${PATH:+:${PATH}}} +# Make sure no extra CFLAGS, CXXFLAGS or LDFLAGS leak through, +# the testsuite sets all flags necessary. See also configure above. +make %{?_smp_mflags} CFLAGS="" CXXFLAGS="" LDFLAGS="" check + +# Workaround https://bugzilla.redhat.com/show_bug.cgi?id=1434601 +# for gdbserver tests. +export PYTHONCOERCECLOCALE=0 + +echo ===============TESTING=================== +%if %{run_full_regtest} + make regtest || : +%else + make nonexp-regtest || : +%endif + +# Make sure test failures show up in build.log +# Gather up the diffs (at most the first 20 lines for each one) +MAX_LINES=20 +diff_files=`find gdbserver_tests */tests -name '*.diff*' | sort` +if [ z"$diff_files" = z ] ; then + echo "Congratulations, all tests passed!" >> diffs +else + for i in $diff_files ; do + echo "=================================================" >> diffs + echo $i >> diffs + echo "=================================================" >> diffs + if [ `wc -l < $i` -le $MAX_LINES ] ; then + cat $i >> diffs + else + head -n $MAX_LINES $i >> diffs + echo "" >> diffs + fi + done +fi +cat diffs +echo ===============END TESTING=============== + +%files +%doc COPYING NEWS README_* +%doc docs/installed/html docs/installed/*.pdf +%{_bindir}/* +%dir %{_libexecdir}/valgrind +# Install everything in the libdir except the .so. +# The vgpreload so files might need file mode adjustment. +%{_libexecdir}/valgrind/*[^o] +# Turn on executable bit again for vgpreload libraries. +# Was disabled in %%install to prevent debuginfo stripping. +%attr(0755,root,root) %{_libexecdir}/valgrind/vgpreload*-%{valarch}-*so +%{_mandir}/man1/* + +%files devel +%dir %{_includedir}/valgrind +%{_includedir}/valgrind/valgrind.h +%{_includedir}/valgrind/callgrind.h +%{_includedir}/valgrind/drd.h +%{_includedir}/valgrind/helgrind.h +%{_includedir}/valgrind/memcheck.h +%{_includedir}/valgrind/dhat.h +%{_libdir}/pkgconfig/valgrind.pc + +%if %{build_tools_devel} +%files tools-devel +%{_includedir}/valgrind/config.h +%{_includedir}/valgrind/libvex*h +%{_includedir}/valgrind/pub_tool_*h +%{_includedir}/valgrind/vki +%dir %{_libdir}/valgrind +%{_libdir}/valgrind/*.a +%endif + +%if %{build_openmpi} +%files openmpi +%dir %{_libdir}/valgrind +%{_libdir}/openmpi/valgrind/libmpiwrap*.so +%{_libdir}/valgrind/libmpiwrap*.so +%endif + +%if 0%{?rhel} == 6 +%post +# There is a bug in rpm (rhbz#214737) that might cause post to be run +# even thought the binary isn't installed when installing two multilib +# versions at the same time. +if [ -x %{_bindir}/valgrind ]; then +# On RHEL6 the fs equivalency should be setup by the devtoolset meta +# package, but because of a rpm bug (rhbz#924044) it might not work. +%{?scl:/sbin/restorecon %{_bindir}/valgrind}%{!?scl:true} +fi +%endif + +%changelog +* Thu Jul 29 2021 Mark Wielaard - 3.17.0-6 +- Use __provides_exclude_from instead of filter_from_provides + +* Thu Jun 24 2021 Mark Wielaard - 3.17.0-5 +- Filter out pkgconfig provides + +* Thu Jun 3 2021 Mark Wielaard - 3.17.0-4 +- Update to upstream 3.17.0 final. +- Add valgrind-3.17.0-ppc64-isa-3.1{,tests}.patch +- Add valgrind-3.17.0-s390_insn_as_string.patch +- Add valgrind-3.17.0-debuginfod.patch +- Add valgrind-3.17.0-clone-parent-res.patch + +* Wed Oct 21 2020 Mark Wielaard - 3.16.0-4 +- Add valgrind-3.16.1-REX-prefix-JMP.patch +- Add valgrind-3.16.1-epoll.patch +- Add valgrind-3.16.1-sched_getsetattr.patch +- Add valgrind-3.16.1-dl_runtime_resolve.patch + +* Wed Jun 24 2020 Mark Wielaard - 3.16.0-3 +- Add valgrind-3.16.0-ppc-L-field.patch +- Add valgrind-3.16.0-387-float.patch + +* Thu May 28 2020 Mark Wielaard - 3.16.0-2 +- Apply stack-protector and -Wl,z,now patches. + +* Wed May 27 2020 Mark Wielaard - 3.16.0-1 +- Update to upstream valgrind 3.16.0 final. + +* Tue May 19 2020 Mark Wielaard - 3.16.0-0.4.RC2 +- Add docbook-dtds to BuildRequires. + +* Tue May 19 2020 Mark Wielaard - 3.16.0-0.3.RC2 +- Update to upstream 3.16.0 RC2 + +* Fri May 1 2020 Mark Wielaard - 3.16.0-0.2.GIT +- Update to upstream 3.16.0 branch point (commit 55cdb7c4e) + +* Fri Apr 17 2020 Mark Wielaard - 3.16.0-0.1.GIT +- Update to upstream 3.16.0-GIT (commit 52d02fe23) + - Drop all streamed patches. + +* Wed Mar 4 2020 Mark Wielaard - 3.15.0-20 +- Add valgrind-3.15.0-z15.patch + +* Fri Feb 28 2020 Mark Wielaard - 3.15.0-19 +- Add valgrind-3.15.0-time64.patch +- Add valgrind-3.15.0-arm-preadv2-pwritev2.patch +- Add valgrind-3.15.0-avx_estimate_insn-test.patch +- Add valgrind-3.15.0-gcc-10-x86-amd64-asm-test.patch + +* Fri Feb 14 2020 Mark Wielaard - 3.15.0-18 +- Add valgrind-3.15.0-ppc64-sigframe.patch + +* Thu Feb 13 2020 Mark Wielaard - 3.15.0-17 +- Add valgrind-3.15.0-glibc-dtv-supp.patch + +* Wed Jan 29 2020 Mark Wielaard - 3.15.0-16 +- Add valgrind-3.15.0-s390x-HRcVec128.patch + +* Wed Jan 29 2020 Mark Wielaard - 3.15.0-15 +- Don't use valgrind-3.15.0-ptrace-siginfo.patch on ppc64[le] +- Add valgrind-3.15.0-s390x-compare-and-signal.patch + +* Fri Jan 24 2020 Mark Wielaard - 3.15.0-14 +- Add valgrind-3.15.0-gcc-10-i686-asm-test.patch +- Add valgrind-3.15.0-gcc10-ppc64-asm-constraints.patch + +* Thu Jan 23 2020 Mark Wielaard - 3.15.0-13 +- Add valgrind-3.15.0-gcc-10-typedef-enum.patch + +* Mon Sep 23 2019 Mark Wielaard - 3.15.0-12 +- Add valgrind-3.15.0-ptrace-siginfo.patch + +* Mon Aug 5 2019 Mark Wielaard - 3.15.0-11 +- Add valgrind-3.15.0-preadv2-pwritev2.patch +- Add valgrind-3.15.0-arm-membarrier.patch +- Add valgrind-3.15.0-z14-misc.patch + +* Sat Jul 27 2019 Fedora Release Engineering - 1:3.15.0-10 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_31_Mass_Rebuild + +* Wed May 29 2019 Mark Wielaard - 3.15.0-9 +- Add valgrind-3.15.0-pkey.patch + +* Tue May 28 2019 Mark Wielaard - 3.15.0-8 +- Update valgrind-3.15.0-copy_file_range.patch. +- Add valgrind-3.15.0-avx-rdrand-f16c.patch. + +* Fri May 24 2019 Mark Wielaard - 3.15.0-7 +- Update valgrind-3.15.0-some-stack-protector.patch to include getoff. +- Add valgrind-3.15.0-some-Wl-z-now.patch + +* Fri May 24 2019 Mark Wielaard - 3.15.0-6 +- Add valgrind-3.15.0-s390x-wrap-drd.patch + +* Mon May 20 2019 Mark Wielaard - 3.15.0-5 +- Add valgrind-3.15.0-exp-sgcheck-no-aarch64.patch +- Add valgrind-3.15.0-scalar-arm64.patch +- Add valgrind-3.15.0-scalar-x86.patch + +* Tue May 7 2019 Mark Wielaard - 3.15.0-4 +- Add valgrind-3.15.0-arm64-ld-stpcpy.patch + +* Sun May 5 2019 Mark Wielaard - 3.15.0-3 +- Add valgrind-3.15.0-copy_file_range.patch + +* Thu Apr 25 2019 Mark Wielaard - 3.15.0-2 +- gdb has been fixed on fedora, run full regtests again. +- Add valgrind-3.15.0-ppc64-filter_gdb.patch + +* Tue Apr 16 2019 Mark Wielaard - 3.15.0-1 +- On ppc64[be] -fexceptions is troublesome. +- valgrind-3.15.0 final + Remove upstreamed patches + - valgrind-3.15.0-arm64-Ity_F16.patch + - valgrind-3.15.0-filter-libc-futex.patch + - valgrind-3.15.0-mmap-32bit.patch + +* Sun Apr 14 2019 Mark Wielaard - 3.15.0-0.8.RC2 +- Adding of stack-protector flag should only be done with newer gcc. +- Older rpm macros didn't provide build_ldflags. +- Add valgrind-3.15.0-arm64-Ity_F16.patch + +* Sun Apr 14 2019 Mark Wielaard - 3.15.0-0.7.RC2 +- Add valgrind-3.15.0-some-stack-protector.patch + +* Sat Apr 13 2019 Mark Wielaard - 3.15.0-0.6.RC2 +- Pass through most (hardening) flags, except -O2, -fstack-protector + and -Wl,-z,now. + +* Fri Apr 12 2019 Mark Wielaard - 3.15.0-0.5.RC2 +- No openmpi support on old s390x rhel. +- Disable s390x z13 support on rhel6 (too old binutils). +- Use an explicit ExclusiveArch, don't rely on %%valgrind_arches. +- Drop close_fds, it is no longer needed. +- Include any gdbserver_tests diffs for failing regtest. + +* Thu Apr 11 2019 Mark Wielaard - 3.15.0-0.4.RC2 +- Update to 3.15.0.RC2. +- Drop upstreamed patches: + - valgrind-3.15.0-s390x-get-startregs-constraint.patch + - valgrind-3.15.0-missing-a-c.patch + - valgrind-3.15.0-libstdc++-supp.patch + - valgrind-3.15.0-dhat-x86.patch + - valgrind-3.15.0-gdb-output1.patch + - valgrind-3.15.0-gdb-output2.patch +- Update valgrind-3.15.0-mmap-32bit.patch to upstream version. +- gdb on f30 and rawhide is currently broken, don't run_full_regtest. +- Any glibc-devel version is. +- Drop rhel5 special case for tools-devel. +- Use /bin/true --help as sanity test. + +* Wed Apr 10 2019 Mark Wielaard - 3.15.0-0.3.RC1 +- Enable full regtest on all fedora arches. +- Make sure that patched a.c is not newer than cgout-test. +- Update valgrind-3.15.0-gdb-output1.patch to upstream version. +- Add valgrind-3.15.0-filter-libc-futex.patch. +- Add valgrind-3.15.0-mmap-32bit.patch. + +* Tue Apr 9 2019 Mark Wielaard - 3.15.0-0.2.RC1 +- Add valgrind-3.15.0-s390x-get-startregs-constraint.patch +- Add valgrind-3.15.0-missing-a-c.patch +- Add valgrind-3.15.0-libstdc++-supp.patch +- Add valgrind-3.15.0-dhat-x86.patch +- Add valgrind-3.15.0-gdb-output1.patch +- Add valgrind-3.15.0-gdb-output2.patch + +* Mon Apr 8 2019 Mark Wielaard - 3.15.0-0.1.RC1 +- Remove patches to prebuild files and always ./autogen.sh. +- Only ever build primary arch. Put tools under libexec. +- Update to upstream 3.15.0-RC1. +- Drop all upstreamed patches. + +* Mon Mar 4 2019 Mark Wielaard - 3.14.0-16 +- Add valgrind-3.14.0-gettid.patch + +* Mon Mar 4 2019 Mark Wielaard - 3.14.0-15 +- Add valgrind-3.14.0-ppc64-quotactl.patch + +* Thu Feb 21 2019 Mark Wielaard - 3.14.0-14 +- Add valgrind-3.14.0-ppc-subfe.patch + +* Thu Feb 14 2019 Orion Poplawski - 1:3.14.0-13 +- Rebuild for openmpi 3.1.3 + +* Sun Feb 03 2019 Fedora Release Engineering - 1:3.14.0-12 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_30_Mass_Rebuild + +* Thu Jan 24 2019 Mark Wielaard - 3.14.0-11 +- Add valgrind-3.14.0-s390x-vec-facility-bit.patch. + +* Wed Jan 9 2019 Mark Wielaard - 3.14.0-10 +- Add valgrind-3.14.0-rsp-clobber.patch +- Add valgrind-3.14.0-subrange_type-count.patch + +* Mon Dec 31 2018 Mark Wielaard - 3.14.0-9 +- Add valgrind-3.14.0-vbit-test-sec.patch +- Add valgrind-3.14.0-x86-Iop_Sar64.patch +- Add valgrind-3.14.0-power9-addex.patch + +* Thu Dec 20 2018 Mark Wielaard - 3.14.0-8 +- Update valgrind-3.14.0-jm-vmx-constraints.patch for ppc64. +- Show all diff files in check, not just the main/default one. + +* Fri Dec 14 2018 Mark Wielaard - 3.14.0-7 +- Add valgrind-3.14.0-arm64-ptrace-traceme.patch +- Add valgrind-3.14.0-mc_translate-vecret.patch + +* Wed Dec 12 2018 Mark Wielaard - 3.14.0-6 +- Add valgrind-3.14.0-final_tidyup.patch +- Add valgrind-3.14.0-ppc64-ldbrx.patch +- Add valgrind-3.14.0-ppc64-unaligned-words.patch +- Add valgrind-3.14.0-ppc64-lxvd2x.patch +- Add valgrind-3.14.0-ppc64-unaligned-vecs.patch +- Add valgrind-3.14.0-ppc64-lxvb16x.patch +- Add valgrind-3.14.0-set_AV_CR6.patch +- Add valgrind-3.14.0-undef_malloc_args.patch +- Add valgrind-3.14.0-jm-vmx-constraints.patch +- Add valgrind-3.14.0-sigkill.patch +- Add valgrind-3.14.0-ppc64-ptrace.patch + +* Sat Dec 1 2018 Mark Wielaard - 3.14.0-5 +- Add valgrind-3.14.0-wcsncmp.patch (#1645971) +- Replace valgrind-3.14.0-s390x-vec-float-point-{code,test}.patch + with upstream versions. + +* Fri Nov 23 2018 Mark Wielaard - 3.14.0-4 +- Add valgrind-3.14.0-get_otrack_shadow_offset_wrk-ppc.patch, + valgrind-3.14.0-new-strlen-IROps.patch, + valgrind-3.14.0-ppc-instr-new-IROps.patch, + valgrind-3.14.0-memcheck-new-IROps.patch, + valgrind-3.14.0-ppc-frontend-new-IROps.patch, + valgrind-3.14.0-transform-popcount64-ctznat64.patch and + valgrind-3.14.0-enable-ppc-Iop_Sar_Shr8.patch (#1652926) + +* Wed Nov 21 2018 Mark Wielaard - 3.14.0-3 +- Add valgrind-3.14.0-s390z-more-z13-fixes.patch. + +* Tue Nov 20 2018 Mark Wielaard - 3.14.0-2 +- Add valgrind-3.14.0-s390x-fix-reg-alloc-vr-vs-fpr.patch. +- Add valgrind-3.14.0-s390x-sign-extend-lochi.patch. +- Add valgrind-3.14.0-s390x-vec-reg-vgdb.patch. +- Add valgrind-3.14.0-s390x-vec-float-point-code.patch + and valgrind-3.14.0-s390x-vec-float-point-tests.patch +- Disable full regtests on fedora everywhere. + +* Tue Oct 9 2018 Mark Wielaard - 3.14.0-1 +- valgrind 3.14.0 final. + +* Thu Oct 4 2018 Mark Wielaard - 3.14.0-0.2.RC2 +- Upgrade to RC2. +- Drop valgrind-3.14.0-add-vector-h.patch. + +* Fri Sep 14 2018 Mark Wielaard - 3.14.0-0.1.GIT +- New upstream (pre-)release. +- Add valgrind-3.14.0-add-vector-h.patch. + +* Fri Aug 10 2018 Mark Wielaard - 3.13.0-28 +- Add valgrind-3.13.0-utime.patch + +* Fri Aug 3 2018 Mark Wielaard - 3.13.0-27 +- Add valgrind-3.13.0-ppc64-xsmaxcdp.patch + +* Fri Aug 3 2018 Mark Wielaard - 3.13.0-26 +- Use valgrind_arches for ExclusiveArch when defined. +- Use restorecon for scl on rhel6 to work around rpm bug (#1610676). + +* Tue Jul 31 2018 Mark Wielaard - 3.13.0-25 +- Add valgrind-3.13.0-x86-arch_prctl.patch (#1610304) + +* Tue Jul 31 2018 Florian Weimer - 3.13.0-24 +- Rebuild with fixed binutils + +* Fri Jul 27 2018 Mark Wielaard - 3.13.0-23 +- Remove valgrind-3.13.0-arm-disable-vfp-test.patch + +* Thu Jul 26 2018 Mark Wielaard - 3.13.0-22 +- Add valgrind-3.13.0-arch_prctl.patch (#1608824) + +* Thu Jul 12 2018 Mark Wielaard - 3.13.0-21 +- Add valgrind-3.13.0-separate-code.patch (#1600034) +- Add valgrind-3.13.0-arm-disable-vfp-test.patch + +* Thu Jul 5 2018 Mark Wielaard - 3.13.0-20 +- Don't try a full_regtest under scl, also don't adjust PATH. + +* Thu Apr 12 2018 Mark Wielaard - 3.13.0-19 +- Improved valgrind-3.13.0-arm64-hwcap.patch +- Add valgrind-3.13.0-arm64-ptrace.patch + +* Thu Apr 12 2018 Mark Wielaard - 3.13.0-18 +- Add valgrind-3.13.0-build-id-phdrs.patch (#1566639) + +* Tue Feb 27 2018 Mark Wielaard - 3.13.0-17 +- Add valgrind-3.13.0-ppc64-mtfprwa-constraint.patch. + +* Fri Feb 09 2018 Fedora Release Engineering - 1:3.13.0-16 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_28_Mass_Rebuild + +* Tue Jan 23 2018 Mark Wielaard - 3.13.0-15 +- Split valgrind-tools-devel from valgrind-devel. +- Make building of libmpi wrapper explicit. + +* Mon Jan 22 2018 Mark Wielaard - 3.13.0-14 +- undefine _strict_symbol_defs_build. + +* Tue Jan 2 2018 Mark Wielaard - 3.13.0-13 +- Add additional fix to valgrind-3.13.0-debug-alt-file.patch. + +* Tue Dec 12 2017 Mark Wielaard - 3.13.0-12 +- Add valgrind-3.13.0-s390-cgijnl.patch. +- Use upstream version of valgrind-3.13.0-debug-alt-file.patch. + +* Sun Dec 10 2017 Mark Wielaard - 3.13.0-11 +- Add valgrind-3.13.0-debug-alt-file.patch. + +* Thu Nov 2 2017 Mark Wielaard - 3.13.0-10 +- Add valgrind-3.13.0-ppc64-timebase.patch. + +* Tue Oct 17 2017 Mark Wielaard - 3.13.0-9 +- Add valgrind-3.13.0-amd64-eflags-tests.patch +- Add valgrind-3.13.0-suppress-dl-trampoline-sse-avx.patch +- Add valgrind-3.13.0-static-tls.patch + +* Mon Oct 16 2017 Mark Wielaard - 3.13.0-8 +- Add valgrind-3.13.0-ppc64-vex-fixes.patch + +* Thu Aug 17 2017 Mark Wielaard - 3.13.0-7 +- Add valgrind-3.13.0-xml-socket.patch + +* Thu Aug 03 2017 Fedora Release Engineering - 1:3.13.0-6 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Binutils_Mass_Rebuild + +* Thu Jul 27 2017 Fedora Release Engineering - 1:3.13.0-5 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Mass_Rebuild + +* Fri Jul 7 2017 Mark Wielaard +- Add --error-exitcode=1 to /bin/true check. + +* Thu Jun 29 2017 Mark Wielaard 3.13.0-4 +- Add valgrind-3.13.0-arm-index-hardwire.patch (#1466017) +- Add valgrind-3.13.0-ucontext_t.patch +- Add valgrind-3.13.0-gdb-8-testfix.patch +- Add valgrind-3.13.0-disable-vgdb-child.patch + +* Fri Jun 23 2017 Mark Wielaard 3.13.0-3 +- Add valgrind-3.13.0-arm64-hwcap.patch (#1464211) + +* Sat Jun 17 2017 Mark Wielaard 3.13.0-2 +- Add valgrind-3.13.0-ppc64-check-no-vsx.patch +- Add valgrind-3.13.0-epoll_pwait.patch (#1462258) +- Add valgrind-3.13.0-ppc64-diag.patch + +* Thu Jun 15 2017 Mark Wielaard - 3.13.0-1 +- valgrind 3.13.0 final. +- Drop all upstreamed patches. + +* Tue Jun 6 2017 Mark Wielaard - 3.13.0-0.2.RC1 +- Add valgrind-3.13.0-arm-dcache.patch +- Add valgrind-3.13.0-g++-4.4.patch +- Add valgrind-3.13.0-s390x-GI-strcspn.patch +- Add valgrind-3.13.0-xtree-callgrind.patch + +* Fri Jun 2 2017 Mark Wielaard - 3.13.0-0.1.RC1 +- Update description as suggested by Ivo Raisr. +- Workaround gdb/python bug in testsuite (#1434601) +- Update to upstream 3.13.0-RC1. +- Drop all upstreamed patches. + +* Tue Mar 28 2017 Mark Wielaard - 3.12.0-8 +- Add valgrind-3.12.0-powerpc-register-pair.patch +- Add valgrind-3.12.0-ppc64-isa-3_00.patch + +* Sat Feb 18 2017 Mark Wielaard - 3.12.0-7 +- Add valgrind-3.12.0-aarch64-syscalls.patch + +* Sat Feb 18 2017 Mark Wielaard - 3.12.0-6 +- Add valgrind-3.12.0-arm64-ppc64-prlimit64.patch +- Add valgrind-3.12.0-arm64-hint.patch +- Add valgrind-3.12.0-clone-spawn.patch +- Add valgrind-3.12.0-quick-fatal-sigs.patch +- Add valgrind-3.12.0-exit_group.patch +- Add valgrind-3.12.0-deregister-stack.patch +- Add valgrind-3.12.0-x86-gdt-and-ss.patch +- Add valgrind-3.12.0-cd-dvd-ioctl.patch +- Add valgrind-3.12.0-tests-cxx11_abi_0.patch +- Add valgrind-3.12.0-helgrind-dl_allocate_tls-supp.patch +- Add valgrind-3.12.0-ppc-xxsel.patch + +* Fri Feb 17 2017 Mark Wielaard - 3.12.0-5 +- Add valgrind-3.12.0-ppc64-r2.patch (#1424367) + +* Sat Feb 11 2017 Fedora Release Engineering - 1:3.12.0-4 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_26_Mass_Rebuild + +* Sat Nov 12 2016 Mark Wielaard - 3.12.0-3 +- Add valgrind-3.12.0-nocwd-cleanup.patch (#1390282) + +* Fri Oct 21 2016 Orion Poplawski - 1:3.12.0-2 +- Rebuild for openmpi 2.0 + +* Fri Oct 21 2016 Mark Wielaard - 3.12.0-1 +- Update to valgrind 3.12.0 release. + +* Thu Oct 20 2016 Mark Wielaard - 3.12.0-0.4-RC2 +- Update to 3.12.0-RC1. Drop integrated patches. +- Add valgrind-3.12.0-skip-cond-var.patch + +* Fri Sep 30 2016 Mark Wielaard - 3.12.0-0.3-BETA1 +- Clear CFLAGS, CXXFLAGS and LDFLAGS during make check. + +* Thu Sep 29 2016 Mark Wielaard - 3.12.0-0.2-BETA1 +- Add valgrind-3.12-beta1-ppc64be.patch. +- Enable gdb_server tests again. + +* Tue Sep 20 2016 Mark Wielaard - 3.12.0-0.1-BETA1 +- Update to valgrind 3.12.0 pre-release. + - Drop upstreamed patches. + - Disable exp-tests in %%check. GDB crashes on gdb_server tests. + +* Fri Jul 22 2016 Mark Wielaard - 3.11.0-26 +- Only build valgrind-openmpi when not creating a software collection. +- No support for multilib on secondary arches when creating scl. +- Touch up empty .exp files. + +* Thu Jul 21 2016 Mark Wielaard - 3.11.0-24 +- Mandatory Perl build-requires added +- Add valgrind-3.11.0-shr.patch +- Add valgrind-3.11.0-pcmpxstrx-0x70-0x19.patch +- Update valgrind-3.11.0-wrapmalloc.patch +- Add valgrind-3.11.0-sighandler-stack.patch + +* Tue Jun 21 2016 Mark Wielaard - 3.11.0-23 +- Update valgrind-3.11.0-ppoll-mask.patch (#1344082) + +* Mon May 30 2016 Mark Wielaard - 3.11.0-22 +- Add valgrind-3.11.0-arm64-handle_at.patch +- Add valgrind-3.11.0-ppc64-syscalls.patch + +* Fri Apr 29 2016 Mark Wielaard - 3.11.0-21 +- Add valgrind-3.11.0-deduppoolalloc.patch +- Add valgrind-3.11.0-ppc-bcd-addsub.patch +- Add valgrind-3.11.0-ppc64-vgdb-vr-regs.patch + +* Fri Apr 15 2016 Mark Wielaard - 3.11.0-20 +- Update valgrind-3.11.0-cxx-freeres.patch (x86 final_tidyup fix) +- Add valgrind-3.11.0-s390x-risbgn.patch + +* Sun Apr 03 2016 Mark Wielaard - 3.11.0-19 +- Add valgrind-3.11.0-cxx-freeres.patch (#1312647) +- Add valgrind-3.11.0-ppc64-separate-socketcalls.patch +- Add valgrind-3.11.0-isZeroU.patch +- Replace valgrind-3.11.0-arm64-ldpsw.patch with upstream version +- Add valgrind-3.11.0-ppc64-128bit-mod-carry.patch +- Add valgrind-3.11.0-amd64-fcom.patch +- Add valgrind-3.11.0-z13s.patch +- Add valgrind-3.11.0-gdb-test-filters.patch + +* Mon Mar 14 2016 Mark Wielaard - 3.11.0-18 +- Update valgrind-3.11.0-libstdc++-supp.patch. +- Add valgrind-3.11.0-arm64-ldr-literal-test.patch. +- Add valgrind-3.11.0-arm64-ldpsw.patch + +* Thu Mar 10 2016 Mark Wielaard - 3.11.0-17 +- Update valgrind-3.11.0-arm64-more-syscalls.patch +- Add valgrind-3.11.0-libstdc++-supp.patch (#1312647) + +* Wed Mar 09 2016 Mark Wielaard - 3.11.0-16 +- Add valgrind-3.11.0-ppoll-mask.patch +- Add valgrind-3.11.0-arm64-more-syscalls.patch + +* Wed Feb 24 2016 Mark Wielaard - 3.11.0-15 +- Add valgrind-3.11.0-s390-separate-socketcalls.patch +- Add valgrind-3.11.0-amd64-ld-index.patch + +* Thu Feb 18 2016 Mark Wielaard - 3.11.0-14 +- Update valgrind-3.11.0-futex.patch (fix helgrind/drd regression). +- Update valgrind-3.11.0-x86_unwind.patch (include amd64 fix). + +* Wed Feb 17 2016 Mark Wielaard - 3.11.0-13 +- Remove valgrind-3.11.0-no-stv.patch (gcc6 has been fixed). +- Add valgrind-3.11.0-futex.patch +- Add valgrind-3.11.0-s390x-popcnt.patch + +* Fri Feb 05 2016 Fedora Release Engineering - 1:3.11.0-12 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_24_Mass_Rebuild + +* Sat Jan 30 2016 Mark Wielaard - 3.11.0-11 +- Add valgrind-3.11.0-no-stv.patch (GCC6 workaround). + +* Mon Jan 25 2016 Mark Wielaard - 3.11.0-10 +- Add valgrind-3.11.0-drd_std_thread.patch GCC6 build fix. + +* Fri Jan 22 2016 Mark Wielaard - 3.11.0-9 +- Fix valgrind-3.11.0-pthread_barrier.patch to apply with older patch. +- Fix multilib issue in config.h with HAVE_AS_AMD64_FXSAVE64. + +* Thu Jan 21 2016 Mark Wielaard - 3.11.0-8 +- Add valgrind-3.11.0-rlimit_data.patch +- Add valgrind-3.11.0-fclose.patch +- Add valgrind-3.11.0-pthread_spin_destroy.patch +- Add valgrind-3.11.0-socketcall-x86-linux.patch +- Don't strip debuginfo from vgpreload libaries. + Enable dwz for everything else again. +- Add valgrind-3.11.0-is_stmt.patch +- Add valgrind-3.11.0-x86_unwind.patch + +* Tue Jan 19 2016 Mark Wielaard - 3.11.0-7 +- Add valgrind-3.11.0-pthread_barrier.patch + +* Sat Jan 16 2016 Mark Wielaard - 3.11.0-6 +- Add valgrind-3.11.0-aspacemgr.patch (#1283774) + +* Sun Nov 15 2015 Mark Wielaard - 3.11.0-5 +- Add valgrind-3.11.0-wrapmalloc.patch + +* Mon Oct 12 2015 Mark Wielaard - 3.11.0-4 +- Fix parenthesis in valgrind-3.11.0-rexw-cvtps2pd.patch. +- Add valgrind-3.11.0-s390-hwcap.patch + +* Mon Oct 12 2015 Mark Wielaard - 3.11.0-3 +- Add valgrind-3.11.0-rexw-cvtps2pd.patch. + +* Thu Oct 01 2015 Mark Wielaard - 3.11.0-2 +- Add valgrind-3.11.0-no-rdrand.patch + +* Wed Sep 23 2015 Mark Wielaard - 3.11.0-1 +- Upgrade to valgrind 3.11.0 final +- Drop patches included upstream + - valgrind-3.11.0-ppc-dfp-guard.patch + - valgrind-3.11.0-ppc-ppr.patch + - valgrind-3.11.0-ppc-mbar.patch + - valgrind-3.11.0-glibc-futex-message.patch + - valgrind-3.11.0-arm64-libvex_test.patch + - valgrind-3.11.0-arm-warnings.patch + - valgrind-3.11.0-arm-no-cast-align.patch + - valgrind-3.11.0-ppc-vbit-test.patch +- Add arm64 syscall patches + - valgrind-3.11.0-arm64-xattr.patch + - valgrind-3.11.0-arm64-sigpending.patch + +* Sat Sep 19 2015 Mark Wielaard - 3.11.0-0.4.TEST1 +- Add valgrind-3.11.0-ppc-dfp-guard.patch +- Add valgrind-3.11.0-ppc-ppr.patch +- Add valgrind-3.11.0-ppc-mbar.patch + +* Fri Sep 18 2015 Mark Wielaard - 3.11.0-0.3.TEST1 +- Make sure some info about the system is in the build.log before check. +- Add valgrind-3.11.0-glibc-futex-message.patch +- Add valgrind-3.11.0-arm64-libvex_test.patch +- Add valgrind-3.11.0-arm-warnings.patch +- Add valgrind-3.11.0-arm-no-cast-align.patch +- Add valgrind-3.11.0-ppc-vbit-test.patch + +* Tue Sep 15 2015 Orion Poplawski - 1:3.11.0-0.2.TEST1 +- Rebuild for openmpi 1.10.0 + +* Thu Sep 10 2015 Mark Wielaard - 3.11.0-0.1.TEST1 +- Add BuildRequires perl(Getopt::Long) +- Upgrade to valgrind 3.11.0.TEST1 +- Remove upstreamed valgrind-3.10.1-gdb-file-warning.patch + +* Tue Aug 25 2015 Mark Wielaard - 3.10.1-22.svn20150825r15589 +- Drop valgrind-3.9.0-stat_h.patch. +- Add BuildRequires gcc-c++. +- Update to current valgrind svn (svn20150825r15589) +- Add valgrind-3.10.1-gdb-file-warning.patch + +* Mon Aug 17 2015 Mark Wielaard - 3.10.1-21.svn20150817r15561 +- Update to current valgrind svn. Drop patches now upstream. + +* Mon Aug 17 2015 Mark Wielaard - 3.10.1-20 +- Don't try to move around libmpiwrap when not building for openmpi (s390x) + +* Fri Aug 14 2015 Mark Wielaard - 3.10.1-19 +- Install libmpiwrap library under {_libdir}/openmpi/valgrind (#1238428) + +* Mon Aug 10 2015 Sandro Mani - 1:3.10.1-18 +- Rebuild for RPM MPI Requires Provides Change + +* Mon Aug 10 2015 Mark Wielaard - 3.10.1-17 +- Add setuid and setresgid to valgrind-3.10.1-aarch64-syscalls.patch. + +* Mon Aug 03 2015 Mark Wielaard - 3.10.1-16 +- Add valgrind-3.10.1-ppc64-hwcap2.patch + +* Wed Jul 08 2015 Mark Wielaard - 3.10.1-15 +- Update valgrind-3.10.1-s390x-fiebra.patch + +* Wed Jul 08 2015 Mark Wielaard - 3.10.1-14 +- Add valgrind-3.10.1-s390x-fiebra.patch + +* Tue Jul 07 2015 Mark Wielaard - 3.10.1-13 +- Add valgrind-3.10.1-di_notify_mmap.patch +- Add valgrind-3.10.1-memmove-ld_so-ppc64.patch + +* Fri Jun 19 2015 Mark Wielaard - 3.10.1-12 +- Add valgrind-3.10.1-kernel-4.0.patch. + +* Fri Jun 19 2015 Fedora Release Engineering - 1:3.10.1-11 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_23_Mass_Rebuild + +* Sun Jun 07 2015 Mark Wielaard - 3.10.1-10 +- Add valgrind-3.10.1-cfi-redzone.patch. + +* Wed Jun 03 2015 Mark Wielaard - 3.10.1-9 +- Add valgrind-3.10.1-memfd_create.patch. +- Add valgrind-3.10.1-syncfs.patch. +- Add valgrind-3.10.1-arm-process_vm_readv_writev.patch. +- Add valgrind-3.10.1-fno-ipa-icf.patch. +- Add valgrind-3.10.1-demangle-q.patch + +* Fri May 22 2015 Mark Wielaard - 3.10.1-8 +- Disable extended regtest on arm. The gdb tests hang for unknown reasons. + The reason is a glibc bug #1196181 which causes: + "GDB fails with Cannot parse expression `.L1055 4@r4'." + +* Wed Apr 22 2015 Mark Wielaard - 3.10.1-7 +- Add valgrind-3.10-1-ppc64-sigpending.patch +- Filter out -fstack-protector-strong and disable _hardened_build. + +* Wed Feb 18 2015 Mark Wielaard - 3.10.1-6 +- Add valgrind-3.10.1-send-recv-mmsg.patch +- Add mount and umount2 to valgrind-3.10.1-aarch64-syscalls.patch. +- Add valgrind-3.10.1-glibc-version-check.patch + +* Tue Feb 10 2015 Mark Wielaard - 3.10.1-5 +- Add accept4 to valgrind-3.10.1-aarch64-syscalls.patch. +- Add valgrind-3.10.1-ppc64-accept4.patch. + +* Sun Feb 08 2015 Mark Wielaard - 3.10.1-4 +- Add valgrind-3.10.1-aarch64-syscalls.patch. + +* Thu Feb 05 2015 Mark Wielaard - 3.10.1-3 +- Add valgrind-3.10-s390-spechelper.patch. + +* Tue Jan 13 2015 Mark Wielaard - 3.10.1-2 +- Add valgrind-3.10.1-mempcpy.patch. + +* Wed Nov 26 2014 Mark Wielaard - 3.10.1-1 +- Upgrade to 3.10.1 final. + +* Mon Nov 24 2014 Mark Wielaard - 3.10.1-0.1.TEST1 +- Upgrade to valgrind 3.10.1.TEST1 +- Remove patches that are now upstream: + - valgrind-3.10.0-old-ppc32-instr-magic.patch + - valgrind-3.10.0-aarch64-syscalls.patch + - valgrind-3.10.0-aarch64-dmb-sy.patch + - valgrind-3.10.0-aarch64-frint.patch + - valgrind-3.10.0-fcvtmu.patch + - valgrind-3.10.0-aarch64-fcvta.patch + +* Wed Nov 19 2014 Mark Wielaard - 3.10.0-6 +- Add getgroups/setgroups to valgrind-3.10.0-aarch64-syscalls.patch + +* Tue Nov 4 2014 Mark Wielaard - 3.10.0-5 +- Merge valgrind-3.10.0-aarch64-times.patch + and valgrind-3.10.0-aarch64-getsetsid.patch + into valgrind-3.10.0-aarch64-syscalls.patch + add fdatasync, msync, pread64, setreuid, setregid, + mknodat, fchdir, chroot, fchownat, fchmod and fchown. +- Add valgrind-3.10.0-aarch64-frint.patch +- Add valgrind-3.10.0-fcvtmu.patch +- Add valgrind-3.10.0-aarch64-fcvta.patch + +* Sat Oct 11 2014 Mark Wielaard - 3.10.0-4 +- Add valgrind-3.10.0-aarch64-times.patch +- Add valgrind-3.10.0-aarch64-getsetsid.patch +- Add valgrind-3.10.0-aarch64-dmb-sy.patch + +* Mon Sep 15 2014 Mark Wielaard - 3.10.0-3 +- Add valgrind-3.10.0-old-ppc32-instr-magic.patch. + +* Fri Sep 12 2014 Mark Wielaard - 3.10.0-2 +- Fix ppc32 multilib handling on ppc64[be]. +- Drop ppc64 secondary for ppc32 primary support. +- Except for armv7hl we don't support any other arm[32] arch. + +* Thu Sep 11 2014 Mark Wielaard - 3.10.0-1 +- Update to 3.10.0 final. +- Remove valgrind-3.10-configure-glibc-2.20.patch fixed upstream. + +* Mon Sep 8 2014 Mark Wielaard - 3.10.0-0.2.BETA2 +- Update to 3.10.0.BETA2. +- Don't run dwz or generate minisymtab. +- Remove valgrind-3.9.0-s390x-ld-supp.patch fixed upstream. +- Add valgrind-3.10-configure-glibc-2.20.patch. + +* Tue Sep 2 2014 Mark Wielaard - 3.10.0-0.1.BETA1 +- Update to official upstream 3.10.0 BETA1. + - Enables inlined frames in stacktraces. + +* Fri Aug 29 2014 Mark Wielaard - 3.9.0-26.svn20140829r14384 +- Update to upstream svn r14384 +- Enable gdb_server tests again for arm and aarch64 + +* Wed Aug 27 2014 Mark Wielaard - 3.9.0-25.svn20140827r14370 +- Update to upstream svn r14370 +- Remove ppc testfile copying (no longer patched in) + +* Mon Aug 18 2014 Mark Wielaard - 3.9.0-24.svn20140818r14303 +- Update to upstream svn r14303 +- Move fake libgcc into shared to not break post-regtest-checks. +- autogen.sh execution no longer needed in %%build. + +* Mon Aug 18 2014 Fedora Release Engineering - 1:3.9.0-23.svn20140809r14250 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_21_22_Mass_Rebuild + +* Sat Aug 9 2014 Mark Wielaard 3.9.0-22.svn20140809r14250 +- Update to upstream svn r14250 + - ppc64le support got integrated upstream. Remove patches: + valgrind-3.9.0-ppc64le-initial.patch + valgrind-3.9.0-ppc64le-functional.patch + valgrind-3.9.0-ppc64le-test.patch + valgrind-3.9.0-ppc64le-extra.patch + +* Sat Jul 19 2014 Mark Wielaard 3.9.0-21.svn20140718r14176 +- Disable full regtest on arm (gdb integration tests sometimes hang). + +* Fri Jul 18 2014 Mark Wielaard 3.9.0-20.svn20140718r14176 +- Update to upstream svn r14176 + Remove valgrind-3.9.0-arm64-user_regs.patch +- Add ppc64le support + valgrind-3.9.0-ppc64le-initial.patch + valgrind-3.9.0-ppc64le-functional.patch + valgrind-3.9.0-ppc64le-test.patch + valgrind-3.9.0-ppc64le-extra.patch + +* Tue Jul 15 2014 Mark Wielaard 3.9.0-19.svn20140715r14165 +- Add valgrind-3.9.0-arm64-user_regs.patch +- Disable full regtest on aarch64 (gdb integration tests sometimes hang). +- Enable openmpi support on aarch64. + +* Tue Jul 15 2014 Mark Wielaard 3.9.0-18.svn20140715r14165 +- Update to upstream svn r14165. +- Remove valgrind-3.9.0-ppc64-ifunc.patch. +- Remove valgrind-3.9.0-aarch64-glibc-2.19.90-gcc-4.9.patch +- Remove valgrind-3.9.0-format-security.patch +- Remove valgrind-3.9.0-msghdr.patch + +* Fri Jul 4 2014 Mark Wielaard 3.9.0-17.svn20140513r13961 +- Remove ppc multilib support (#1116110) +- Add valgrind-3.9.0-ppc64-ifunc.patch + +* Sun Jun 08 2014 Fedora Release Engineering - 1:3.9.0-16.svn20140513r13961 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_21_Mass_Rebuild + +* Mon May 19 2014 Mark Wielaard +- Don't cleanup fake 32-bit libgcc created in %%build. + make regtest might depend on it to build -m32 binaries. + +* Fri May 16 2014 Mark Wielaard 3.9.0-15.svn20140513r13961 +- Add SHL_d_d_#imm to valgrind-3.9.0-aarch64-glibc-2.19.90-gcc-4.9.patch + +* Thu May 15 2014 Mark Wielaard 3.9.0-14.svn20140513r13961 +- Add valgrind-3.9.0-aarch64-glibc-2.19.90-gcc-4.9.patch + +* Tue May 13 2014 Mark Wielaard 3.9.0-13.svn20140513r13961 +- Update to upstream svn r13961. +- Remove valgrind-3.9.0-mpx.patch integrated upstream now. +- Add valgrind-3.9.0-msghdr.patch +- Add valgrind-3.9.0-format-security.patch + +* Thu May 8 2014 Mark Wielaard 3.9.0-12.svn20140319r13879 +- Add valgrind-3.9.0-mpx.patch (#1087933) + +* Wed Mar 19 2014 Mark Wielaard - 3.9.0-11.svn20140319r13879 +- Update to upstream svn r13879. arm64 make check now builds. + +* Tue Mar 18 2014 Mark Wielaard - 3.9.0-10.svn20140318r13876 +- Make sure basic binary (/bin/true) runs under valgrind. + And fail the whole build if not. The regtests are not zero-fail. +- Update to upstream svn r13876. +- Introduce build_openmpi and build_multilib in spec file. + +* Tue Mar 11 2014 Mark Wielaard - 3.9.0-9.svn20140311r13869 +- Enable aarch64 based on current upstream svn. Removed upstreamed patches. + Thanks to Marcin Juszkiewicz + +* Mon Mar 10 2014 Mark Wielaard - 3.9.0-8 +- Add valgrind-3.9.0-ppc64-priority.patch + +* Mon Feb 24 2014 Mark Wielaard +- Add upstream fixes to valgrind-3.9.0-timer_create.patch + +* Fri Feb 21 2014 Mark Wielaard - 3.9.0-7 +- Add valgrind-3.9.0-glibc-2.19.patch + +* Fri Feb 21 2014 Mark Wielaard - 3.9.0-6 +- Add valgrind-3.9.0-s390-dup3.patch +- Add valgrind-3.9.0-timer_create.patch + +* Thu Dec 12 2013 Mark Wielaard - 3.9.0-5 +- Add valgrind-3.9.0-manpage-memcheck-options.patch. +- Add valgrind-3.9.0-s390-fpr-pair.patch. + +* Thu Nov 28 2013 Mark Wielaard - 3.9.0-4 +- Add valgrind-3.9.0-xabort.patch. + +* Fri Nov 22 2013 Mark Wielaard - 3.9.0-3 +- Add valgrind-3.9.0-anon-typedef.patch. +- Add valgrind-3.9.0-s390x-ld-supp.patch + +* Wed Nov 20 2013 Mark Wielaard - 3.9.0-2 +- Add valgrind-3.9.0-dwz-alt-buildid.patch. +- Add valgrind-3.9.0-s390-risbg.patch. + +* Fri Nov 1 2013 Mark Wielaard - 3.9.0-1 +- Upgrade to valgrind 3.9.0 final. +- Remove support for really ancient GCCs (valgrind-3.9.0-config_h.patch). +- Add valgrind-3.9.0-amd64_gen_insn_test.patch. +- Remove and cleanup fake 32-bit libgcc package. + +* Mon Oct 28 2013 Mark Wielaard - 3.9.0-0.1.TEST1 +- Upgrade to valgrind 3.9.0.TEST1 +- Remove patches that are now upstream: + - valgrind-3.8.1-abbrev-parsing.patch + - valgrind-3.8.1-af-bluetooth.patch + - valgrind-3.8.1-aspacemgr_VG_N_SEGs.patch + - valgrind-3.8.1-avx2-bmi-fma.patch.gz + - valgrind-3.8.1-avx2-prereq.patch + - valgrind-3.8.1-bmi-conf-check.patch + - valgrind-3.8.1-capget.patch + - valgrind-3.8.1-cfi_dw_ops.patch + - valgrind-3.8.1-dwarf-anon-enum.patch + - valgrind-3.8.1-filter_gdb.patch + - valgrind-3.8.1-find-buildid.patch + - valgrind-3.8.1-gdbserver_exit.patch + - valgrind-3.8.1-gdbserver_tests-syscall-template-source.patch + - valgrind-3.8.1-glibc-2.17-18.patch + - valgrind-3.8.1-index-supp.patch + - valgrind-3.8.1-initial-power-isa-207.patch + - valgrind-3.8.1-manpages.patch + - valgrind-3.8.1-memcheck-mc_translate-Iop_8HLto16.patch + - valgrind-3.8.1-mmxext.patch + - valgrind-3.8.1-movntdqa.patch + - valgrind-3.8.1-new-manpages.patch + - valgrind-3.8.1-openat.patch + - valgrind-3.8.1-overlap_memcpy_filter.patch + - valgrind-3.8.1-pie.patch + - valgrind-3.8.1-pkg-config.patch + - valgrind-3.8.1-power-isa-205-deprecation.patch + - valgrind-3.8.1-ppc-32-mode-64-bit-instr.patch + - valgrind-3.8.1-ppc-setxattr.patch + - valgrind-3.8.1-proc-auxv.patch + - valgrind-3.8.1-ptrace-include-configure.patch + - valgrind-3.8.1-ptrace-setgetregset.patch + - valgrind-3.8.1-ptrace-thread-area.patch + - valgrind-3.8.1-regtest-fixlets.patch + - valgrind-3.8.1-s390-STFLE.patch + - valgrind-3.8.1-s390_tsearch_supp.patch + - valgrind-3.8.1-sendmsg-flags.patch + - valgrind-3.8.1-sigill_diag.patch + - valgrind-3.8.1-static-variables.patch + - valgrind-3.8.1-stpncpy.patch + - valgrind-3.8.1-text-segment.patch + - valgrind-3.8.1-wcs.patch + - valgrind-3.8.1-x86_amd64_features-avx.patch + - valgrind-3.8.1-xaddb.patch + - valgrind-3.8.1-zero-size-sections.patch +- Remove special case valgrind-3.8.1-enable-armv5.patch. +- Remove valgrind-3.8.1-x86-backtrace.patch, rely on new upstream fp/cfi + try-cache mechanism. + +* Mon Oct 14 2013 Mark Wielaard - 3.8.1-31 +- Fix multilib issue with HAVE_PTRACE_GETREGS in config.h. + +* Thu Sep 26 2013 Mark Wielaard - 3.8.1-30 +- Add valgrind-3.8.1-index-supp.patch (#1011713) + +* Wed Sep 25 2013 Mark Wielaard - 3.8.1-29 +- Filter out -mcpu= so tests are compiled with the right flags. (#996927). + +* Mon Sep 23 2013 Mark Wielaard - 3.8.1-28 +- Implement SSE4 MOVNTDQA insn (valgrind-3.8.1-movntdqa.patch) +- Don't BuildRequire /bin/ps, just BuildRequire procps + (procps-ng provides procps). + +* Thu Sep 05 2013 Mark Wielaard - 3.8.1-27 +- Fix power_ISA2_05 testcase (valgrind-3.8.1-power-isa-205-deprecation.patch) +- Fix ppc32 make check build (valgrind-3.8.1-initial-power-isa-207.patch) +- Add valgrind-3.8.1-mmxext.patch + +* Wed Aug 21 2013 Mark Wielaard - 3.8.1-26 +- Allow building against glibc 2.18. (#999169) + +* Thu Aug 15 2013 Mark Wielaard - 3.8.1-25 +- Add valgrind-3.8.1-s390-STFLE.patch + s390 message-security assist (MSA) instruction extension not implemented. + +* Wed Aug 14 2013 Mark Wielaard - 3.8.1-24 +- Add valgrind-3.8.1-power-isa-205-deprecation.patch + Deprecation of some ISA 2.05 POWER6 instructions. +- Fixup auto-foo generation of new manpage doc patch. + +* Wed Aug 14 2013 Mark Wielaard - 3.8.1-23 +- tests/check_isa-2_07_cap should be executable. + +* Tue Aug 13 2013 Mark Wielaard - 3.8.1-22 +- Add valgrind-3.8.1-initial-power-isa-207.patch + Initial ISA 2.07 support for POWER8-tuned libc. + +* Thu Aug 08 2013 Mark Wielaard - 3.8.1-21 +- Don't depend on docdir location and version in openmpi subpackage + description (#993938). +- Enable openmpi subpackage also on arm. + +* Thu Aug 08 2013 Mark Wielaard - 3.8.1-20 +- Add valgrind-3.8.1-ptrace-include-configure.patch (#992847) + +* Sun Aug 04 2013 Fedora Release Engineering - 1:3.8.1-19 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_20_Mass_Rebuild + +* Thu Jul 18 2013 Petr Pisar - 1:3.8.1-18 +- Perl 5.18 rebuild + +* Mon Jul 08 2013 Mark Wielaard - 3.8.1-17 +- Add valgrind-3.8.1-dwarf-anon-enum.patch +- Cleanup valgrind-3.8.1-sigill_diag.patch .orig file changes (#949687). +- Add valgrind-3.8.1-ppc-setxattr.patch +- Add valgrind-3.8.1-new-manpages.patch +- Add valgrind-3.8.1-ptrace-thread-area.patch +- Add valgrind-3.8.1-af-bluetooth.patch + +* Tue May 28 2013 Michael Schwendt - 1:3.8.1-16 +- Provide virtual -static package in -devel subpackage (#609624). + +* Thu Apr 25 2013 Mark Wielaard 3.8.1-15 +- Add valgrind-3.8.1-zero-size-sections.patch. Resolves issues with zero + sized .eh_frame sections on ppc64. + +* Thu Apr 18 2013 Mark Wielaard 3.8.1-14 +- fixup selinux file context when doing a scl build. +- Enable regtest suite on ARM. +- valgrind-3.8.1-abbrev-parsing.patch, drop workaround, enable real fix. +- Fix -Ttext-segment configure check. Enables s390x again. +- BuildRequire ps for testsuite. + +* Tue Apr 02 2013 Mark Wielaard 3.8.1-13 +- Fix quoting in valgrind valgrind-3.8.1-enable-armv5.patch and + remove arm configure hunk from valgrind-3.8.1-text-segment.patch #947440 +- Replace valgrind-3.8.1-text-segment.patch with upstream variant. +- Add valgrind-3.8.1-regtest-fixlets.patch. + +* Wed Mar 20 2013 Mark Wielaard 3.8.1-12 +- Add valgrind-3.8.1-text-segment.patch +- Don't undefine _missing_build_ids_terminate_build. + +* Tue Mar 12 2013 Mark Wielaard 3.8.1-11 +- Add valgrind-3.8.1-manpages.patch + +* Fri Mar 01 2013 Mark Wielaard 3.8.1-10 +- Don't disable -debuginfo package generation, but do undefine + _missing_build_ids_terminate_build. + +* Thu Feb 28 2013 Mark Wielaard 3.8.1-9 +- Replace valgrind-3.8.1-sendmsg-flags.patch with upstream version. + +* Tue Feb 19 2013 Mark Wielaard 3.8.1-8 +- Add valgrind-3.8.1-sendmsg-flags.patch +- Add valgrind-3.8.1-ptrace-setgetregset.patch +- Add valgrind-3.8.1-static-variables.patch + +* Thu Feb 07 2013 Jon Ciesla 1:3.8.1-7 +- Merge review fixes, BZ 226522. + +* Wed Jan 16 2013 Mark Wielaard 3.8.1-6 +- Allow building against glibc-2.17. + +* Sun Nov 4 2012 Mark Wielaard 3.8.1-5 +- Add valgrind-3.8.1-stpncpy.patch (KDE#309427) +- Add valgrind-3.8.1-ppc-32-mode-64-bit-instr.patch (#810992, KDE#308573) +- Add valgrind-3.8.1-sigill_diag.patch (#810992, KDE#309425) + +* Tue Oct 16 2012 Mark Wielaard 3.8.1-4 +- Add valgrind-3.8.1-xaddb.patch (#866793, KDE#307106) + +* Mon Oct 15 2012 Mark Wielaard 3.8.1-3 +- Add valgrind-3.8.1-x86_amd64_features-avx.patch (KDE#307285) +- Add valgrind-3.8.1-gdbserver_tests-syscall-template-source.patch (KDE#307155) +- Add valgrind-3.8.1-overlap_memcpy_filter.patch (KDE#307290) +- Add valgrind-3.8.1-pkg-config.patch (#827219, KDE#307729) +- Add valgrind-3.8.1-proc-auxv.patch (KDE#253519) +- Add valgrind-3.8.1-wcs.patch (#755242, KDE#307828) +- Add valgrind-3.8.1-filter_gdb.patch (KDE#308321) +- Add valgrind-3.8.1-gdbserver_exit.patch (#862795, KDE#308341) +- Add valgrind-3.8.1-aspacemgr_VG_N_SEGs.patch (#730303, KDE#164485) +- Add valgrind-3.8.1-s390_tsearch_supp.patch (#816244, KDE#308427) + +* Fri Sep 21 2012 Mark Wielaard 3.8.1-2 +- Add valgrind-3.8.1-gdbserver_tests-mcinvoke-ppc64.patch +- Replace valgrind-3.8.1-cfi_dw_ops.patch with version as committed upstream. +- Remove erroneous printf change from valgrind-3.8.1-abbrev-parsing.patch. +- Add scalar testcase change to valgrind-3.8.1-capget.patch. + +* Thu Sep 20 2012 Mark Wielaard 3.8.1-1 +- Add partial backport of upstream revision 12884 + valgrind-3.8.0-memcheck-mc_translate-Iop_8HLto16.patch + without it AVX2 VPBROADCASTB insn is broken under memcheck. +- Add valgrind-3.8.0-cfi_dw_ops.patch (KDE#307038) + DWARF2 CFI reader: unhandled DW_OP_ opcode 0x8 (DW_OP_const1u and friends) +- Add valgrind-3.8.0-avx2-prereq.patch. +- Remove accidentially included diffs for gdbserver_tests and helgrind/tests + Makefile.in from valgrind-3.8.0-avx2-bmi-fma.patch.gz +- Remove valgrind-3.8.0-tests.patch tests no longer hang. +- Added SCL macros to support building as part of a Software Collection. +- Upgrade to valgrind 3.8.1. + +* Wed Sep 12 2012 Mark Wielaard 3.8.0-8 +- Add configure fixup valgrind-3.8.0-bmi-conf-check.patch + +* Wed Sep 12 2012 Mark Wielaard 3.8.0-7 +- Add valgrind-3.8.0-avx2-bmi-fma.patch (KDE#305728) + +* Tue Sep 11 2012 Mark Wielaard 3.8.0-6 +- Add valgrind-3.8.0-lzcnt-tzcnt-bugfix.patch (KDE#295808) +- Add valgrind-3.8.0-avx-alignment-check.patch (KDE#305926) + +* Mon Aug 27 2012 Mark Wielaard 3.8.0-5 +- Add valgrind-3.8.0-abbrev-parsing.patch for #849783 (KDE#305513). + +* Sun Aug 19 2012 Mark Wielaard 3.8.0-4 +- Add valgrind-3.8.0-find-buildid.patch workaround bug #849435 (KDE#305431). + +* Wed Aug 15 2012 Jakub Jelinek 3.8.0-3 +- fix up last change + +* Wed Aug 15 2012 Jakub Jelinek 3.8.0-2 +- tweak up to allow simultaneous installation + of valgrind-devel.{i686,x86_64} (#848146) + +* Fri Aug 10 2012 Jakub Jelinek 3.8.0-1 +- update to 3.8.0 release +- from CFLAGS/CXXFLAGS filter just fortification flags, not arch + specific flags +- on i?86 prefer to use CFI over %%ebp unwinding, as GCC 4.6+ + defaults to -fomit-frame-pointer + +* Tue Aug 07 2012 Mark Wielaard 3.8.0-0.1.TEST1.svn12858 +- Update to 3.8.0-TEST1 +- Clear CFLAGS CXXFLAGS LDFLAGS. +- Fix \ line continuation in configure line. + +* Fri Aug 03 2012 Mark Wielaard 3.7.0-7 +- Fixup shadowing warnings valgrind-3.7.0-dwz.patch +- Add valgrind-3.7.0-ref_addr.patch (#842659, KDE#298864) + +* Wed Jul 25 2012 Mark Wielaard 3.7.0-6 +- handle dwz DWARF compressor output (#842659, KDE#302901) +- allow glibc 2.16. + +* Sun Jul 22 2012 Fedora Release Engineering - 1:3.7.0-5 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_18_Mass_Rebuild + +* Mon May 7 2012 Jakub Jelinek 3.7.0-4 +- adjust suppressions so that it works even with ld-2.15.so (#806854) +- handle DW_TAG_unspecified_type and DW_TAG_rvalue_reference_type + (#810284, KDE#278313) +- handle .debug_types sections (#810286, KDE#284124) + +* Sun Mar 4 2012 Peter Robinson 3.7.0-2 +- Fix building on ARM platform + +* Fri Jan 27 2012 Jakub Jelinek 3.7.0-1 +- update to 3.7.0 (#769213, #782910, #772343) +- handle some further SCSI ioctls (#783936) +- handle fcntl F_SETOWN_EX and F_GETOWN_EX (#770746) + +* Wed Aug 17 2011 Adam Jackson 3.6.1-6 +- rebuild for rpm 4.9.1 trailing / bug + +* Thu Jul 21 2011 Jakub Jelinek 3.6.1-5 +- handle PLT unwind info (#723790, KDE#277045) + +* Mon Jun 13 2011 Jakub Jelinek 3.6.1-4 +- fix memcpy/memmove redirection on x86_64 (#705790) + +* Wed Jun 8 2011 Jakub Jelinek 3.6.1-3 +- fix testing against glibc 2.14 + +* Wed Jun 8 2011 Jakub Jelinek 3.6.1-2 +- fix build on ppc64 (#711608) +- don't fail if s390x support patch hasn't been applied, + move testing into %%check (#708522) +- rebuilt against glibc 2.14 + +* Wed Feb 23 2011 Jakub Jelinek 3.6.1-1 +- update to 3.6.1 + +* Mon Feb 07 2011 Fedora Release Engineering - 1:3.6.0-3 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_15_Mass_Rebuild + +* Fri Jan 28 2011 Jakub Jelinek 3.6.0-2 +- rebuilt against glibc 2.13 (#673046) +- hook in pwrite64 syscall on ppc64 (#672858) +- fix PIE handling on ppc/ppc64 (#665289) + +* Fri Nov 12 2010 Jakub Jelinek 3.6.0-1 +- update to 3.6.0 +- add s390x support (#632354) +- provide a replacement for str{,n}casecmp{,_l} (#626470) + +* Tue May 18 2010 Jakub Jelinek 3.5.0-18 +- rebuilt against glibc 2.12 + +* Mon Apr 12 2010 Jakub Jelinek 3.5.0-16 +- change pub_tool_basics.h not to include config.h (#579283) +- add valgrind-openmpi package for OpenMPI support (#565541) +- allow NULL second argument to capget (#450976) + +* Wed Apr 7 2010 Jakub Jelinek 3.5.0-15 +- handle i686 nopw insns with more than one data16 prefix (#574889) +- DWARF4 support +- handle getcpu and splice syscalls + +* Wed Jan 20 2010 Jakub Jelinek 3.5.0-14 +- fix build against latest glibc headers + +* Wed Jan 20 2010 Jakub Jelinek 3.5.0-13 +- DW_OP_mod is unsigned modulus instead of signed +- fix up valgrind.pc (#551277) + +* Mon Dec 21 2009 Jakub Jelinek 3.5.0-12 +- don't require offset field to be set in adjtimex's + ADJ_OFFSET_SS_READ mode (#545866) + +* Wed Dec 2 2009 Jakub Jelinek 3.5.0-10 +- add handling of a bunch of recent syscalls and fix some + other syscall wrappers (Dodji Seketeli) +- handle prelink created split of .bss into .dynbss and .bss + and similarly for .sbss and .sdynbss (#539874) + +* Wed Nov 4 2009 Jakub Jelinek 3.5.0-9 +- rebuilt against glibc 2.11 +- use upstream version of the ifunc support + +* Wed Oct 28 2009 Jakub Jelinek 3.5.0-8 +- add preadv/pwritev syscall support + +* Tue Oct 27 2009 Jakub Jelinek 3.5.0-7 +- add perf_counter_open syscall support (#531271) +- add handling of some sbb/adc insn forms on x86_64 (KDE#211410) + +* Fri Oct 23 2009 Jakub Jelinek 3.5.0-6 +- ppc and ppc64 fixes + +* Thu Oct 22 2009 Jakub Jelinek 3.5.0-5 +- add emulation of 0x67 prefixed loop* insns on x86_64 (#530165) + +* Wed Oct 21 2009 Jakub Jelinek 3.5.0-4 +- handle reading of .debug_frame in addition to .eh_frame +- ignore unknown DWARF3 expressions in evaluate_trivial_GX +- suppress helgrind race errors in helgrind's own mythread_wrapper +- fix compilation of x86 tests on x86_64 and ppc tests + +* Wed Oct 14 2009 Jakub Jelinek 3.5.0-3 +- handle many more DW_OP_* ops that GCC now uses +- handle the more compact form of DW_AT_data_member_location +- don't strip .debug_loc etc. from valgrind binaries + +* Mon Oct 12 2009 Jakub Jelinek 3.5.0-2 +- add STT_GNU_IFUNC support (Dodji Seketeli, #518247) +- wrap inotify_init1 syscall (Dodji Seketeli, #527198) +- fix mmap/mprotect handling in memcheck (KDE#210268) + +* Fri Aug 21 2009 Jakub Jelinek 3.5.0-1 +- update to 3.5.0 + +* Tue Jul 28 2009 Jakub Jelinek 3.4.1-7 +- handle futex ops newly added during last 4 years (#512121) + +* Sun Jul 26 2009 Fedora Release Engineering 3.4.1-6 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_12_Mass_Rebuild + +* Mon Jul 13 2009 Jakub Jelinek 3.4.1-5 +- add support for DW_CFA_{remember,restore}_state + +* Mon Jul 13 2009 Jakub Jelinek 3.4.1-4 +- handle version 3 .debug_frame, .eh_frame, .debug_info and + .debug_line (#509197) + +* Mon May 11 2009 Jakub Jelinek 3.4.1-3 +- rebuilt against glibc 2.10.1 + +* Wed Apr 22 2009 Jakub Jelinek 3.4.1-2 +- redirect x86_64 ld.so strlen early (#495645) + +* Mon Mar 9 2009 Jakub Jelinek 3.4.1-1 +- update to 3.4.1 + +* Mon Feb 9 2009 Jakub Jelinek 3.4.0-3 +- update to 3.4.0 + +* Wed Apr 16 2008 Jakub Jelinek 3.3.0-3 +- add suppressions for glibc 2.8 +- add a bunch of syscall wrappers (#441709) + +* Mon Mar 3 2008 Jakub Jelinek 3.3.0-2 +- add _dl_start suppression for ppc/ppc64 + +* Mon Mar 3 2008 Jakub Jelinek 3.3.0-1 +- update to 3.3.0 +- split off devel bits into valgrind-devel subpackage + +* Thu Oct 18 2007 Jakub Jelinek 3.2.3-7 +- add suppressions for glibc >= 2.7 + +* Fri Aug 31 2007 Jakub Jelinek 3.2.3-6 +- handle new x86_64 nops (#256801, KDE#148447) +- add support for private futexes (KDE#146781) +- update License tag + +* Fri Aug 3 2007 Jakub Jelinek 3.2.3-5 +- add ppc64-linux symlink in valgrind ppc.rpm, so that when + rpm prefers 32-bit binaries over 64-bit ones 32-bit + /usr/bin/valgrind can find 64-bit valgrind helper binaries + (#249773) +- power5+ and power6 support (#240762) + +* Thu Jun 28 2007 Jakub Jelinek 3.2.3-4 +- pass GDB=%%{_prefix}/gdb to configure to fix default + --db-command (#220840) + +* Wed Jun 27 2007 Jakub Jelinek 3.2.3-3 +- add suppressions for glibc >= 2.6 +- avoid valgrind internal error if io_destroy syscall is + passed a bogus argument + +* Tue Feb 13 2007 Jakub Jelinek 3.2.3-2 +- fix valgrind.pc again + +* Tue Feb 13 2007 Jakub Jelinek 3.2.3-1 +- update to 3.2.3 + +* Wed Nov 8 2006 Jakub Jelinek 3.2.1-7 +- some cachegrind improvements (Ulrich Drepper) + +* Mon Nov 6 2006 Jakub Jelinek 3.2.1-6 +- fix valgrind.pc (#213149) +- handle Intel Core2 cache sizes in cachegrind (Ulrich Drepper) + +* Wed Oct 25 2006 Jakub Jelinek 3.2.1-5 +- fix valgrind on ppc/ppc64 where PAGESIZE is 64K (#211598) + +* Sun Oct 1 2006 Jakub Jelinek 3.2.1-4 +- adjust for glibc-2.5 + +* Wed Sep 27 2006 Jakub Jelinek 3.2.1-3 +- another DW_CFA_set_loc handling fix + +* Tue Sep 26 2006 Jakub Jelinek 3.2.1-2 +- fix openat handling (#208097) +- fix DW_CFA_set_loc handling + +* Tue Sep 19 2006 Jakub Jelinek 3.2.1-1 +- update to 3.2.1 bugfix release + - SSE3 emulation fixes, reduce memcheck false positive rate, + 4 dozens of bugfixes + +* Mon Aug 21 2006 Jakub Jelinek 3.2.0-5 +- handle the new i686/x86_64 nops (#203273) + +* Fri Jul 28 2006 Jeremy Katz - 1:3.2.0-4 +- rebuild to bring ppc back + +* Wed Jul 12 2006 Jesse Keating - 1:3.2.0-3.1 +- rebuild + +* Fri Jun 16 2006 Jakub Jelinek 3.2.0-3 +- handle [sg]et_robust_list syscall on ppc{32,64} + +* Fri Jun 16 2006 Jakub Jelinek 3.2.0-2 +- fix ppc64 symlink to 32-bit valgrind libdir +- handle a few extra ppc64 syscalls + +* Thu Jun 15 2006 Jakub Jelinek 3.2.0-1 +- update to 3.2.0 + - ppc64 support + +* Fri May 26 2006 Jakub Jelinek 3.1.1-3 +- handle [sg]et_robust_list syscalls on i?86/x86_64 +- handle *at syscalls on ppc +- ensure on x86_64 both 32-bit and 64-bit glibc{,-devel} are + installed in the buildroot (#191820) + +* Wed Apr 12 2006 Jakub Jelinek 3.1.1-2 +- handle many syscalls that were unhandled before, especially on ppc + +* Mon Apr 3 2006 Jakub Jelinek 3.1.1-1 +- upgrade to 3.1.1 + - many bugfixes + +* Mon Mar 13 2006 Jakub Jelinek 3.1.0-2 +- add support for DW_CFA_val_offset{,_sf}, DW_CFA_def_cfa_sf + and skip over DW_CFA_val_expression quietly +- adjust libc/ld.so filenames in glibc-2.4.supp for glibc 2.4 + release + +* Mon Jan 9 2006 Jakub Jelinek 3.1.0-1 +- upgrade to 3.1.0 (#174582) + - many bugfixes, ppc32 support + +* Thu Oct 13 2005 Jakub Jelinek 3.0.1-2 +- remove Obsoletes for valgrind-callgrind, as it has been + ported to valgrind 3.0.x already + +* Sun Sep 11 2005 Jakub Jelinek 3.0.1-1 +- upgrade to 3.0.1 + - many bugfixes +- handle xattr syscalls on x86-64 (Ulrich Drepper) + +* Fri Aug 12 2005 Jakub Jelinek 3.0.0-3 +- fix amd64 handling of cwtd instruction +- fix amd64 handling of e.g. sarb $0x4,val(%%rip) +- speedup amd64 insn decoding + +* Fri Aug 12 2005 Jakub Jelinek 3.0.0-2 +- lower x86_64 stage2 base from 112TB down to 450GB, so that + valgrind works even on 2.4.x kernels. Still way better than + 1.75GB that stock valgrind allows + +* Fri Aug 12 2005 Jakub Jelinek 3.0.0-1 +- upgrade to 3.0.0 + - x86_64 support +- temporarily obsolete valgrind-callgrind, as it has not been + ported yet + +* Tue Jul 12 2005 Jakub Jelinek 2.4.0-3 +- build some insn tests with -mmmx, -msse or -msse2 (#161572) +- handle glibc-2.3.90 the same way as 2.3.[0-5] + +* Wed Mar 30 2005 Jakub Jelinek 2.4.0-2 +- resurrect the non-upstreamed part of valgrind_h patch +- remove 2.1.2-4G patch, seems to be upstreamed +- resurrect passing -fno-builtin in memcheck tests + +* Sun Mar 27 2005 Colin Walters 2.4.0-1 +- New upstream version +- Update valgrind-2.2.0-regtest.patch to 2.4.0; required minor + massaging +- Disable valgrind-2.1.2-4G.patch for now; Not going to touch this, + and Fedora does not ship 4G kernel by default anymore +- Remove upstreamed valgrind-2.2.0.ioctls.patch +- Remove obsolete valgrind-2.2.0-warnings.patch; Code is no longer + present +- Remove upstreamed valgrind-2.2.0-valgrind_h.patch +- Remove obsolete valgrind-2.2.0-unnest.patch and + valgrind-2.0.0-pthread-stacksize.patch; valgrind no longer + includes its own pthread library + +* Thu Mar 17 2005 Jakub Jelinek 2.2.0-10 +- rebuilt with GCC 4 + +* Tue Feb 8 2005 Jakub Jelinek 2.2.0-8 +- avoid unnecessary use of nested functions for pthread_once + cleanup + +* Mon Dec 6 2004 Jakub Jelinek 2.2.0-7 +- update URL (#141873) + +* Tue Nov 16 2004 Jakub Jelinek 2.2.0-6 +- act as if NVALGRIND is defined when using + in non-m32/i386 programs (#138923) +- remove weak from VALGRIND_PRINTF*, make it static and + add unused attribute + +* Mon Nov 8 2004 Jakub Jelinek 2.2.0-4 +- fix a printout and possible problem with local variable + usage around setjmp (#138254) + +* Tue Oct 5 2004 Jakub Jelinek 2.2.0-3 +- remove workaround for buggy old makes (#134563) + +* Fri Oct 1 2004 Jakub Jelinek 2.2.0-2 +- handle some more ioctls (Peter Jones, #131967) + +* Thu Sep 2 2004 Jakub Jelinek 2.2.0-1 +- update to 2.2.0 + +* Thu Jul 22 2004 Jakub Jelinek 2.1.2-3 +- fix packaging of documentation + +* Tue Jul 20 2004 Jakub Jelinek 2.1.2-2 +- allow tracing of 32-bit binaries on x86-64 + +* Tue Jul 20 2004 Jakub Jelinek 2.1.2-1 +- update to 2.1.2 +- run make regtest as part of package build +- use glibc-2.3 suppressions instead of glibc-2.2 suppressions + +* Thu Apr 29 2004 Colin Walters 2.0.0-1 +- update to 2.0.0 + +* Tue Feb 25 2003 Jeff Johnson 1.9.4-0.20030228 +- update to 1.9.4 from CVS. +- dwarf patch from Graydon Hoare. +- sysinfo patch from Graydon Hoare, take 1. + +* Fri Feb 14 2003 Jeff Johnson 1.9.3-6.20030207 +- add return codes to syscalls. +- fix: set errno after syscalls. + +* Tue Feb 11 2003 Graydon Hoare 1.9.3-5.20030207 +- add handling for separate debug info (+fix). +- handle blocking readv/writev correctly. +- comment out 4 overly zealous pthread checks. + +* Tue Feb 11 2003 Jeff Johnson 1.9.3-4.20030207 +- move _pthread_desc to vg_include.h. +- implement pthread_mutex_timedlock(). +- implement pthread_barrier_wait(). + +* Mon Feb 10 2003 Jeff Johnson 1.9.3-3.20030207 +- import all(afaik) missing functionality from linuxthreads. + +* Sun Feb 9 2003 Jeff Johnson 1.9.3-2.20030207 +- import more missing functionality from linuxthreads in glibc-2.3.1. + +* Sat Feb 8 2003 Jeff Johnson 1.9.3-1.20030207 +- start fixing nptl test cases. + +* Fri Feb 7 2003 Jeff Johnson 1.9.3-0.20030207 +- build against current 1.9.3 with nptl hacks. + +* Tue Oct 15 2002 Alexander Larsson +- Update to 1.0.4 + +* Fri Aug 9 2002 Alexander Larsson +- Update to 1.0.0 + +* Wed Jul 3 2002 Alexander Larsson +- Update to pre4. + +* Tue Jun 18 2002 Alexander Larsson +- Add threadkeys and extra suppressions patches. Bump epoch. + +* Mon Jun 17 2002 Alexander Larsson +- Updated to 1.0pre1 + +* Tue May 28 2002 Alex Larsson +- Updated to 20020524. Added GLIBC_PRIVATE patch + +* Thu May 9 2002 Jonathan Blandford +- add missing symbol __pthread_clock_settime + +* Wed May 8 2002 Alex Larsson +- Update to 20020508 + +* Mon May 6 2002 Alex Larsson +- Update to 20020503b + +* Thu May 2 2002 Alex Larsson +- update to new snapshot + +* Mon Apr 29 2002 Alex Larsson 20020428-1 +- update to new snapshot + +* Fri Apr 26 2002 Jeremy Katz 20020426-1 +- update to new snapshot + +* Thu Apr 25 2002 Alex Larsson 20020424-5 +- Added stack patch. Commented out other patches. + +* Wed Apr 24 2002 Nalin Dahyabhai 20020424-4 +- filter out GLIBC_PRIVATE requires, add preload patch + +* Wed Apr 24 2002 Alex Larsson 20020424-3 +- Make glibc 2.2 and XFree86 4 the default supressions + +* Wed Apr 24 2002 Alex Larsson 20020424-2 +- Added patch that includes atomic.h + +* Wed Apr 24 2002 Alex Larsson 20020424-1 +- Initial build