import gcc-toolset-11-gdb-10.2-5.el8
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0ffd305e31
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@ -395,3 +395,8 @@ Patch095: gdb-testsuite26997-fix-array-slices-m32.patch
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# Backport "adjust gdb.python/flexible-array-member.exp expected pattern"
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# (Simon Marchi)
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Patch096: gdb-flexible-array-member-expected-pattern.patch
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# Backport "Fix avx512 -m32 support in gdbserver"
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# (Tom de Vries, RHBZ 2019936)
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Patch097: gdb-rhbz2019936-gdbserver-avx512-m32.patch
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@ -94,3 +94,4 @@
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%patch094 -p1
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%patch095 -p1
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%patch096 -p1
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%patch097 -p1
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170
SOURCES/gdb-rhbz2019936-gdbserver-avx512-m32.patch
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170
SOURCES/gdb-rhbz2019936-gdbserver-avx512-m32.patch
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@ -0,0 +1,170 @@
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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Tom de Vries <tdevries@suse.de>
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Date: Mon, 6 Dec 2021 15:39:03 -0500
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Subject: gdb-rhbz2019936-gdbserver-avx512-m32.patch
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;; Backport "Fix avx512 -m32 support in gdbserver"
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;; (Tom de Vries, RHBZ 2019936)
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PR27257 reports a problem that can be reproduced as follows:
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- use x86_64 machine with avx512 support
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- compile a hello world with -m32 to a.out
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- start a gdbserver session with a.out
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- use gdb to connect to the gdbserver session
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This makes us run into:
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...
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Listening on port 2346
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Remote debugging from host ::1, port 34940
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src/gdbserver/regcache.cc:257: \
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A problem internal to GDBserver has been detected.
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Unknown register zmm16h requested
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...
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The problem is that i387_xsave_to_cache in gdbserver/i387-fp.cc can't find a
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register zmm16h in the register cache.
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To understand how this happens, first some background.
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SSE has 16 128-bit wide xmm registers.
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AVX extends the SSE registers set as follows:
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- it extends the 16 existing 128-bit wide xmm registers to 256-bit wide ymm
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registers.
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AVX512 extends the AVX register set as follows:
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- it extends the 16 existing 256-bit wide ymm registers to 512-bit wide zmm
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registers.
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- it adds 16 additional 512-bit wide zmm registers (with corresponding ymm and
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xmm subregisters added as well)
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However, in 32-bit mode, there are only 8 xmm/ymm/zmm registers.
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The problem we're running into is that gdbserver/i387-fp.cc uses these
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constants to describe the size of the register file:
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...
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static const int num_avx512_zmmh_low_registers = 16;
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static const int num_avx512_zmmh_high_registers = 16;
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static const int num_avx512_ymmh_registers = 16;
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static const int num_avx512_xmm_registers = 16;
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...
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which are all incorrect for the 32-bit case.
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Fix this by replacing the constants with variables that have the appropriate
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values in 64-bit and 32-bit mode.
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Tested on x86_64-linux with native and unix/-m32.
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diff --git a/gdbserver/i387-fp.cc b/gdbserver/i387-fp.cc
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--- a/gdbserver/i387-fp.cc
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+++ b/gdbserver/i387-fp.cc
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@@ -23,10 +23,6 @@
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static const int num_mpx_bnd_registers = 4;
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static const int num_mpx_cfg_registers = 2;
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static const int num_avx512_k_registers = 8;
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-static const int num_avx512_zmmh_low_registers = 16;
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-static const int num_avx512_zmmh_high_registers = 16;
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-static const int num_avx512_ymmh_registers = 16;
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-static const int num_avx512_xmm_registers = 16;
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static const int num_pkeys_registers = 1;
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/* Note: These functions preserve the reserved bits in control registers.
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@@ -256,14 +252,22 @@ void
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i387_cache_to_xsave (struct regcache *regcache, void *buf)
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{
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struct i387_xsave *fp = (struct i387_xsave *) buf;
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+ bool amd64 = register_size (regcache->tdesc, 0) == 8;
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int i;
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unsigned long val, val2;
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unsigned long long xstate_bv = 0;
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unsigned long long clear_bv = 0;
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char raw[64];
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char *p;
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+
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/* Amd64 has 16 xmm regs; I386 has 8 xmm regs. */
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- int num_xmm_registers = register_size (regcache->tdesc, 0) == 8 ? 16 : 8;
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+ int num_xmm_registers = amd64 ? 16 : 8;
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+ /* AVX512 extends the existing xmm/ymm registers to a wider mode: zmm. */
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+ int num_avx512_zmmh_low_registers = num_xmm_registers;
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+ /* AVX512 adds 16 extra regs in Amd64 mode, but none in I386 mode.*/
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+ int num_avx512_zmmh_high_registers = amd64 ? 16 : 0;
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+ int num_avx512_ymmh_registers = amd64 ? 16 : 0;
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+ int num_avx512_xmm_registers = amd64 ? 16 : 0;
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/* The supported bits in `xstat_bv' are 8 bytes. Clear part in
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vector registers if its bit in xstat_bv is zero. */
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@@ -452,7 +456,9 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf)
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/* Check if any of ZMM16H-ZMM31H registers are changed. */
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if ((x86_xcr0 & X86_XSTATE_ZMM))
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{
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- int zmm16h_regnum = find_regno (regcache->tdesc, "zmm16h");
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+ int zmm16h_regnum = (num_avx512_zmmh_high_registers == 0
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+ ? -1
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+ : find_regno (regcache->tdesc, "zmm16h"));
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for (i = 0; i < num_avx512_zmmh_high_registers; i++)
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{
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@@ -469,7 +475,9 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf)
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/* Check if any XMM_AVX512 registers are changed. */
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if ((x86_xcr0 & X86_XSTATE_ZMM))
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{
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- int xmm_avx512_regnum = find_regno (regcache->tdesc, "xmm16");
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+ int xmm_avx512_regnum = (num_avx512_xmm_registers == 0
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+ ? -1
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+ : find_regno (regcache->tdesc, "xmm16"));
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for (i = 0; i < num_avx512_xmm_registers; i++)
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{
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@@ -486,7 +494,9 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf)
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/* Check if any YMMH_AVX512 registers are changed. */
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if ((x86_xcr0 & X86_XSTATE_ZMM))
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{
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- int ymmh_avx512_regnum = find_regno (regcache->tdesc, "ymm16h");
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+ int ymmh_avx512_regnum = (num_avx512_ymmh_registers == 0
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+ ? -1
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+ : find_regno (regcache->tdesc, "ymm16h"));
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for (i = 0; i < num_avx512_ymmh_registers; i++)
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{
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@@ -710,12 +720,20 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf)
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{
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struct i387_xsave *fp = (struct i387_xsave *) buf;
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struct i387_fxsave *fxp = (struct i387_fxsave *) buf;
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+ bool amd64 = register_size (regcache->tdesc, 0) == 8;
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int i, top;
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unsigned long val;
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unsigned long long clear_bv;
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gdb_byte *p;
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- /* Amd64 has 16 xmm regs; I386 has 8 xmm regs. */
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- int num_xmm_registers = register_size (regcache->tdesc, 0) == 8 ? 16 : 8;
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+
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+ /* Amd64 has 16 xmm regs; I386 has 8 xmm regs. */
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+ int num_xmm_registers = amd64 ? 16 : 8;
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+ /* AVX512 extends the existing xmm/ymm registers to a wider mode: zmm. */
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+ int num_avx512_zmmh_low_registers = num_xmm_registers;
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+ /* AVX512 adds 16 extra regs in Amd64 mode, but none in I386 mode.*/
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+ int num_avx512_zmmh_high_registers = amd64 ? 16 : 0;
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+ int num_avx512_ymmh_registers = amd64 ? 16 : 0;
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+ int num_avx512_xmm_registers = amd64 ? 16 : 0;
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/* The supported bits in `xstat_bv' are 8 bytes. Clear part in
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vector registers if its bit in xstat_bv is zero. */
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@@ -845,9 +863,15 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf)
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if ((x86_xcr0 & X86_XSTATE_ZMM) != 0)
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{
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- int zmm16h_regnum = find_regno (regcache->tdesc, "zmm16h");
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- int ymm16h_regnum = find_regno (regcache->tdesc, "ymm16h");
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- int xmm16_regnum = find_regno (regcache->tdesc, "xmm16");
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+ int zmm16h_regnum = (num_avx512_zmmh_high_registers == 0
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+ ? -1
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+ : find_regno (regcache->tdesc, "zmm16h"));
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+ int ymm16h_regnum = (num_avx512_ymmh_registers == 0
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+ ? -1
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+ : find_regno (regcache->tdesc, "ymm16h"));
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+ int xmm16_regnum = (num_avx512_xmm_registers == 0
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+ ? -1
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+ : find_regno (regcache->tdesc, "xmm16"));
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if ((clear_bv & X86_XSTATE_ZMM) != 0)
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{
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@ -37,7 +37,7 @@ Version: 10.2
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# The release always contains a leading reserved number, start it at 1.
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# `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing.
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Release: 4%{?dist}
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Release: 5%{?dist}
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License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ and GPLv2+ with exceptions and GPL+ and LGPLv2+ and LGPLv3+ and BSD and Public Domain and GFDL
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# Do not provide URL for snapshots as the file lasts there only for 2 days.
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@ -1157,6 +1157,10 @@ fi
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%endif
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%changelog
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* Wed Dec 8 2021 Keith Seitz <keiths@redhat.com> - 10.2-5.el8
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- Backport "Fix avx512 -m32 support in gdbserver"
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- (Tom de Vries, RH BZ 2011520)
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* Thu Jun 10 2021 Keith Seitz <keiths@redhat.com> - 10.2-4.el8
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- Backport "Fix gdb.fortran/array-slices.exp with -m32"
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(Tom de Vries, testsuite/269970)
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