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From 97bf40d859ffe44892b3ad2c62f011fd26fca699 Mon Sep 17 00:00:00 2001
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From: Alan Modra <amodra@gmail.com>
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Date: Mon, 5 Apr 2021 08:17:06 +0930
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Subject: [PATCH] PR27676, PowerPC missing extended dcbt, dcbtst mnemonics
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Note that this doesn't implement the ISA to the letter regarding
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dcbtds (and dcbtstds), which says that the TH field may be zero. That
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doesn't make sense because allowing TH=0 would mean you no long have a
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dcbtds but rather a dcbtct instruction. I'm interpreting the ISA
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wording about allowing TH=0 to mean that the TH field of dcbtds is
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optional (in which case the TH value is 0b1000).
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opcodes/
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PR 27676
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* ppc-opc.c (DCBT_EO): Move earlier.
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(insert_thct, extract_thct, insert_thds, extract_thds): New functions.
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(powerpc_operands): Add THCT and THDS entries.
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(powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
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gas/
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* testsuite/gas/ppc/power4_32.d: Update.
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---
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gas/testsuite/gas/ppc/power4_32.d | 6 +--
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opcodes/ppc-opc.c | 89 ++++++++++++++++++++++++++++---
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diff --git a/gas/testsuite/gas/ppc/power4_32.d b/gas/testsuite/gas/ppc/power4_32.d
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index 39c80dd4d2e5..8396d7d294fb 100644
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--- a/gas/testsuite/gas/ppc/power4_32.d
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+++ b/gas/testsuite/gas/ppc/power4_32.d
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@@ -41,7 +41,7 @@ Disassembly of section \.text:
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7c: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2
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80: (7c 23 27 ec|ec 27 23 7c) dcbzl r3,r4
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84: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6
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- 88: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
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- 8c: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
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- 90: (7d 05 32 2c|2c 32 05 7d) dcbt r5,r6,8
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+ 88: (7c 05 32 2c|2c 32 05 7c) dcbtct r5,r6
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+ 8c: (7c 05 32 2c|2c 32 05 7c) dcbtct r5,r6
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+ 90: (7d 05 32 2c|2c 32 05 7d) dcbtds r5,r6
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#pass
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diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
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index 97982ab7e754..025a2ba2fba7 100644
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--- a/opcodes/ppc-opc.c
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+++ b/opcodes/ppc-opc.c
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@@ -2205,6 +2205,74 @@ extract_sxl (uint64_t insn,
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return 1;
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return (insn >> 11) & 0x1;
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}
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+
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+/* The list of embedded processors that use the embedded operand ordering
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+ for the 3 operand dcbt and dcbtst instructions. */
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+#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
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+ | PPC_OPCODE_A2)
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+
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+/* ISA 2.03 and later specify extended mnemonics dcbtct, dcbtds, and
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+ dcbtstct, dcbtstds with a note saying these should be used in new
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+ programs rather than the base mnemonics "so that it can be coded
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+ with TH as the last operand for all categories". For that reason
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+ the extended mnemonics are enabled in the assembler for the
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+ embedded processors, but not for the disassembler so as to display
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+ the embedded dcbt or dcbtst expected form with TH first for
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+ embedded programmers. */
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+
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+static uint64_t
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+insert_thct (uint64_t insn,
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+ int64_t value,
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+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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+ const char **errmsg)
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+{
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+ if ((uint64_t) value > 7)
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+ *errmsg = _("invalid TH value");
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+ return insn | ((value & 7) << 21);
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+}
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+
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+static int64_t
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+extract_thct (uint64_t insn,
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+ ppc_cpu_t dialect,
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+ int *invalid)
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+{
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+ /* Missing optional operands have a value of 0. */
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+ if (*invalid < 0)
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+ return 0;
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+
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+ int64_t value = (insn >> 21) & 0x1f;
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+ if (value > 7 || (dialect & DCBT_EO) != 0)
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+ *invalid = 1;
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+
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+ return value;
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+}
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+
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+static uint64_t
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+insert_thds (uint64_t insn,
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+ int64_t value,
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+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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+ const char **errmsg)
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+{
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+ if (value < 8 || value > 15)
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+ *errmsg = _("invalid TH value");
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+ return insn | ((value & 0x1f) << 21);
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+}
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+
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+static int64_t
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+extract_thds (uint64_t insn,
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+ ppc_cpu_t dialect,
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+ int *invalid)
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+{
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+ /* Missing optional operands have a value of 8. */
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+ if (*invalid < 0)
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+ return 8;
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+
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+ int64_t value = (insn >> 21) & 0x1f;
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+ if (value < 8 || value > 15 || (dialect & DCBT_EO) != 0)
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+ *invalid = 1;
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+
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+ return value;
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+}
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/* The operands table.
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@@ -2402,10 +2470,18 @@ const struct powerpc_operand powerpc_operands[] =
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#define MO CT
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{ 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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+ /* The TH field in dcbtct. */
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+#define THCT CT + 1
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+ { 0x1f, 21, insert_thct, extract_thct, PPC_OPERAND_OPTIONAL },
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+
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+ /* The TH field in dcbtds. */
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+#define THDS THCT + 1
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+ { 0x1f, 21, insert_thds, extract_thds, PPC_OPERAND_OPTIONAL },
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+
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/* The D field in a D form instruction. This is a displacement off
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a register, and implies that the next operand is a register in
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parentheses. */
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-#define D CT + 1
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+#define D THDS + 1
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{ 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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/* The D8 field in a D form instruction. This is a displacement off
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@@ -4211,12 +4287,6 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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#define PPCHTM PPC_OPCODE_POWER8
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#define E200Z4 PPC_OPCODE_E200Z4
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#define PPCLSP PPC_OPCODE_LSP
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-/* The list of embedded processors that use the embedded operand ordering
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- for the 3 operand dcbt and dcbtst instructions. */
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-#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
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- | PPC_OPCODE_A2)
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-
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-
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/* The opcode table.
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@@ -6592,6 +6662,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
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{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
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+{"dcbtstct", X(31,246), X_MASK, POWER4, 0, {RA0, RB, THCT}},
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+{"dcbtstds", X(31,246), X_MASK, POWER4, 0, {RA0, RB, THDS}},
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{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
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{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
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{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
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@@ -6643,6 +6715,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
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{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
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+{"dcbna", XRT(31,278,0x11), XRT_MASK, POWER10, 0, {RA0, RB}},
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+{"dcbtct", X(31,278), X_MASK, POWER4, 0, {RA0, RB, THCT}},
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+{"dcbtds", X(31,278), X_MASK, POWER4, 0, {RA0, RB, THDS}},
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{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
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{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
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{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
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