147 lines
4.0 KiB
Diff
147 lines
4.0 KiB
Diff
From c3103091f40eaedd03a1f1bcb3503311a6072927 Mon Sep 17 00:00:00 2001
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From: Peter Lemenkov <lemenkov@gmail.com>
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Date: Tue, 21 Sep 2010 17:51:08 +0400
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Subject: [PATCH 07/12] Simplify hwaccess.c
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This file is saturated with superfluous ifdefs arranged into
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several nested levels. This in turn adds additional complexity
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to process of adding another architecture.
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I re-arranged all ifdef blocks and killed duplicated function
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definitions. Also I added define(__amd64) to the list of x86-arches.
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Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
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---
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hwaccess.c | 85 +++++++++++++++++++++--------------------------------------
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1 files changed, 30 insertions(+), 55 deletions(-)
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diff --git a/hwaccess.c b/hwaccess.c
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index bbb91a6..e700b67 100644
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--- a/hwaccess.c
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+++ b/hwaccess.c
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@@ -31,30 +31,47 @@
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#endif
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#include "flash.h"
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+#if !( defined(__i386__) || \
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+ defined(__x86_64__) || defined(__amd64) || \
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+ defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) || \
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+ defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__))
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+#error Unknown architecture
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+#endif
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+
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#if defined(__i386__) || defined(__x86_64__)
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+#if defined(__FreeBSD__) || defined(__DragonFly__)
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+int io_fd;
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+#endif
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+#endif
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-/* sync primitive is not needed because x86 uses uncached accesses
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- * which have a strongly ordered memory model.
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- */
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static inline void sync_primitive(void)
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{
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-}
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-
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-#if defined(__FreeBSD__) || defined(__DragonFly__)
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-int io_fd;
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+/* sync primitive is needed only on PowerPC because
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+ * x86 uses uncached accesses which have a strongly ordered memory model
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+ * /dev/mem on MIPS uses uncached accesses in mode 2 which has a strongly ordered memory model.
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+ */
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+#if defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
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+ /* Prevent reordering and/or merging of reads/writes to hardware.
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+ * Such reordering and/or merging would break device accesses which
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+ * depend on the exact access order.
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+ */
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+ asm("eieio" : : : "memory");
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#endif
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+}
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void get_io_perms(void)
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{
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+/* PCI port I/O is not yet implemented on PowerPC or MIPS. */
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+#if defined(__i386__) || defined(__x86_64__) || defined(__amd64)
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#if defined(__DJGPP__) || defined(__LIBPAYLOAD__)
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/* We have full permissions by default. */
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return;
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#else
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-#if defined (__sun) && (defined(__i386) || defined(__amd64))
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+#if defined (__sun)
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if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
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#elif defined(__FreeBSD__) || defined (__DragonFly__)
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if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
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-#else
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+#else
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if (iopl(3) != 0) {
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#endif
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msg_perr("ERROR: Could not get I/O privileges (%s).\n"
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@@ -67,60 +84,18 @@ void get_io_perms(void)
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exit(1);
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}
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#endif
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+#endif
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}
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void release_io_perms(void)
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{
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+/* PCI port I/O is not yet implemented on PowerPC or MIPS. */
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+#if defined(__i386__) || defined(__x86_64__) || defined(__amd64)
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#if defined(__FreeBSD__) || defined(__DragonFly__)
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close(io_fd);
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#endif
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-}
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-
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-#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
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-
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-static inline void sync_primitive(void)
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-{
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- /* Prevent reordering and/or merging of reads/writes to hardware.
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- * Such reordering and/or merging would break device accesses which
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- * depend on the exact access order.
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- */
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- asm("eieio" : : : "memory");
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-}
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-
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-/* PCI port I/O is not yet implemented on PowerPC. */
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-void get_io_perms(void)
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-{
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-}
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-
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-/* PCI port I/O is not yet implemented on PowerPC. */
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-void release_io_perms(void)
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-{
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-}
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-
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-#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
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-
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-/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses
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- * in mode 2 which has a strongly ordered memory model.
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- */
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-static inline void sync_primitive(void)
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-{
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-}
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-
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-/* PCI port I/O is not yet implemented on MIPS. */
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-void get_io_perms(void)
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-{
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-}
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-
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-/* PCI port I/O is not yet implemented on MIPS. */
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-void release_io_perms(void)
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-{
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-}
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-
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-#else
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-
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-#error Unknown architecture
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-
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#endif
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+}
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void mmio_writeb(uint8_t val, void *addr)
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{
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--
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1.7.3.1
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