42 lines
1.6 KiB
Diff
42 lines
1.6 KiB
Diff
From 625a70fc26d752b0025eae19682b386f44fa089b Mon Sep 17 00:00:00 2001
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Tue, 30 Jan 2024 14:04:39 +0100
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Subject: [PATCH] MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache types
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RH-Author: Gerd Hoffmann <None>
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RH-MergeRequest: 55: OvmfPkg/Sec: Setup MTRR early in the boot process.
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RH-Jira: RHEL-21704
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Commit: [2/4] a568bc2793d677462a2971aae9566a9bbc64b063 (kraxel.rh/centos-src-edk2)
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Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
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Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Message-ID: <20240130130441.772484-3-kraxel@redhat.com>
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patch_name: edk2-MdePkg-ArchitecturalMsr.h-add-defines-for-MTRR-cache.patch
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present_in_specfile: true
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location_in_specfile: 50
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---
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MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
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index 756e7c86ec..08ba949cf7 100644
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--- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
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+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
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@@ -2103,6 +2103,13 @@ typedef union {
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#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
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/// @}
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+#define MSR_IA32_MTRR_CACHE_UNCACHEABLE 0
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+#define MSR_IA32_MTRR_CACHE_WRITE_COMBINING 1
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+#define MSR_IA32_MTRR_CACHE_WRITE_THROUGH 4
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+#define MSR_IA32_MTRR_CACHE_WRITE_PROTECTED 5
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+#define MSR_IA32_MTRR_CACHE_WRITE_BACK 6
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+#define MSR_IA32_MTRR_CACHE_INVALID_TYPE 7
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+
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/**
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MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
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#MSR_IA32_MTRR_PHYSBASE9
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