143 lines
4.7 KiB
Diff
143 lines
4.7 KiB
Diff
From c4aa4797fafa3a627205eaa346401e399d4a7146 Mon Sep 17 00:00:00 2001
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Tue, 27 Aug 2024 12:06:15 +0200
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Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: skip PatchInstructionX86 calls if
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not needed.
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RH-Author: Oliver Steffen <osteffen@redhat.com>
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RH-MergeRequest: 71: UefiCpuPkg/PiSmmCpuDxeSmm: skip PatchInstructionX86 calls if not needed.
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RH-Jira: RHEL-45847
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RH-Acked-by: Gerd Hoffmann <None>
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RH-Commit: [1/1] 70ceffb2c1e695276af87d3aa334fe9be8e2e90e (osteffen/edk2)
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Add the new global mMsrIa32MiscEnableSupported variable to track
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whenever support for the IA32_MISC_ENABLE MSR is present or not.
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Add new local PatchingNeeded variable to CheckFeatureSupported()
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to track if patching the SMM setup code is needed or not.
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Issue PatchInstructionX86() calls only if needed, i.e. if one of
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the *Supported variables has been updated.
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Result is that on a typical SMP machine where all processors are
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identical the PatchInstructionX86() calls are issued only once,
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when checking the first processor. Specifically this avoids
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PatchInstructionX86() being called in OVMF on CPU hotplug. That
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is important because instruction patching at runtime does not not
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work and leads to page faults.
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This fixes CPU hotplug on OVMF not working with AMD cpus.
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Fixes: 6b3a89a9fdb5 ("OvmfPkg/PlatformPei: Relocate SmBases in PEI phase")
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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(cherry picked from commit 17ff8960848b2cb2e49fffb3dfbacd08865786a4)
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---
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UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 49 +++++++++++++++++++++-----
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1 file changed, 40 insertions(+), 9 deletions(-)
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diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
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index 8142d3ceac..8e299fd29a 100644
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--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
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+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
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@@ -40,6 +40,11 @@ BOOLEAN mXdEnabled = FALSE;
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//
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BOOLEAN mBtsSupported = TRUE;
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+//
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+// The flag indicates if MSR_IA32_MISC_ENABLE is supported by processor
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+//
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+BOOLEAN mMsrIa32MiscEnableSupported = TRUE;
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+
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//
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// The flag indicates if SMM profile starts to record data.
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//
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@@ -904,18 +909,23 @@ CheckFeatureSupported (
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UINT32 RegEcx;
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UINT32 RegEdx;
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MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;
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+ BOOLEAN PatchingNeeded = FALSE;
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if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
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AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);
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if (RegEax >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) {
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AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, NULL);
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if ((RegEcx & CPUID_CET_SS) == 0) {
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- mCetSupported = FALSE;
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- PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
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+ if (mCetSupported) {
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+ mCetSupported = FALSE;
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+ PatchingNeeded = TRUE;
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+ }
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}
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} else {
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- mCetSupported = FALSE;
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- PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
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+ if (mCetSupported) {
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+ mCetSupported = FALSE;
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+ PatchingNeeded = TRUE;
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+ }
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}
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}
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@@ -925,8 +935,10 @@ CheckFeatureSupported (
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//
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// Extended CPUID functions are not supported on this processor.
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//
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- mXdSupported = FALSE;
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- PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);
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+ if (mXdSupported) {
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+ mXdSupported = FALSE;
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+ PatchingNeeded = TRUE;
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+ }
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}
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AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
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@@ -934,15 +946,20 @@ CheckFeatureSupported (
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//
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// Execute Disable Bit feature is not supported on this processor.
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//
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- mXdSupported = FALSE;
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- PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);
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+ if (mXdSupported) {
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+ mXdSupported = FALSE;
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+ PatchingNeeded = TRUE;
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+ }
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}
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if (StandardSignatureIsAuthenticAMD ()) {
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//
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// AMD processors do not support MSR_IA32_MISC_ENABLE
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//
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- PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1);
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+ if (mMsrIa32MiscEnableSupported) {
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+ mMsrIa32MiscEnableSupported = FALSE;
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+ PatchingNeeded = TRUE;
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+ }
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}
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}
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@@ -966,6 +983,20 @@ CheckFeatureSupported (
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}
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}
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}
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+
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+ if (PatchingNeeded) {
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+ if (!mCetSupported) {
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+ PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
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+ }
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+
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+ if (!mXdSupported) {
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+ PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);
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+ }
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+
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+ if (!mMsrIa32MiscEnableSupported) {
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+ PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1);
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+ }
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+ }
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}
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/**
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--
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2.39.3
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