74 lines
2.8 KiB
Diff
74 lines
2.8 KiB
Diff
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From: Ruiyu Ni <ruiyu.ni@intel.com>
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Subject: [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource
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Date: Thu, 16 Nov 2017 18:15:14 +0100
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The bug was caused by 728d74973c9262b6c7b7ef4be213223d55affec3
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"MdeModulePkg/PciBus: Count multiple hotplug resource paddings".
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The patch firstly updated the Bridge->Alignment to the maximum
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alignment of all devices under the bridge, then aligned the
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Bridge->Length to Bridge->Alignment.
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It caused too much resources were claimed.
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The new patch firstly aligns Bridge->Length to Bridge->Alignment,
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then updates the Bridge->Alignment to the maximum alignment of all
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devices under the bridge.
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Because the step to update the Bridge->Alignment is to make sure
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the resource allocated to the bus under the Bridge meets all
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devices alignment. But the Bridge->Length doesn't have to align
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to the maximum alignment.
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Contributed-under: TianoCore Contribution Agreement 1.1
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Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
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Reviewed-by: Eric Dong <eric.dong@intel.com>
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(cherry picked from commit 6e3287442774c1a4bc83f127694700eeb07c18dc)
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---
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MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 24 ++++++++++----------
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1 file changed, 12 insertions(+), 12 deletions(-)
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diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
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index 8dbe9a00380f..2f713fcee95e 100644
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--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
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+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
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@@ -389,18 +389,7 @@ CalculateResourceAperture (
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}
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//
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- // Adjust the bridge's alignment to the MAX (first) alignment of all children.
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- //
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- CurrentLink = Bridge->ChildList.ForwardLink;
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- if (CurrentLink != &Bridge->ChildList) {
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- Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
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- if (Node->Alignment > Bridge->Alignment) {
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- Bridge->Alignment = Node->Alignment;
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- }
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- }
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-
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- //
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- // At last, adjust the aperture with the bridge's alignment
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+ // Adjust the aperture with the bridge's alignment
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//
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Aperture[PciResUsageTypical] = ALIGN_VALUE (Aperture[PciResUsageTypical], Bridge->Alignment + 1);
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Aperture[PciResUsagePadding] = ALIGN_VALUE (Aperture[PciResUsagePadding], Bridge->Alignment + 1);
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@@ -410,6 +399,17 @@ CalculateResourceAperture (
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// Use the larger one between the padding resource and actual occupied resource.
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//
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Bridge->Length = MAX (Aperture[PciResUsageTypical], Aperture[PciResUsagePadding]);
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+
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+ //
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+ // Adjust the bridge's alignment to the MAX (first) alignment of all children.
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+ //
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+ CurrentLink = Bridge->ChildList.ForwardLink;
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+ if (CurrentLink != &Bridge->ChildList) {
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+ Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
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+ if (Node->Alignment > Bridge->Alignment) {
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+ Bridge->Alignment = Node->Alignment;
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+ }
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+ }
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}
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/**
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--
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2.14.1.3.gb7cf6e02401b
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