edk2/0032-UefiCpuPkg-MtrrLib.h-use-cache-type-defines-from-Arc.patch

From 75618356e04278e4346ffc5e147b9f6f101e8173 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Tue, 30 Jan 2024 14:04:40 +0100
Subject: [PATCH] UefiCpuPkg/MtrrLib.h: use cache type #defines from
 ArchitecturalMsr.h

RH-Author: Gerd Hoffmann <None>
RH-MergeRequest: 55: OvmfPkg/Sec: Setup MTRR early in the boot process.
RH-Jira: RHEL-21704
RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
RH-Commit: [3/4] 8b766c97b247a8665662697534455c19423ff23c (kraxel.rh/centos-src-edk2)

Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-ID: <20240130130441.772484-4-kraxel@redhat.com>

patch_name: edk2-UefiCpuPkg-MtrrLib.h-use-cache-type-defines-from-Arc.patch
present_in_specfile: true
location_in_specfile: 51
---
 UefiCpuPkg/Include/Library/MtrrLib.h | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h
index 86cc1aab3b..287d249a99 100644
--- a/UefiCpuPkg/Include/Library/MtrrLib.h
+++ b/UefiCpuPkg/Include/Library/MtrrLib.h
@@ -9,6 +9,8 @@
 #ifndef  _MTRR_LIB_H_
 #define  _MTRR_LIB_H_
 
+#include <Register/Intel/ArchitecturalMsr.h>
+
 //
 // According to IA32 SDM, MTRRs number and MSR offset are always consistent
 // for IA32 processor family
@@ -82,20 +84,20 @@ typedef struct _MTRR_SETTINGS_ {
 // Memory cache types
 //
 typedef enum {
-  CacheUncacheable    = 0,
-  CacheWriteCombining = 1,
-  CacheWriteThrough   = 4,
-  CacheWriteProtected = 5,
-  CacheWriteBack      = 6,
-  CacheInvalid        = 7
+  CacheUncacheable    = MSR_IA32_MTRR_CACHE_UNCACHEABLE,
+  CacheWriteCombining = MSR_IA32_MTRR_CACHE_WRITE_COMBINING,
+  CacheWriteThrough   = MSR_IA32_MTRR_CACHE_WRITE_THROUGH,
+  CacheWriteProtected = MSR_IA32_MTRR_CACHE_WRITE_PROTECTED,
+  CacheWriteBack      = MSR_IA32_MTRR_CACHE_WRITE_BACK,
+  CacheInvalid        = MSR_IA32_MTRR_CACHE_INVALID_TYPE,
 } MTRR_MEMORY_CACHE_TYPE;
 
-#define  MTRR_CACHE_UNCACHEABLE      0
-#define  MTRR_CACHE_WRITE_COMBINING  1
-#define  MTRR_CACHE_WRITE_THROUGH    4
-#define  MTRR_CACHE_WRITE_PROTECTED  5
-#define  MTRR_CACHE_WRITE_BACK       6
-#define  MTRR_CACHE_INVALID_TYPE     7
+#define  MTRR_CACHE_UNCACHEABLE      MSR_IA32_MTRR_CACHE_UNCACHEABLE
+#define  MTRR_CACHE_WRITE_COMBINING  MSR_IA32_MTRR_CACHE_WRITE_COMBINING
+#define  MTRR_CACHE_WRITE_THROUGH    MSR_IA32_MTRR_CACHE_WRITE_THROUGH
+#define  MTRR_CACHE_WRITE_PROTECTED  MSR_IA32_MTRR_CACHE_WRITE_PROTECTED
+#define  MTRR_CACHE_WRITE_BACK       MSR_IA32_MTRR_CACHE_WRITE_BACK
+#define  MTRR_CACHE_INVALID_TYPE     MSR_IA32_MTRR_CACHE_INVALID_TYPE
 
 typedef struct {
   UINT64                    BaseAddress;