2024-11-12 08:41:04 +00:00
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From f015a541308b2d752c399b9ef9597c4585218032 Mon Sep 17 00:00:00 2001
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2024-05-15 07:15:17 +00:00
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Tue, 30 Jan 2024 14:04:40 +0100
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2024-11-12 08:41:04 +00:00
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Subject: [PATCH] UefiCpuPkg/MtrrLib.h: use cache type #defines from
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2024-05-15 07:15:17 +00:00
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ArchitecturalMsr.h
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RH-Author: Gerd Hoffmann <None>
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RH-MergeRequest: 55: OvmfPkg/Sec: Setup MTRR early in the boot process.
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RH-Jira: RHEL-21704
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Commit: [3/4] 8b766c97b247a8665662697534455c19423ff23c (kraxel.rh/centos-src-edk2)
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Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
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Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Message-ID: <20240130130441.772484-4-kraxel@redhat.com>
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2024-11-12 08:41:04 +00:00
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patch_name: edk2-UefiCpuPkg-MtrrLib.h-use-cache-type-defines-from-Arc.patch
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present_in_specfile: true
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location_in_specfile: 51
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2024-05-15 07:15:17 +00:00
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---
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UefiCpuPkg/Include/Library/MtrrLib.h | 26 ++++++++++++++------------
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1 file changed, 14 insertions(+), 12 deletions(-)
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diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h
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index 86cc1aab3b..287d249a99 100644
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--- a/UefiCpuPkg/Include/Library/MtrrLib.h
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+++ b/UefiCpuPkg/Include/Library/MtrrLib.h
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@@ -9,6 +9,8 @@
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#ifndef _MTRR_LIB_H_
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#define _MTRR_LIB_H_
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+#include <Register/Intel/ArchitecturalMsr.h>
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+
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//
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// According to IA32 SDM, MTRRs number and MSR offset are always consistent
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// for IA32 processor family
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@@ -82,20 +84,20 @@ typedef struct _MTRR_SETTINGS_ {
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// Memory cache types
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//
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typedef enum {
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- CacheUncacheable = 0,
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- CacheWriteCombining = 1,
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- CacheWriteThrough = 4,
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- CacheWriteProtected = 5,
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- CacheWriteBack = 6,
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- CacheInvalid = 7
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+ CacheUncacheable = MSR_IA32_MTRR_CACHE_UNCACHEABLE,
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+ CacheWriteCombining = MSR_IA32_MTRR_CACHE_WRITE_COMBINING,
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+ CacheWriteThrough = MSR_IA32_MTRR_CACHE_WRITE_THROUGH,
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+ CacheWriteProtected = MSR_IA32_MTRR_CACHE_WRITE_PROTECTED,
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+ CacheWriteBack = MSR_IA32_MTRR_CACHE_WRITE_BACK,
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+ CacheInvalid = MSR_IA32_MTRR_CACHE_INVALID_TYPE,
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} MTRR_MEMORY_CACHE_TYPE;
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-#define MTRR_CACHE_UNCACHEABLE 0
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-#define MTRR_CACHE_WRITE_COMBINING 1
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-#define MTRR_CACHE_WRITE_THROUGH 4
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-#define MTRR_CACHE_WRITE_PROTECTED 5
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-#define MTRR_CACHE_WRITE_BACK 6
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-#define MTRR_CACHE_INVALID_TYPE 7
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+#define MTRR_CACHE_UNCACHEABLE MSR_IA32_MTRR_CACHE_UNCACHEABLE
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+#define MTRR_CACHE_WRITE_COMBINING MSR_IA32_MTRR_CACHE_WRITE_COMBINING
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+#define MTRR_CACHE_WRITE_THROUGH MSR_IA32_MTRR_CACHE_WRITE_THROUGH
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+#define MTRR_CACHE_WRITE_PROTECTED MSR_IA32_MTRR_CACHE_WRITE_PROTECTED
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+#define MTRR_CACHE_WRITE_BACK MSR_IA32_MTRR_CACHE_WRITE_BACK
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+#define MTRR_CACHE_INVALID_TYPE MSR_IA32_MTRR_CACHE_INVALID_TYPE
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typedef struct {
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UINT64 BaseAddress;
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