146 lines
3.8 KiB
Diff
146 lines
3.8 KiB
Diff
From 29e626f6ed3edb72ebd2ca3fe0e1fbd956ab71a1 Mon Sep 17 00:00:00 2001
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From: Jerry Hoemann <jerry.hoemann@hpe.com>
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Date: Wed, 20 Jun 2018 09:51:53 +0200
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Subject: [PATCH 16/21] dmidecode: Extensions to Memory Device (Type 17)
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The DSP0134 v3.2.0 extended the Memory Device (Type 17) structure
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starting at offset 28h continuing to 4Ch to reflect persistent memory.
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Signed-off-by: Jerry Hoemann <jerry.hoemann@hpe.com>
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Signed-off-by: Jean Delvare <jdelvare@suse.de>
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---
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dmidecode.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 110 insertions(+)
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diff --git a/dmidecode.c b/dmidecode.c
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index d18a258..f8c3b30 100644
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--- a/dmidecode.c
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+++ b/dmidecode.c
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@@ -2507,6 +2507,79 @@ static void dmi_memory_device_speed(u16 code)
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printf(" %u MT/s", code);
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}
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+static void dmi_memory_technology(u8 code)
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+{
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+ /* 7.18.6 */
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+ static const char * const technology[] = {
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+ "Other", /* 0x01 */
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+ "Unknown",
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+ "DRAM",
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+ "NVDIMM-N",
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+ "NVDIMM-F",
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+ "NVDIMM-P",
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+ "Intel persistent memory" /* 0x07 */
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+ };
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+ if (code >= 0x01 && code <= 0x07)
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+ printf(" %s", technology[code - 0x01]);
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+ else
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+ printf(" %s", out_of_spec);
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+}
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+
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+static void dmi_memory_operating_mode_capability(u16 code)
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+{
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+ /* 7.18.7 */
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+ static const char * const mode[] = {
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+ "Other", /* 1 */
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+ "Unknown",
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+ "Volatile memory",
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+ "Byte-accessible persistent memory",
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+ "Block-accessible persistent memory" /* 5 */
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+ };
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+
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+ if ((code & 0xFFFE) == 0)
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+ printf(" None");
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+ else {
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+ int i;
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+
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+ for (i = 1; i <= 5; i++)
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+ if (code & (1 << i))
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+ printf(" %s", mode[i - 1]);
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+ }
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+}
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+
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+static void dmi_memory_manufacturer_id(u16 code)
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+{
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+ /* 7.18.8 */
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+ /* 7.18.10 */
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+ /* LSB is 7-bit Odd Parity number of continuation codes */
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+ if (code == 0)
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+ printf(" Unknown");
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+ else
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+ printf(" Bank %d, Hex 0x%02X", (code & 0x7F) + 1, code >> 8);
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+}
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+
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+static void dmi_memory_product_id(u16 code)
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+{
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+ /* 7.18.9 */
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+ /* 7.18.11 */
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+ if (code == 0)
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+ printf(" Unknown");
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+ else
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+ printf(" 0x%04X", code);
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+}
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+
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+static void dmi_memory_size(u64 code)
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+{
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+ /* 7.18.12 */
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+ /* 7.18.13 */
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+ if (code.h == 0xFFFFFFFF && code.l == 0xFFFFFFFF)
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+ printf(" Unknown");
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+ else if (code.h == 0x0 && code.l == 0x0)
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+ printf(" None");
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+ else
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+ dmi_print_memory_size(code, 0);
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+}
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+
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/*
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* 7.19 32-bit Memory Error Information (Type 18)
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*/
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@@ -3907,6 +3980,43 @@ static void dmi_decode(const struct dmi_header *h, u16 ver)
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printf("\tConfigured Voltage:");
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dmi_memory_voltage_value(WORD(data + 0x26));
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printf("\n");
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+ if (h->length < 0x34) break;
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+ printf("\tMemory Technology:");
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+ dmi_memory_technology(data[0x28]);
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+ printf("\n");
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+ printf("\tMemory Operating Mode Capability:");
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+ dmi_memory_operating_mode_capability(WORD(data + 0x29));
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+ printf("\n");
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+ printf("\tFirmware Version: %s\n",
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+ dmi_string(h, data[0x2B]));
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+ printf("\tModule Manufacturer ID:");
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+ dmi_memory_manufacturer_id(WORD(data + 0x2C));
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+ printf("\n");
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+ printf("\tModule Product ID:");
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+ dmi_memory_product_id(WORD(data + 0x2E));
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+ printf("\n");
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+ printf("\tMemory Subsystem Controller Manufacturer ID:");
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+ dmi_memory_manufacturer_id(WORD(data + 0x30));
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+ printf("\n");
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+ printf("\tMemory Subsystem Controller Product ID:");
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+ dmi_memory_product_id(WORD(data + 0x32));
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+ printf("\n");
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+ if (h->length < 0x3C) break;
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+ printf("\tNon-Volatile Size:");
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+ dmi_memory_size(QWORD(data + 0x34));
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+ printf("\n");
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+ if (h->length < 0x44) break;
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+ printf("\tVolatile Size:");
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+ dmi_memory_size(QWORD(data + 0x3C));
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+ printf("\n");
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+ if (h->length < 0x4C) break;
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+ printf("\tCache Size:");
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+ dmi_memory_size(QWORD(data + 0x44));
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+ printf("\n");
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+ if (h->length < 0x54) break;
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+ printf("\tLogical Size:");
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+ dmi_memory_size(QWORD(data + 0x4C));
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+ printf("\n");
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break;
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case 18: /* 7.19 32-bit Memory Error Information */
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--
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2.17.1
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