349 lines
12 KiB
Diff
349 lines
12 KiB
Diff
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2015-10-14 Peter Bergner <bergner@vnet.ibm.com>
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Torvald Riegel <triegel@redhat.com>
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PR target/67281
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* config/rs6000/htm.md (UNSPEC_HTM_FENCE): New.
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(tabort, tabort<wd>c, tabort<wd>ci, tbegin, tcheck, tend,
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trechkpt, treclaim, tsr, ttest): Rename define_insns from this...
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(*tabort, *tabort<wd>c, *tabort<wd>ci, *tbegin, *tcheck, *tend,
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*trechkpt, *treclaim, *tsr, *ttest): ...to this. Add memory barrier.
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(tabort, tabort<wd>c, tabort<wd>ci, tbegin, tcheck, tend,
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trechkpt, treclaim, tsr, ttest): New define_expands.
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* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
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__TM_FENCE__ for htm.
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* doc/extend.texi: Update documentation for htm builtins.
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2015-08-03 Peter Bergner <bergner@vnet.ibm.com>
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* config/rs6000/htm.md (tabort.): Restrict the source operand to
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using a base register.
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* gcc.target/powerpc/htm-tabort-no-r0.c: New test.
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--- gcc/doc/extend.texi (revision 228826)
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+++ gcc/doc/extend.texi (revision 228827)
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@@ -16092,6 +16092,28 @@ unsigned int __builtin_tresume (void)
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unsigned int __builtin_tsuspend (void)
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@end smallexample
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+Note that the semantics of the above HTM builtins are required to mimic
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+the locking semantics used for critical sections. Builtins that are used
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+to create a new transaction or restart a suspended transaction must have
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+lock acquisition like semantics while those builtins that end or suspend a
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+transaction must have lock release like semantics. Specifically, this must
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+mimic lock semantics as specified by C++11, for example: Lock acquisition is
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+as-if an execution of __atomic_exchange_n(&globallock,1,__ATOMIC_ACQUIRE)
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+that returns 0, and lock release is as-if an execution of
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+__atomic_store(&globallock,0,__ATOMIC_RELEASE), with globallock being an
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+implicit implementation-defined lock used for all transactions. The HTM
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+instructions associated with with the builtins inherently provide the
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+correct acquisition and release hardware barriers required. However,
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+the compiler must also be prohibited from moving loads and stores across
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+the builtins in a way that would violate their semantics. This has been
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+accomplished by adding memory barriers to the associated HTM instructions
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+(which is a conservative approach to provide acquire and release semantics).
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+Earlier versions of the compiler did not treat the HTM instructions as
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+memory barriers. A @code{__TM_FENCE__} macro has been added, which can
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+be used to determine whether the current compiler treats HTM instructions
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+as memory barriers or not. This allows the user to explicitly add memory
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+barriers to their code when using an older version of the compiler.
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+
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The following set of built-in functions are available to gain access
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to the HTM specific special purpose registers.
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--- gcc/config/rs6000/htm.md (revision 226531)
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+++ gcc/config/rs6000/htm.md (revision 228827)
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@@ -27,6 +27,14 @@ (define_constants
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])
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;;
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+;; UNSPEC usage
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+;;
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+
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+(define_c_enum "unspec"
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+ [UNSPEC_HTM_FENCE
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+ ])
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+
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+;;
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;; UNSPEC_VOLATILE usage
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;;
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@@ -45,96 +53,223 @@ (define_c_enum "unspecv"
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UNSPECV_HTM_MTSPR
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])
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+(define_expand "tabort"
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+ [(parallel
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+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(match_operand:SI 0 "base_reg_operand" "b")]
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+ UNSPECV_HTM_TABORT))
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+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[2]) = 1;
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+})
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-(define_insn "tabort"
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+(define_insn "*tabort"
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[(set (match_operand:CC 1 "cc_reg_operand" "=x")
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- (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
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- UNSPECV_HTM_TABORT))]
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+ (unspec_volatile:CC [(match_operand:SI 0 "base_reg_operand" "b")]
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+ UNSPECV_HTM_TABORT))
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+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"tabort. %0"
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "tabort<wd>c"
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+(define_expand "tabort<wd>c"
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+ [(parallel
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+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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+ (match_operand:GPR 1 "gpc_reg_operand" "r")
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+ (match_operand:GPR 2 "gpc_reg_operand" "r")]
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+ UNSPECV_HTM_TABORTXC))
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+ (set (match_dup 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[4] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[4]) = 1;
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+})
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+
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+(define_insn "*tabort<wd>c"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x")
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(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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(match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "gpc_reg_operand" "r")]
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- UNSPECV_HTM_TABORTXC))]
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+ UNSPECV_HTM_TABORTXC))
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+ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"tabort<wd>c. %0,%1,%2"
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "tabort<wd>ci"
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+(define_expand "tabort<wd>ci"
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+ [(parallel
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+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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+ (match_operand:GPR 1 "gpc_reg_operand" "r")
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+ (match_operand 2 "s5bit_cint_operand" "n")]
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+ UNSPECV_HTM_TABORTXCI))
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+ (set (match_dup 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[4] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[4]) = 1;
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+})
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+
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+(define_insn "*tabort<wd>ci"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x")
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(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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(match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand 2 "s5bit_cint_operand" "n")]
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- UNSPECV_HTM_TABORTXCI))]
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+ UNSPECV_HTM_TABORTXCI))
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+ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"tabort<wd>ci. %0,%1,%2"
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "tbegin"
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+(define_expand "tbegin"
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+ [(parallel
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+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
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+ UNSPECV_HTM_TBEGIN))
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+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[2]) = 1;
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+})
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+
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+(define_insn "*tbegin"
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[(set (match_operand:CC 1 "cc_reg_operand" "=x")
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(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
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- UNSPECV_HTM_TBEGIN))]
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+ UNSPECV_HTM_TBEGIN))
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+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"tbegin. %0"
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "tcheck"
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+(define_expand "tcheck"
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+ [(parallel
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+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TCHECK))
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+ (set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[1]) = 1;
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+})
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+
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+(define_insn "*tcheck"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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- (unspec_volatile:CC [(const_int 0)]
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- UNSPECV_HTM_TCHECK))]
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+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TCHECK))
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+ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"tcheck %0"
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "tend"
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+(define_expand "tend"
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+ [(parallel
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+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
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+ UNSPECV_HTM_TEND))
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+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[2]) = 1;
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+})
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+
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+(define_insn "*tend"
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[(set (match_operand:CC 1 "cc_reg_operand" "=x")
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(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
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- UNSPECV_HTM_TEND))]
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+ UNSPECV_HTM_TEND))
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+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"tend. %0"
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "trechkpt"
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+(define_expand "trechkpt"
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+ [(parallel
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+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TRECHKPT))
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+ (set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[1]) = 1;
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+})
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+
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+(define_insn "*trechkpt"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x")
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- (unspec_volatile:CC [(const_int 0)]
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- UNSPECV_HTM_TRECHKPT))]
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+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TRECHKPT))
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+ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"trechkpt."
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "treclaim"
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+(define_expand "treclaim"
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+ [(parallel
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+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
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+ UNSPECV_HTM_TRECLAIM))
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+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[2]) = 1;
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+})
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+
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+(define_insn "*treclaim"
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[(set (match_operand:CC 1 "cc_reg_operand" "=x")
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(unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
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- UNSPECV_HTM_TRECLAIM))]
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+ UNSPECV_HTM_TRECLAIM))
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+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"treclaim. %0"
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[(set_attr "type" "htm")
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(set_attr "length" "4")])
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-(define_insn "tsr"
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+(define_expand "tsr"
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+ [(parallel
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+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
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+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
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+ UNSPECV_HTM_TSR))
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+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
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+ "TARGET_HTM"
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+{
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+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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+ MEM_VOLATILE_P (operands[2]) = 1;
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+})
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+
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+(define_insn "*tsr"
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[(set (match_operand:CC 1 "cc_reg_operand" "=x")
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(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
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- UNSPECV_HTM_TSR))]
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+ UNSPECV_HTM_TSR))
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+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
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"TARGET_HTM"
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"tsr. %0"
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[(set_attr "type" "htm")
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|
|
(set_attr "length" "4")])
|
||
|
|
|
||
|
|
-(define_insn "ttest"
|
||
|
|
+(define_expand "ttest"
|
||
|
|
+ [(parallel
|
||
|
|
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
|
||
|
|
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TTEST))
|
||
|
|
+ (set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
|
||
|
|
+ "TARGET_HTM"
|
||
|
|
+{
|
||
|
|
+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
||
|
|
+ MEM_VOLATILE_P (operands[1]) = 1;
|
||
|
|
+})
|
||
|
|
+
|
||
|
|
+(define_insn "*ttest"
|
||
|
|
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
|
||
|
|
- (unspec_volatile:CC [(const_int 0)]
|
||
|
|
- UNSPECV_HTM_TTEST))]
|
||
|
|
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TTEST))
|
||
|
|
+ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
|
||
|
|
"TARGET_HTM"
|
||
|
|
"tabortwci. 0,1,0"
|
||
|
|
[(set_attr "type" "htm")
|
||
|
|
--- gcc/config/rs6000/rs6000-c.c (revision 228826)
|
||
|
|
+++ gcc/config/rs6000/rs6000-c.c (revision 228827)
|
||
|
|
@@ -372,7 +372,11 @@ rs6000_target_modify_macros (bool define
|
||
|
|
if ((flags & OPTION_MASK_VSX) != 0)
|
||
|
|
rs6000_define_or_undefine_macro (define_p, "__VSX__");
|
||
|
|
if ((flags & OPTION_MASK_HTM) != 0)
|
||
|
|
- rs6000_define_or_undefine_macro (define_p, "__HTM__");
|
||
|
|
+ {
|
||
|
|
+ rs6000_define_or_undefine_macro (define_p, "__HTM__");
|
||
|
|
+ /* Tell the user that our HTM insn patterns act as memory barriers. */
|
||
|
|
+ rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
|
||
|
|
+ }
|
||
|
|
if ((flags & OPTION_MASK_P8_VECTOR) != 0)
|
||
|
|
rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
|
||
|
|
if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
|
||
|
|
--- gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c (revision 0)
|
||
|
|
+++ gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c (revision 226532)
|
||
|
|
@@ -0,0 +1,12 @@
|
||
|
|
+/* { dg-do compile { target { powerpc*-*-* } } } */
|
||
|
|
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||
|
|
+/* { dg-require-effective-target powerpc_htm_ok } */
|
||
|
|
+/* { dg-options "-O2 -mhtm -ffixed-r3 -ffixed-r4 -ffixed-r5 -ffixed-r6 -ffixed-r7 -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12" } */
|
||
|
|
+
|
||
|
|
+/* { dg-final { scan-assembler-not "tabort\\.\[ \t\]0" } } */
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+foo (void)
|
||
|
|
+{
|
||
|
|
+ return __builtin_tabort (10);
|
||
|
|
+}
|