229 lines
6.8 KiB
Diff
229 lines
6.8 KiB
Diff
--- ceph-15.2.4/src/yasm-wrapper.orig 2020-06-30 11:40:51.000000000 -0400
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+++ ceph-15.2.4/src/yasm-wrapper 2020-07-20 12:21:34.574980869 -0400
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@@ -1,10 +1,11 @@
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-#!/bin/sh -e
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+#!/bin/sh
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# libtool and yasm do not get along.
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# filter out any crap that libtool feeds us that yasm does not understand.
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#echo $0: got $*
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new=""
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touch=""
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+object=""
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while [ -n "$*" ]; do
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case "$1" in
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-f )
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@@ -29,6 +30,12 @@
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touch="$1"
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shift
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;;
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+ -o )
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+ shift
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+ object="$1"
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+ new="$new -o $1"
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+ shift
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+ ;;
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* )
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new="$new $1"
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shift
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@@ -36,8 +43,15 @@
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esac
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done
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-#echo $0: yasm $new
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-yasm $new
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+#echo ${0}: yasm ${new}
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+yasm ${new}
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+
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+echo ${new} | grep -- "crc32c_intel_fast*asm\.s"
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+if [ $? -ne 0 ]; then
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+ touch /tmp/${object}
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+ ld -r -z ibt -z shstk -z noexecstack -o ${object}.tmp ${object}
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+ mv ${object}.tmp ${object}
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+fi
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[ -n "$touch" ] && touch $touch
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--- ceph-15.2.2/src/common/crc32c_intel_fast_asm.s.orig 2020-05-26 08:34:32.226201974 -0400
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+++ ceph-15.2.2/src/common/crc32c_intel_fast_asm.s 2020-05-26 17:19:20.327201974 -0400
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@@ -1,5 +1,5 @@
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;
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-; Copyright 2012-2013 Intel Corporation All Rights Reserved.
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+; Copyright 2012-2015 Intel Corporation All Rights Reserved.
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; All rights reserved.
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;
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; http://opensource.org/licenses/BSD-3-Clause
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@@ -59,16 +59,34 @@
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xor rbx, rbx ;; rbx = crc1 = 0;
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xor r10, r10 ;; r10 = crc2 = 0;
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+ cmp len, %%bSize*3*2
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+ jbe %%non_prefetch
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+
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%assign i 0
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%rep %%bSize/8 - 1
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- crc32 rax, [bufptmp+i + 0*%%bSize] ;; update crc0
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- crc32 rbx, [bufptmp+i + 1*%%bSize] ;; update crc1
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- crc32 r10, [bufptmp+i + 2*%%bSize] ;; update crc2
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+ %if i < %%bSize*3/4
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+ prefetchnta [bufptmp+ %%bSize*3 + i*4]
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+ %endif
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+ crc32 rax, qword [bufptmp+i + 0*%%bSize] ;; update crc0
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+ crc32 rbx, qword [bufptmp+i + 1*%%bSize] ;; update crc1
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+ crc32 r10, qword [bufptmp+i + 2*%%bSize] ;; update crc2
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%assign i (i+8)
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%endrep
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- crc32 rax, [bufptmp+i + 0*%%bSize] ;; update crc0
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- crc32 rbx, [bufptmp+i + 1*%%bSize] ;; update crc1
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-; SKIP ;crc32 r10, [bufptmp+i + 2*%%bSize] ;; update crc2
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+ jmp %%next %+ %1
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+
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+%%non_prefetch:
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+ %assign i 0
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+ %rep %%bSize/8 - 1
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+ crc32 rax, qword [bufptmp+i + 0*%%bSize] ;; update crc0
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+ crc32 rbx, qword [bufptmp+i + 1*%%bSize] ;; update crc1
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+ crc32 r10, qword [bufptmp+i + 2*%%bSize] ;; update crc2
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+ %assign i (i+8)
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+ %endrep
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+
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+%%next %+ %1:
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+ crc32 rax, qword [bufptmp+i + 0*%%bSize] ;; update crc0
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+ crc32 rbx, qword [bufptmp+i + 1*%%bSize] ;; update crc1
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+; SKIP ;crc32 r10, qword [bufptmp+i + 2*%%bSize] ;; update crc2
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; merge in crc0
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movzx bufp_dw, al
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@@ -180,12 +198,15 @@
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%define crc_init_dw r8d
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%endif
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-
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+ endbranch
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push rdi
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push rbx
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mov rax, crc_init ;; rax = crc_init;
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+ cmp len, 8
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+ jb less_than_8
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+
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; 1) ALIGN: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -195,9 +216,6 @@
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;; amount of the address
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je proc_block ;; Skip if aligned
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- cmp len, 8
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- jb less_than_8
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-
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;;;; Calculate CRC of unaligned bytes of the buffer (if any) ;;;;
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mov rbx, [bufptmp] ;; load a quadword from the buffer
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add bufptmp, bufp ;; align buffer pointer for
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@@ -233,7 +251,7 @@
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jnc bit7 ;; jump to bit-6 if bit-7 == 0
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%assign i 0
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%rep 16
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- crc32 rax, [bufptmp+i] ;; compute crc32 of 8-byte data
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+ crc32 rax, qword [bufptmp+i] ;; compute crc32 of 8-byte data
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%assign i (i+8)
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%endrep
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je do_return ;; return if remaining data is zero
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@@ -244,7 +262,7 @@
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jnc bit6 ;; jump to bit-6 if bit-7 == 0
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%assign i 0
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%rep 8
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- crc32 rax, [bufptmp+i] ;; compute crc32 of 8-byte data
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+ crc32 rax, qword [bufptmp+i] ;; compute crc32 of 8-byte data
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%assign i (i+8)
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%endrep
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je do_return ;; return if remaining data is zero
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@@ -254,7 +272,7 @@
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jnc bit5 ;; jump to bit-5 if bit-6 == 0
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%assign i 0
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%rep 4
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- crc32 rax, [bufptmp+i] ;; compute crc32 of 8-byte data
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+ crc32 rax, qword [bufptmp+i] ;; compute crc32 of 8-byte data
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%assign i (i+8)
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%endrep
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je do_return ;; return if remaining data is zero
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@@ -264,7 +282,7 @@
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jnc bit4 ;; jump to bit-4 if bit-5 == 0
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%assign i 0
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%rep 2
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- crc32 rax, [bufptmp+i] ;; compute crc32 of 8-byte data
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+ crc32 rax, qword [bufptmp+i] ;; compute crc32 of 8-byte data
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%assign i (i+8)
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%endrep
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je do_return ;; return if remaining data is zero
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@@ -272,11 +290,11 @@
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bit4:
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shl len_b, 1 ;; shift-out MSB (bit-4)
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jnc bit3 ;; jump to bit-3 if bit-4 == 0
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- crc32 rax, [bufptmp] ;; compute crc32 of 8-byte data
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+ crc32 rax, qword [bufptmp] ;; compute crc32 of 8-byte data
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je do_return ;; return if remaining data is zero
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add bufptmp, 8 ;; buf +=8; (next 8 bytes)
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bit3:
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- mov rbx, [bufptmp] ;; load a 8-bytes from the buffer:
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+ mov rbx, qword [bufptmp] ;; load a 8-bytes from the buffer:
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shl len_b, 1 ;; shift-out MSB (bit-3)
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jnc bit2 ;; jump to bit-2 if bit-3 == 0
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crc32 eax, ebx ;; compute crc32 of 4-byte data
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--- ceph-15.2.2/src/common/crc32c_intel_fast_zero_asm.s.orig 2020-05-26 08:34:32.226201974 -0400
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+++ ceph-15.2.2/src/common/crc32c_intel_fast_zero_asm.s 2020-05-26 17:19:32.497201974 -0400
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@@ -1,5 +1,5 @@
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;
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-; Copyright 2012-2013 Intel Corporation All Rights Reserved.
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+; Copyright 2012-2015 Intel Corporation All Rights Reserved.
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; All rights reserved.
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;
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; http://opensource.org/licenses/BSD-3-Clause
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@@ -59,6 +59,19 @@
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xor rbx, rbx ;; rbx = crc1 = 0;
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xor r10, r10 ;; r10 = crc2 = 0;
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+ cmp len, %%bSize*3*2
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+ jbe %%non_prefetch
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+
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+ %assign i 0
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+ %rep %%bSize/8 - 1
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+ crc32 rax, bufptmp ;; update crc0
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+ crc32 rbx, bufptmp ;; update crc1
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+ crc32 r10, bufptmp ;; update crc2
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+ %assign i (i+8)
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+ %endrep
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+ jmp %%next %+ %1
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+
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+%%non_prefetch:
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%assign i 0
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%rep %%bSize/8 - 1
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crc32 rax, bufptmp ;; update crc0
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@@ -66,6 +79,8 @@
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crc32 r10, bufptmp ;; update crc2
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%assign i (i+8)
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%endrep
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+
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+%%next %+ %1:
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crc32 rax, bufptmp ;; update crc0
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crc32 rbx, bufptmp ;; update crc1
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; SKIP ;crc32 r10, bufptmp ;; update crc2
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@@ -180,12 +195,15 @@
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%define crc_init_dw r8d
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%endif
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-
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+ endbranch
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push rdi
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push rbx
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mov rax, crc_init ;; rax = crc_init;
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+ cmp len, 8
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+ jb less_than_8
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+
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; 1) ALIGN: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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