diff -rup binutils.orig/gas/config/tc-aarch64.c binutils-2.30/gas/config/tc-aarch64.c
--- binutils.orig/gas/config/tc-aarch64.c	2022-04-05 10:30:32.735881142 +0100
+++ binutils-2.30/gas/config/tc-aarch64.c	2022-04-05 10:31:28.198694747 +0100
@@ -8553,6 +8553,8 @@ static const struct aarch64_option_cpu_v
   {"sha3",		AARCH64_FEATURE (AARCH64_FEATURE_SHA2
 					 | AARCH64_FEATURE_SHA3, 0),
 			AARCH64_ARCH_NONE},
+  {"rng",               AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
+                        AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff -rup binutils.orig/gas/doc/c-aarch64.texi binutils-2.30/gas/doc/c-aarch64.texi
--- binutils.orig/gas/doc/c-aarch64.texi	2022-04-05 10:30:32.735881142 +0100
+++ binutils-2.30/gas/doc/c-aarch64.texi	2022-04-05 10:32:35.814423321 +0100
@@ -179,6 +179,8 @@ automatically cause those extensions to
 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
  This implies @code{fp16}.
+@item @code{rng} @tab ARMv8.5-A @tab No
+ @tab Enable ARMv8.5-A random number instructions.
 @end multitable
 
 @node AArch64 Syntax
Only in binutils-2.30/gas/testsuite/gas/aarch64: rng-1.d
Only in binutils-2.30/gas/testsuite/gas/aarch64: rng-1.s
diff -rup binutils.orig/include/opcode/aarch64.h binutils-2.30/include/opcode/aarch64.h
--- binutils.orig/include/opcode/aarch64.h	2022-04-05 10:30:33.256879707 +0100
+++ binutils-2.30/include/opcode/aarch64.h	2022-04-05 10:42:30.241087320 +0100
@@ -62,6 +62,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_COMPNUM	0x40000000	/* Complex # instructions.  */
 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
 #define AARCH64_FEATURE_F16_FML	0x1000000000ULL	/* v8.2 FP16FML ins.  */
+#define AARCH64_FEATURE_RNG     0x80000000000ULL /* Random Number instructions.  */
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
diff -rup binutils.orig/opcodes/aarch64-opc.c binutils-2.30/opcodes/aarch64-opc.c
--- binutils.orig/opcodes/aarch64-opc.c	2022-04-05 10:30:33.019880360 +0100
+++ binutils-2.30/opcodes/aarch64-opc.c	2022-04-05 10:58:07.179526356 +0100
@@ -3823,6 +3823,8 @@ const aarch64_sys_reg aarch64_sys_regs [
   { "contextidr_el1",   CPENC(3,0,C13,C0,1),	0 },
   { "contextidr_el2",	CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
   { "contextidr_el12",	CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
+  { "rndr",             CPENC(3,3,C2,C4,0),       F_ARCHEXT }, /* RO */
+  { "rndrrs",           CPENC(3,3,C2,C4,1),       F_ARCHEXT }, /* RO */
   { "tpidr_el0",        CPENC(3,3,C13,C0,2),	0 },
   { "tpidrro_el0",      CPENC(3,3,C13,C0,3),	0 }, /* RO */
   { "tpidr_el1",        CPENC(3,0,C13,C0,4),	0 },
@@ -4254,6 +4256,13 @@ aarch64_sys_reg_supported_p (const aarch
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
 
+  /* Random Number Instructions.  For now they are available
+     (and optional) only with ARMv8.5-A.  */
+  if ((   reg->value == CPENC (3, 3, C2, C4, 0)
+       || reg->value == CPENC (3, 3, C2, C4, 1))
+      && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)))
+    return FALSE;
+
   return TRUE;
 }
 
--- /dev/null	2022-04-05 09:32:54.900867346 +0100
+++ binutils-2.30/gas/testsuite/gas/aarch64/rng-1.s	2022-04-05 10:36:04.921589937 +0100
@@ -0,0 +1,3 @@
+	.arch armv8.4-a+rng
+	mrs x5, rndr
+	mrs x6, rndrrs
--- /dev/null	2022-04-05 09:32:54.900867346 +0100
+++ binutils-2.30/gas/testsuite/gas/aarch64/rng-1.d	2022-04-05 10:35:48.937653638 +0100
@@ -0,0 +1,10 @@
+#source: rng-1.s
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d53b2405 	mrs	x5, rndr
+.*:	d53b2426 	mrs	x6, rndrrs