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import CS binutils-2.35.2-67.el9

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eabdullin 2025-09-15 11:46:45 +00:00
parent 3b4d9851b5
commit 913d8c86c3
15 changed files with 7912 additions and 1 deletions
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130
SOURCES/binutils-AArch64-missing-assembler-tests-1.patch Normal file
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@ -0,0 +1,130 @@
From 7e5de6cc9202b3e60a0bec954a59e3550923d710 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:07:31 +0100
Subject: [PATCH] aarch64: Add new test addsub-carry.d
All instructions were previously untested.
---
gas/testsuite/gas/aarch64/addsub-carry.d | 53 ++++++++++++++++++++++++
gas/testsuite/gas/aarch64/addsub-carry.s | 49 ++++++++++++++++++++++
2 files changed, 102 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/addsub-carry.d
create mode 100644 gas/testsuite/gas/aarch64/addsub-carry.s
diff --git a/gas/testsuite/gas/aarch64/addsub-carry.d b/gas/testsuite/gas/aarch64/addsub-carry.d
new file mode 100644
index 00000000000..9b32d51f77d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/addsub-carry.d
@@ -0,0 +1,53 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 1a000000 adc w0, w0, w0
+ *[0-9a-f]+: 1a00001f adc wzr, w0, w0
+ *[0-9a-f]+: 1a0003e0 adc w0, wzr, w0
+ *[0-9a-f]+: 1a1f0000 adc w0, w0, wzr
+ *[0-9a-f]+: 9a000000 adc x0, x0, x0
+ *[0-9a-f]+: 9a00001f adc xzr, x0, x0
+ *[0-9a-f]+: 9a0003e0 adc x0, xzr, x0
+ *[0-9a-f]+: 9a1f0000 adc x0, x0, xzr
+ *[0-9a-f]+: 3a000000 adcs w0, w0, w0
+ *[0-9a-f]+: 3a00001f adcs wzr, w0, w0
+ *[0-9a-f]+: 3a0003e0 adcs w0, wzr, w0
+ *[0-9a-f]+: 3a1f0000 adcs w0, w0, wzr
+ *[0-9a-f]+: ba000000 adcs x0, x0, x0
+ *[0-9a-f]+: ba00001f adcs xzr, x0, x0
+ *[0-9a-f]+: ba0003e0 adcs x0, xzr, x0
+ *[0-9a-f]+: ba1f0000 adcs x0, x0, xzr
+ *[0-9a-f]+: 5a000000 sbc w0, w0, w0
+ *[0-9a-f]+: 5a00001f sbc wzr, w0, w0
+ *[0-9a-f]+: 5a0003e0 ngc w0, w0
+ *[0-9a-f]+: 5a1f0000 sbc w0, w0, wzr
+ *[0-9a-f]+: da000000 sbc x0, x0, x0
+ *[0-9a-f]+: da00001f sbc xzr, x0, x0
+ *[0-9a-f]+: da0003e0 ngc x0, x0
+ *[0-9a-f]+: da1f0000 sbc x0, x0, xzr
+ *[0-9a-f]+: 7a000000 sbcs w0, w0, w0
+ *[0-9a-f]+: 7a00001f sbcs wzr, w0, w0
+ *[0-9a-f]+: 7a0003e0 ngcs w0, w0
+ *[0-9a-f]+: 7a1f0000 sbcs w0, w0, wzr
+ *[0-9a-f]+: fa000000 sbcs x0, x0, x0
+ *[0-9a-f]+: fa00001f sbcs xzr, x0, x0
+ *[0-9a-f]+: fa0003e0 ngcs x0, x0
+ *[0-9a-f]+: fa1f0000 sbcs x0, x0, xzr
+ *[0-9a-f]+: 5a0003e0 ngc w0, w0
+ *[0-9a-f]+: 5a0003ff ngc wzr, w0
+ *[0-9a-f]+: 5a1f03e0 ngc w0, wzr
+ *[0-9a-f]+: da0003e0 ngc x0, x0
+ *[0-9a-f]+: da0003ff ngc xzr, x0
+ *[0-9a-f]+: da1f03e0 ngc x0, xzr
+ *[0-9a-f]+: 7a0003e0 ngcs w0, w0
+ *[0-9a-f]+: 7a0003ff ngcs wzr, w0
+ *[0-9a-f]+: 7a1f03e0 ngcs w0, wzr
+ *[0-9a-f]+: fa0003e0 ngcs x0, x0
+ *[0-9a-f]+: fa0003ff ngcs xzr, x0
+ *[0-9a-f]+: fa1f03e0 ngcs x0, xzr
diff --git a/gas/testsuite/gas/aarch64/addsub-carry.s b/gas/testsuite/gas/aarch64/addsub-carry.s
new file mode 100644
index 00000000000..89f2ec15fc2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/addsub-carry.s
@@ -0,0 +1,49 @@
+ adc w0, w0, w0
+ adc wzr, w0, w0
+ adc w0, wzr, w0
+ adc w0, w0, wzr
+ adc x0, x0, x0
+ adc xzr, x0, x0
+ adc x0, xzr, x0
+ adc x0, x0, xzr
+
+ adcs w0, w0, w0
+ adcs wzr, w0, w0
+ adcs w0, wzr, w0
+ adcs w0, w0, wzr
+ adcs x0, x0, x0
+ adcs xzr, x0, x0
+ adcs x0, xzr, x0
+ adcs x0, x0, xzr
+
+ sbc w0, w0, w0
+ sbc wzr, w0, w0
+ sbc w0, wzr, w0
+ sbc w0, w0, wzr
+ sbc x0, x0, x0
+ sbc xzr, x0, x0
+ sbc x0, xzr, x0
+ sbc x0, x0, xzr
+
+ sbcs w0, w0, w0
+ sbcs wzr, w0, w0
+ sbcs w0, wzr, w0
+ sbcs w0, w0, wzr
+ sbcs x0, x0, x0
+ sbcs xzr, x0, x0
+ sbcs x0, xzr, x0
+ sbcs x0, x0, xzr
+
+ ngc w0, w0
+ ngc wzr, w0
+ ngc w0, wzr
+ ngc x0, x0
+ ngc xzr, x0
+ ngc x0, xzr
+
+ ngcs w0, w0
+ ngcs wzr, w0
+ ngcs w0, wzr
+ ngcs x0, x0
+ ngcs xzr, x0
+ ngcs x0, xzr
--
2.50.1

83
SOURCES/binutils-AArch64-missing-assembler-tests-10.patch Normal file
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@ -0,0 +1,83 @@
From f495cce64504db4b66a23479022c887fa04a1242 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:12:00 +0100
Subject: [PATCH] aarch64: Add new test exception-generation.d
svc and dcps* were already tested, but are included here as part of the
same encoding group.
---
.../gas/aarch64/exception-generation.d | 28 +++++++++++++++++++
.../gas/aarch64/exception-generation.s | 26 +++++++++++++++++
2 files changed, 54 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/exception-generation.d
create mode 100644 gas/testsuite/gas/aarch64/exception-generation.s
diff --git a/gas/testsuite/gas/aarch64/exception-generation.d b/gas/testsuite/gas/aarch64/exception-generation.d
new file mode 100644
index 00000000000..e35cccd5831
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/exception-generation.d
@@ -0,0 +1,28 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: d4000001 svc #0x0
+ *[0-9a-f]+: d41fffe1 svc #0xffff
+ *[0-9a-f]+: d4000002 hvc #0x0
+ *[0-9a-f]+: d41fffe2 hvc #0xffff
+ *[0-9a-f]+: d4000003 smc #0x0
+ *[0-9a-f]+: d41fffe3 smc #0xffff
+ *[0-9a-f]+: d4200000 brk #0x0
+ *[0-9a-f]+: d43fffe0 brk #0xffff
+ *[0-9a-f]+: d4400000 hlt #0x0
+ *[0-9a-f]+: d45fffe0 hlt #0xffff
+ *[0-9a-f]+: d4a00001 dcps1
+ *[0-9a-f]+: d4a00001 dcps1
+ *[0-9a-f]+: d4bfffe1 dcps1 #0xffff
+ *[0-9a-f]+: d4a00002 dcps2
+ *[0-9a-f]+: d4a00002 dcps2
+ *[0-9a-f]+: d4bfffe2 dcps2 #0xffff
+ *[0-9a-f]+: d4a00003 dcps3
+ *[0-9a-f]+: d4a00003 dcps3
+ *[0-9a-f]+: d4bfffe3 dcps3 #0xffff
diff --git a/gas/testsuite/gas/aarch64/exception-generation.s b/gas/testsuite/gas/aarch64/exception-generation.s
new file mode 100644
index 00000000000..56294fe57cd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/exception-generation.s
@@ -0,0 +1,26 @@
+ svc #0
+ svc #65535
+
+ hvc #0
+ hvc #65535
+
+ smc #0
+ smc #65535
+
+ brk #0
+ brk #65535
+
+ hlt #0
+ hlt #65535
+
+ dcps1
+ dcps1 #0
+ dcps1 #65535
+
+ dcps2
+ dcps2 #0
+ dcps2 #65535
+
+ dcps3
+ dcps3 #0
+ dcps3 #65535
--
2.50.1

153
SOURCES/binutils-AArch64-missing-assembler-tests-11.patch Normal file
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@ -0,0 +1,153 @@
From 37c162f51a3f1399b0cd3bc2b744d41432119762 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:10:33 +0100
Subject: [PATCH] aarch64: Add new test ldst-unpriv.d
All instructions were previously untested.
---
gas/testsuite/gas/aarch64/ldst-unpriv.d | 61 +++++++++++++++++++++++
gas/testsuite/gas/aarch64/ldst-unpriv.s | 64 +++++++++++++++++++++++++
2 files changed, 125 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/ldst-unpriv.d
create mode 100644 gas/testsuite/gas/aarch64/ldst-unpriv.s
diff --git a/gas/testsuite/gas/aarch64/ldst-unpriv.d b/gas/testsuite/gas/aarch64/ldst-unpriv.d
new file mode 100644
index 00000000000..9c33678b28f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ldst-unpriv.d
@@ -0,0 +1,61 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 38000800 sttrb w0, \[x0\]
+ *[0-9a-f]+: 3800081f sttrb wzr, \[x0\]
+ *[0-9a-f]+: 38000be0 sttrb w0, \[sp\]
+ *[0-9a-f]+: 381ff800 sttrb w0, \[x0, #-1\]
+ *[0-9a-f]+: 38400800 ldtrb w0, \[x0\]
+ *[0-9a-f]+: 3840081f ldtrb wzr, \[x0\]
+ *[0-9a-f]+: 38400be0 ldtrb w0, \[sp\]
+ *[0-9a-f]+: 385ff800 ldtrb w0, \[x0, #-1\]
+ *[0-9a-f]+: 38800800 ldtrsb x0, \[x0\]
+ *[0-9a-f]+: 3880081f ldtrsb xzr, \[x0\]
+ *[0-9a-f]+: 38800be0 ldtrsb x0, \[sp\]
+ *[0-9a-f]+: 389ff800 ldtrsb x0, \[x0, #-1\]
+ *[0-9a-f]+: 38c00800 ldtrsb w0, \[x0\]
+ *[0-9a-f]+: 38c0081f ldtrsb wzr, \[x0\]
+ *[0-9a-f]+: 38c00be0 ldtrsb w0, \[sp\]
+ *[0-9a-f]+: 38dff800 ldtrsb w0, \[x0, #-1\]
+ *[0-9a-f]+: 78000800 sttrh w0, \[x0\]
+ *[0-9a-f]+: 7800081f sttrh wzr, \[x0\]
+ *[0-9a-f]+: 78000be0 sttrh w0, \[sp\]
+ *[0-9a-f]+: 781ff800 sttrh w0, \[x0, #-1\]
+ *[0-9a-f]+: 78400800 ldtrh w0, \[x0\]
+ *[0-9a-f]+: 7840081f ldtrh wzr, \[x0\]
+ *[0-9a-f]+: 78400be0 ldtrh w0, \[sp\]
+ *[0-9a-f]+: 785ff800 ldtrh w0, \[x0, #-1\]
+ *[0-9a-f]+: 78800800 ldtrsh x0, \[x0\]
+ *[0-9a-f]+: 7880081f ldtrsh xzr, \[x0\]
+ *[0-9a-f]+: 78800be0 ldtrsh x0, \[sp\]
+ *[0-9a-f]+: 789ff800 ldtrsh x0, \[x0, #-1\]
+ *[0-9a-f]+: 78c00800 ldtrsh w0, \[x0\]
+ *[0-9a-f]+: 78c0081f ldtrsh wzr, \[x0\]
+ *[0-9a-f]+: 78c00be0 ldtrsh w0, \[sp\]
+ *[0-9a-f]+: 78dff800 ldtrsh w0, \[x0, #-1\]
+ *[0-9a-f]+: b8000800 sttr w0, \[x0\]
+ *[0-9a-f]+: b800081f sttr wzr, \[x0\]
+ *[0-9a-f]+: b8000be0 sttr w0, \[sp\]
+ *[0-9a-f]+: b81ff800 sttr w0, \[x0, #-1\]
+ *[0-9a-f]+: b8400800 ldtr w0, \[x0\]
+ *[0-9a-f]+: b840081f ldtr wzr, \[x0\]
+ *[0-9a-f]+: b8400be0 ldtr w0, \[sp\]
+ *[0-9a-f]+: b85ff800 ldtr w0, \[x0, #-1\]
+ *[0-9a-f]+: b8800800 ldtrsw x0, \[x0\]
+ *[0-9a-f]+: b880081f ldtrsw xzr, \[x0\]
+ *[0-9a-f]+: b8800be0 ldtrsw x0, \[sp\]
+ *[0-9a-f]+: b89ff800 ldtrsw x0, \[x0, #-1\]
+ *[0-9a-f]+: f8000800 sttr x0, \[x0\]
+ *[0-9a-f]+: f800081f sttr xzr, \[x0\]
+ *[0-9a-f]+: f8000be0 sttr x0, \[sp\]
+ *[0-9a-f]+: f81ff800 sttr x0, \[x0, #-1\]
+ *[0-9a-f]+: f8400800 ldtr x0, \[x0\]
+ *[0-9a-f]+: f840081f ldtr xzr, \[x0\]
+ *[0-9a-f]+: f8400be0 ldtr x0, \[sp\]
+ *[0-9a-f]+: f85ff800 ldtr x0, \[x0, #-1\]
diff --git a/gas/testsuite/gas/aarch64/ldst-unpriv.s b/gas/testsuite/gas/aarch64/ldst-unpriv.s
new file mode 100644
index 00000000000..52f6461ce97
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ldst-unpriv.s
@@ -0,0 +1,64 @@
+ sttrb w0, [x0]
+ sttrb wzr, [x0, #0]
+ sttrb w0, [sp]
+ sttrb w0, [x0, #-1]
+
+ ldtrb w0, [x0]
+ ldtrb wzr, [x0, #0]
+ ldtrb w0, [sp]
+ ldtrb w0, [x0, #-1]
+
+ ldtrsb x0, [x0]
+ ldtrsb xzr, [x0, #0]
+ ldtrsb x0, [sp]
+ ldtrsb x0, [x0, #-1]
+
+ ldtrsb w0, [x0]
+ ldtrsb wzr, [x0, #0]
+ ldtrsb w0, [sp]
+ ldtrsb w0, [x0, #-1]
+
+ sttrh w0, [x0]
+ sttrh wzr, [x0, #0]
+ sttrh w0, [sp]
+ sttrh w0, [x0, #-1]
+
+ ldtrh w0, [x0]
+ ldtrh wzr, [x0, #0]
+ ldtrh w0, [sp]
+ ldtrh w0, [x0, #-1]
+
+ ldtrsh x0, [x0]
+ ldtrsh xzr, [x0, #0]
+ ldtrsh x0, [sp]
+ ldtrsh x0, [x0, #-1]
+
+ ldtrsh w0, [x0]
+ ldtrsh wzr, [x0, #0]
+ ldtrsh w0, [sp]
+ ldtrsh w0, [x0, #-1]
+
+ sttr w0, [x0]
+ sttr wzr, [x0, #0]
+ sttr w0, [sp]
+ sttr w0, [x0, #-1]
+
+ ldtr w0, [x0]
+ ldtr wzr, [x0, #0]
+ ldtr w0, [sp]
+ ldtr w0, [x0, #-1]
+
+ ldtrsw x0, [x0]
+ ldtrsw xzr, [x0, #0]
+ ldtrsw x0, [sp]
+ ldtrsw x0, [x0, #-1]
+
+ sttr x0, [x0]
+ sttr xzr, [x0, #0]
+ sttr x0, [sp]
+ sttr x0, [x0, #-1]
+
+ ldtr x0, [x0]
+ ldtr xzr, [x0, #0]
+ ldtr x0, [sp]
+ ldtr x0, [x0, #-1]
--
2.50.1

40
SOURCES/binutils-AArch64-missing-assembler-tests-12.patch Normal file
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@ -0,0 +1,40 @@
From 727964dd52f5e6d1a42cf0a12508bb0ee4e23833 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:20:44 +0100
Subject: [PATCH] aarch64: Add tests for csdb and eret to system.d
---
--- binutils-2.35.2.orig/gas/testsuite/gas/aarch64/system.s 2025-07-22 08:52:03.803039248 +0100
+++ binutils-2.35.2/gas/testsuite/gas/aarch64/system.s 2025-07-22 09:07:13.082237231 +0100
@@ -1,5 +1,6 @@
.text
drps
+ eret
//
// HINTS
@@ -11,6 +12,7 @@
wfi
sev
sevl
+ csdb
.macro all_hints from=0, to=127
hint \from
--- binutils-2.35.2.orig/gas/testsuite/gas/aarch64/system.d 2025-07-22 08:52:03.809039283 +0100
+++ binutils-2.35.2/gas/testsuite/gas/aarch64/system.d 2025-07-22 09:07:49.780518903 +0100
@@ -6,12 +6,14 @@ Disassembly of section \.text:
0+ <.*>:
.*: d6bf03e0 drps
+.*: d69f03e0 eret
.*: d503201f nop
.*: d503203f yield
.*: d503205f wfe
.*: d503207f wfi
.*: d503209f sev
.*: d50320bf sevl
+.*: d503229f csdb
.*: d503201f nop
.*: d503203f yield
.*: d503205f wfe

390
SOURCES/binutils-AArch64-missing-assembler-tests-2.patch Normal file
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@ -0,0 +1,390 @@
From 6fb41cbeebaf0e36affb0037c182edf938aae0d3 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:02:01 +0100
Subject: [PATCH] aarch64: Add new test advsimd-copy.d
Only smov and the second dup variant were previously untested. However,
the only test for umov was a disassembly test with -M no-aliases, and
the first dup variant was only tested in assembly in diagnostic.d with
the non-architectural syntax `dup v0.2d, v1.2d[0]`.
---
gas/testsuite/gas/aarch64/advsimd-copy.d | 178 ++++++++++++++++++++++
gas/testsuite/gas/aarch64/advsimd-copy.s | 181 +++++++++++++++++++++++
2 files changed, 359 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/advsimd-copy.d
create mode 100644 gas/testsuite/gas/aarch64/advsimd-copy.s
diff --git a/gas/testsuite/gas/aarch64/advsimd-copy.d b/gas/testsuite/gas/aarch64/advsimd-copy.d
new file mode 100644
index 00000000000..59ade08186d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-copy.d
@@ -0,0 +1,178 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0e010400 dup v0\.8b, v0\.b\[0\]
+ *[0-9a-f]+: 0e01041f dup v31\.8b, v0\.b\[0\]
+ *[0-9a-f]+: 0e0107e0 dup v0\.8b, v31\.b\[0\]
+ *[0-9a-f]+: 0e1f0400 dup v0\.8b, v0\.b\[15\]
+ *[0-9a-f]+: 0e020400 dup v0\.4h, v0\.h\[0\]
+ *[0-9a-f]+: 0e02041f dup v31\.4h, v0\.h\[0\]
+ *[0-9a-f]+: 0e0207e0 dup v0\.4h, v31\.h\[0\]
+ *[0-9a-f]+: 0e1e0400 dup v0\.4h, v0\.h\[7\]
+ *[0-9a-f]+: 0e040400 dup v0\.2s, v0\.s\[0\]
+ *[0-9a-f]+: 0e04041f dup v31\.2s, v0\.s\[0\]
+ *[0-9a-f]+: 0e0407e0 dup v0\.2s, v31\.s\[0\]
+ *[0-9a-f]+: 0e1c0400 dup v0\.2s, v0\.s\[3\]
+ *[0-9a-f]+: 4e010400 dup v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 4e01041f dup v31\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 4e0107e0 dup v0\.16b, v31\.b\[0\]
+ *[0-9a-f]+: 4e1f0400 dup v0\.16b, v0\.b\[15\]
+ *[0-9a-f]+: 4e020400 dup v0\.8h, v0\.h\[0\]
+ *[0-9a-f]+: 4e02041f dup v31\.8h, v0\.h\[0\]
+ *[0-9a-f]+: 4e0207e0 dup v0\.8h, v31\.h\[0\]
+ *[0-9a-f]+: 4e1e0400 dup v0\.8h, v0\.h\[7\]
+ *[0-9a-f]+: 4e040400 dup v0\.4s, v0\.s\[0\]
+ *[0-9a-f]+: 4e04041f dup v31\.4s, v0\.s\[0\]
+ *[0-9a-f]+: 4e0407e0 dup v0\.4s, v31\.s\[0\]
+ *[0-9a-f]+: 4e1c0400 dup v0\.4s, v0\.s\[3\]
+ *[0-9a-f]+: 4e080400 dup v0\.2d, v0\.d\[0\]
+ *[0-9a-f]+: 4e08041f dup v31\.2d, v0\.d\[0\]
+ *[0-9a-f]+: 4e0807e0 dup v0\.2d, v31\.d\[0\]
+ *[0-9a-f]+: 4e180400 dup v0.2d, v0.d\[1\]
+ *[0-9a-f]+: 0e010c00 dup v0\.8b, w0
+ *[0-9a-f]+: 0e010c1f dup v31\.8b, w0
+ *[0-9a-f]+: 0e010fe0 dup v0\.8b, wzr
+ *[0-9a-f]+: 0e020c00 dup v0\.4h, w0
+ *[0-9a-f]+: 0e020c1f dup v31\.4h, w0
+ *[0-9a-f]+: 0e020fe0 dup v0\.4h, wzr
+ *[0-9a-f]+: 0e040c00 dup v0\.2s, w0
+ *[0-9a-f]+: 0e040c1f dup v31\.2s, w0
+ *[0-9a-f]+: 0e040fe0 dup v0\.2s, wzr
+ *[0-9a-f]+: 4e010c00 dup v0\.16b, w0
+ *[0-9a-f]+: 4e010c1f dup v31\.16b, w0
+ *[0-9a-f]+: 4e010fe0 dup v0\.16b, wzr
+ *[0-9a-f]+: 4e020c00 dup v0\.8h, w0
+ *[0-9a-f]+: 4e020c1f dup v31\.8h, w0
+ *[0-9a-f]+: 4e020fe0 dup v0\.8h, wzr
+ *[0-9a-f]+: 4e040c00 dup v0\.4s, w0
+ *[0-9a-f]+: 4e040c1f dup v31\.4s, w0
+ *[0-9a-f]+: 4e040fe0 dup v0\.4s, wzr
+ *[0-9a-f]+: 4e080c00 dup v0\.2d, x0
+ *[0-9a-f]+: 4e080c1f dup v31\.2d, x0
+ *[0-9a-f]+: 4e080fe0 dup v0\.2d, xzr
+ *[0-9a-f]+: 0e150c00 dup v0\.8b, w0
+ *[0-9a-f]+: 4e180c00 dup v0\.2d, x0
+ *[0-9a-f]+: 0e012c00 smov w0, v0\.b\[0\]
+ *[0-9a-f]+: 0e012c1f smov wzr, v0\.b\[0\]
+ *[0-9a-f]+: 0e012fe0 smov w0, v31\.b\[0\]
+ *[0-9a-f]+: 0e1f2c00 smov w0, v0\.b\[15\]
+ *[0-9a-f]+: 0e022c00 smov w0, v0\.h\[0\]
+ *[0-9a-f]+: 0e022c1f smov wzr, v0\.h\[0\]
+ *[0-9a-f]+: 0e022fe0 smov w0, v31\.h\[0\]
+ *[0-9a-f]+: 0e1e2c00 smov w0, v0\.h\[7\]
+ *[0-9a-f]+: 4e012c00 smov x0, v0\.b\[0\]
+ *[0-9a-f]+: 4e012c1f smov xzr, v0\.b\[0\]
+ *[0-9a-f]+: 4e012fe0 smov x0, v31\.b\[0\]
+ *[0-9a-f]+: 4e1f2c00 smov x0, v0\.b\[15\]
+ *[0-9a-f]+: 4e022c00 smov x0, v0\.h\[0\]
+ *[0-9a-f]+: 4e022c1f smov xzr, v0\.h\[0\]
+ *[0-9a-f]+: 4e022fe0 smov x0, v31\.h\[0\]
+ *[0-9a-f]+: 4e1e2c00 smov x0, v0\.h\[7\]
+ *[0-9a-f]+: 4e042c00 smov x0, v0\.s\[0\]
+ *[0-9a-f]+: 4e042c1f smov xzr, v0\.s\[0\]
+ *[0-9a-f]+: 4e042fe0 smov x0, v31\.s\[0\]
+ *[0-9a-f]+: 4e1c2c00 smov x0, v0\.s\[3\]
+ *[0-9a-f]+: 0e013c00 umov w0, v0\.b\[0\]
+ *[0-9a-f]+: 0e013c1f umov wzr, v0\.b\[0\]
+ *[0-9a-f]+: 0e013fe0 umov w0, v31\.b\[0\]
+ *[0-9a-f]+: 0e1f3c00 umov w0, v0\.b\[15\]
+ *[0-9a-f]+: 0e023c00 umov w0, v0\.h\[0\]
+ *[0-9a-f]+: 0e023c1f umov wzr, v0\.h\[0\]
+ *[0-9a-f]+: 0e023fe0 umov w0, v31\.h\[0\]
+ *[0-9a-f]+: 0e1e3c00 umov w0, v0\.h\[7\]
+ *[0-9a-f]+: 0e043c00 mov w0, v0\.s\[0\]
+ *[0-9a-f]+: 0e043c1f mov wzr, v0\.s\[0\]
+ *[0-9a-f]+: 0e043fe0 mov w0, v31\.s\[0\]
+ *[0-9a-f]+: 0e1c3c00 mov w0, v0\.s\[3\]
+ *[0-9a-f]+: 4e083c00 mov x0, v0\.d\[0\]
+ *[0-9a-f]+: 4e083c1f mov xzr, v0\.d\[0\]
+ *[0-9a-f]+: 4e083fe0 mov x0, v31\.d\[0\]
+ *[0-9a-f]+: 4e183c00 mov x0, v0\.d\[1\]
+ *[0-9a-f]+: 0e043c00 mov w0, v0\.s\[0\]
+ *[0-9a-f]+: 0e043c1f mov wzr, v0\.s\[0\]
+ *[0-9a-f]+: 0e043fe0 mov w0, v31\.s\[0\]
+ *[0-9a-f]+: 0e1c3c00 mov w0, v0\.s\[3\]
+ *[0-9a-f]+: 4e083c00 mov x0, v0\.d\[0\]
+ *[0-9a-f]+: 4e083c1f mov xzr, v0\.d\[0\]
+ *[0-9a-f]+: 4e083fe0 mov x0, v31\.d\[0\]
+ *[0-9a-f]+: 4e183c00 mov x0, v0\.d\[1\]
+ *[0-9a-f]+: 4e011c00 mov v0\.b\[0\], w0
+ *[0-9a-f]+: 4e011c1f mov v31\.b\[0\], w0
+ *[0-9a-f]+: 4e011fe0 mov v0\.b\[0\], wzr
+ *[0-9a-f]+: 4e1f1c00 mov v0\.b\[15\], w0
+ *[0-9a-f]+: 4e021c00 mov v0\.h\[0\], w0
+ *[0-9a-f]+: 4e021c1f mov v31\.h\[0\], w0
+ *[0-9a-f]+: 4e021fe0 mov v0\.h\[0\], wzr
+ *[0-9a-f]+: 4e1e1c00 mov v0\.h\[7\], w0
+ *[0-9a-f]+: 4e041c00 mov v0\.s\[0\], w0
+ *[0-9a-f]+: 4e041c1f mov v31\.s\[0\], w0
+ *[0-9a-f]+: 4e041fe0 mov v0\.s\[0\], wzr
+ *[0-9a-f]+: 4e1c1c00 mov v0\.s\[3\], w0
+ *[0-9a-f]+: 4e081c00 mov v0\.d\[0\], x0
+ *[0-9a-f]+: 4e081c1f mov v31\.d\[0\], x0
+ *[0-9a-f]+: 4e081fe0 mov v0\.d\[0\], xzr
+ *[0-9a-f]+: 4e181c00 mov v0\.d\[1\], x0
+ *[0-9a-f]+: 4e011c00 mov v0\.b\[0\], w0
+ *[0-9a-f]+: 4e011c1f mov v31\.b\[0\], w0
+ *[0-9a-f]+: 4e011fe0 mov v0\.b\[0\], wzr
+ *[0-9a-f]+: 4e1f1c00 mov v0\.b\[15\], w0
+ *[0-9a-f]+: 4e021c00 mov v0\.h\[0\], w0
+ *[0-9a-f]+: 4e021c1f mov v31\.h\[0\], w0
+ *[0-9a-f]+: 4e021fe0 mov v0\.h\[0\], wzr
+ *[0-9a-f]+: 4e1e1c00 mov v0\.h\[7\], w0
+ *[0-9a-f]+: 4e041c00 mov v0\.s\[0\], w0
+ *[0-9a-f]+: 4e041c1f mov v31\.s\[0\], w0
+ *[0-9a-f]+: 4e041fe0 mov v0\.s\[0\], wzr
+ *[0-9a-f]+: 4e1c1c00 mov v0\.s\[3\], w0
+ *[0-9a-f]+: 4e081c00 mov v0\.d\[0\], x0
+ *[0-9a-f]+: 4e081c1f mov v31\.d\[0\], x0
+ *[0-9a-f]+: 4e081fe0 mov v0\.d\[0\], xzr
+ *[0-9a-f]+: 4e181c00 mov v0\.d\[1\], x0
+ *[0-9a-f]+: 6e010400 mov v0\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+: 6e01041f mov v31\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+: 6e0107e0 mov v0\.b\[0\], v31\.b\[0\]
+ *[0-9a-f]+: 6e1f0400 mov v0\.b\[15\], v0\.b\[0\]
+ *[0-9a-f]+: 6e017c00 mov v0\.b\[0\], v0\.b\[15\]
+ *[0-9a-f]+: 6e020400 mov v0\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+: 6e02041f mov v31\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+: 6e0207e0 mov v0\.h\[0\], v31\.h\[0\]
+ *[0-9a-f]+: 6e1e0400 mov v0\.h\[7\], v0\.h\[0\]
+ *[0-9a-f]+: 6e027400 mov v0\.h\[0\], v0\.h\[7\]
+ *[0-9a-f]+: 6e040400 mov v0\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+: 6e04041f mov v31\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+: 6e0407e0 mov v0\.s\[0\], v31\.s\[0\]
+ *[0-9a-f]+: 6e1c0400 mov v0\.s\[3\], v0\.s\[0\]
+ *[0-9a-f]+: 6e046400 mov v0\.s\[0\], v0\.s\[3\]
+ *[0-9a-f]+: 6e080400 mov v0\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+: 6e08041f mov v31\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+: 6e0807e0 mov v0\.d\[0\], v31\.d\[0\]
+ *[0-9a-f]+: 6e180400 mov v0\.d\[1\], v0\.d\[0\]
+ *[0-9a-f]+: 6e084400 mov v0\.d\[0\], v0\.d\[1\]
+ *[0-9a-f]+: 6e022c00 mov v0\.h\[0\], v0\.h\[2\]
+ *[0-9a-f]+: 6e083c00 mov v0\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+: 6e010400 mov v0\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+: 6e01041f mov v31\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+: 6e0107e0 mov v0\.b\[0\], v31\.b\[0\]
+ *[0-9a-f]+: 6e1f0400 mov v0\.b\[15\], v0\.b\[0\]
+ *[0-9a-f]+: 6e017c00 mov v0\.b\[0\], v0\.b\[15\]
+ *[0-9a-f]+: 6e020400 mov v0\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+: 6e02041f mov v31\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+: 6e0207e0 mov v0\.h\[0\], v31\.h\[0\]
+ *[0-9a-f]+: 6e1e0400 mov v0\.h\[7\], v0\.h\[0\]
+ *[0-9a-f]+: 6e027400 mov v0\.h\[0\], v0\.h\[7\]
+ *[0-9a-f]+: 6e040400 mov v0\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+: 6e04041f mov v31\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+: 6e0407e0 mov v0\.s\[0\], v31\.s\[0\]
+ *[0-9a-f]+: 6e1c0400 mov v0\.s\[3\], v0\.s\[0\]
+ *[0-9a-f]+: 6e046400 mov v0\.s\[0\], v0\.s\[3\]
+ *[0-9a-f]+: 6e080400 mov v0\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+: 6e08041f mov v31\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+: 6e0807e0 mov v0\.d\[0\], v31\.d\[0\]
+ *[0-9a-f]+: 6e180400 mov v0\.d\[1\], v0\.d\[0\]
+ *[0-9a-f]+: 6e084400 mov v0\.d\[0\], v0\.d\[1\]
diff --git a/gas/testsuite/gas/aarch64/advsimd-copy.s b/gas/testsuite/gas/aarch64/advsimd-copy.s
new file mode 100644
index 00000000000..d0618948686
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-copy.s
@@ -0,0 +1,181 @@
+ dup v0.8b, v0.b[0]
+ dup v31.8b, v0.b[0]
+ dup v0.8b, v31.b[0]
+ dup v0.8b, v0.b[15]
+ dup v0.4h, v0.h[0]
+ dup v31.4h, v0.h[0]
+ dup v0.4h, v31.h[0]
+ dup v0.4h, v0.h[7]
+ dup v0.2s, v0.s[0]
+ dup v31.2s, v0.s[0]
+ dup v0.2s, v31.s[0]
+ dup v0.2s, v0.s[3]
+ dup v0.16b, v0.b[0]
+ dup v31.16b, v0.b[0]
+ dup v0.16b, v31.b[0]
+ dup v0.16b, v0.b[15]
+ dup v0.8h, v0.h[0]
+ dup v31.8h, v0.h[0]
+ dup v0.8h, v31.h[0]
+ dup v0.8h, v0.h[7]
+ dup v0.4s, v0.s[0]
+ dup v31.4s, v0.s[0]
+ dup v0.4s, v31.s[0]
+ dup v0.4s, v0.s[3]
+ dup v0.2d, v0.d[0]
+ dup v31.2d, v0.d[0]
+ dup v0.2d, v31.d[0]
+ dup v0.2d, v0.d[1]
+
+ dup v0.8b, w0
+ dup v31.8b, w0
+ dup v0.8b, wzr
+ dup v0.4h, w0
+ dup v31.4h, w0
+ dup v0.4h, wzr
+ dup v0.2s, w0
+ dup v31.2s, w0
+ dup v0.2s, wzr
+ dup v0.16b, w0
+ dup v31.16b, w0
+ dup v0.16b, wzr
+ dup v0.8h, w0
+ dup v31.8h, w0
+ dup v0.8h, wzr
+ dup v0.4s, w0
+ dup v31.4s, w0
+ dup v0.4s, wzr
+ dup v0.2d, x0
+ dup v31.2d, x0
+ dup v0.2d, xzr
+// Unspecified bits in imm5 (20..16) are ignored but should be set to zero by
+// an assembler. This tests disassembly when the ignored bits are nonzero.
+ .inst 0x0e150c00
+ .inst 0x4e180c00
+
+ smov w0, v0.b[0]
+ smov wzr, v0.b[0]
+ smov w0, v31.b[0]
+ smov w0, v0.b[15]
+ smov w0, v0.h[0]
+ smov wzr, v0.h[0]
+ smov w0, v31.h[0]
+ smov w0, v0.h[7]
+ smov x0, v0.b[0]
+ smov xzr, v0.b[0]
+ smov x0, v31.b[0]
+ smov x0, v0.b[15]
+ smov x0, v0.h[0]
+ smov xzr, v0.h[0]
+ smov x0, v31.h[0]
+ smov x0, v0.h[7]
+ smov x0, v0.s[0]
+ smov xzr, v0.s[0]
+ smov x0, v31.s[0]
+ smov x0, v0.s[3]
+
+ umov w0, v0.b[0]
+ umov wzr, v0.b[0]
+ umov w0, v31.b[0]
+ umov w0, v0.b[15]
+ umov w0, v0.h[0]
+ umov wzr, v0.h[0]
+ umov w0, v31.h[0]
+ umov w0, v0.h[7]
+ umov w0, v0.s[0]
+ umov wzr, v0.s[0]
+ umov w0, v31.s[0]
+ umov w0, v0.s[3]
+ umov x0, v0.d[0]
+ umov xzr, v0.d[0]
+ umov x0, v31.d[0]
+ umov x0, v0.d[1]
+
+ mov w0, v0.s[0]
+ mov wzr, v0.s[0]
+ mov w0, v31.s[0]
+ mov w0, v0.s[3]
+ mov x0, v0.d[0]
+ mov xzr, v0.d[0]
+ mov x0, v31.d[0]
+ mov x0, v0.d[1]
+
+ ins v0.b[0], w0
+ ins v31.b[0], w0
+ ins v0.b[0], wzr
+ ins v0.b[15], w0
+ ins v0.h[0], w0
+ ins v31.h[0], w0
+ ins v0.h[0], wzr
+ ins v0.h[7], w0
+ ins v0.s[0], w0
+ ins v31.s[0], w0
+ ins v0.s[0], wzr
+ ins v0.s[3], w0
+ ins v0.d[0], x0
+ ins v31.d[0], x0
+ ins v0.d[0], xzr
+ ins v0.d[1], x0
+
+ mov v0.b[0], w0
+ mov v31.b[0], w0
+ mov v0.b[0], wzr
+ mov v0.b[15], w0
+ mov v0.h[0], w0
+ mov v31.h[0], w0
+ mov v0.h[0], wzr
+ mov v0.h[7], w0
+ mov v0.s[0], w0
+ mov v31.s[0], w0
+ mov v0.s[0], wzr
+ mov v0.s[3], w0
+ mov v0.d[0], x0
+ mov v31.d[0], x0
+ mov v0.d[0], xzr
+ mov v0.d[1], x0
+
+ ins v0.b[0], v0.b[0]
+ ins v31.b[0], v0.b[0]
+ ins v0.b[0], v31.b[0]
+ ins v0.b[15], v0.b[0]
+ ins v0.b[0], v0.b[15]
+ ins v0.h[0], v0.h[0]
+ ins v31.h[0], v0.h[0]
+ ins v0.h[0], v31.h[0]
+ ins v0.h[7], v0.h[0]
+ ins v0.h[0], v0.h[7]
+ ins v0.s[0], v0.s[0]
+ ins v31.s[0], v0.s[0]
+ ins v0.s[0], v31.s[0]
+ ins v0.s[3], v0.s[0]
+ ins v0.s[0], v0.s[3]
+ ins v0.d[0], v0.d[0]
+ ins v31.d[0], v0.d[0]
+ ins v0.d[0], v31.d[0]
+ ins v0.d[1], v0.d[0]
+ ins v0.d[0], v0.d[1]
+// Unspecified bits in imm4 (14..11) are ignored but should be set to zero by
+// an assembler. This tests disassembly when the ignored bits are nonzero.
+ .inst 0x6e022c00
+ .inst 0x6e083c00
+
+ mov v0.b[0], v0.b[0]
+ mov v31.b[0], v0.b[0]
+ mov v0.b[0], v31.b[0]
+ mov v0.b[15], v0.b[0]
+ mov v0.b[0], v0.b[15]
+ mov v0.h[0], v0.h[0]
+ mov v31.h[0], v0.h[0]
+ mov v0.h[0], v31.h[0]
+ mov v0.h[7], v0.h[0]
+ mov v0.h[0], v0.h[7]
+ mov v0.s[0], v0.s[0]
+ mov v31.s[0], v0.s[0]
+ mov v0.s[0], v31.s[0]
+ mov v0.s[3], v0.s[0]
+ mov v0.s[0], v0.s[3]
+ mov v0.d[0], v0.d[0]
+ mov v31.d[0], v0.d[0]
+ mov v0.d[0], v31.d[0]
+ mov v0.d[1], v0.d[0]
+ mov v0.d[0], v0.d[1]
--
2.50.1

384
SOURCES/binutils-AArch64-missing-assembler-tests-3.patch Normal file
View File

@ -0,0 +1,384 @@
From c9b4c146368433f0bbdf4d6b3517e3b5f79d2bb4 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:03:39 +0100
Subject: [PATCH] aarch64: Add new test advsimd-scalar-shift-immediate.d
All instructions were previously untested.
---
.../aarch64/advsimd-scalar-shift-immediate.d | 173 +++++++++++++++++
.../aarch64/advsimd-scalar-shift-immediate.s | 183 ++++++++++++++++++
2 files changed, 356 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.d
create mode 100644 gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.s
diff --git a/gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.d b/gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.d
new file mode 100644
index 00000000000..8a511fccc71
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.d
@@ -0,0 +1,173 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 5f400400 sshr d0, d0, #64
+ *[0-9a-f]+: 5f40041f sshr d31, d0, #64
+ *[0-9a-f]+: 5f4007e0 sshr d0, d31, #64
+ *[0-9a-f]+: 5f7f0400 sshr d0, d0, #1
+ *[0-9a-f]+: 5f401400 ssra d0, d0, #64
+ *[0-9a-f]+: 5f40141f ssra d31, d0, #64
+ *[0-9a-f]+: 5f4017e0 ssra d0, d31, #64
+ *[0-9a-f]+: 5f7f1400 ssra d0, d0, #1
+ *[0-9a-f]+: 5f402400 srshr d0, d0, #64
+ *[0-9a-f]+: 5f40241f srshr d31, d0, #64
+ *[0-9a-f]+: 5f4027e0 srshr d0, d31, #64
+ *[0-9a-f]+: 5f7f2400 srshr d0, d0, #1
+ *[0-9a-f]+: 5f403400 srsra d0, d0, #64
+ *[0-9a-f]+: 5f40341f srsra d31, d0, #64
+ *[0-9a-f]+: 5f4037e0 srsra d0, d31, #64
+ *[0-9a-f]+: 5f7f3400 srsra d0, d0, #1
+ *[0-9a-f]+: 5f405400 shl d0, d0, #0
+ *[0-9a-f]+: 5f40541f shl d31, d0, #0
+ *[0-9a-f]+: 5f4057e0 shl d0, d31, #0
+ *[0-9a-f]+: 5f7f5400 shl d0, d0, #63
+ *[0-9a-f]+: 5f087400 sqshl b0, b0, #0
+ *[0-9a-f]+: 5f08741f sqshl b31, b0, #0
+ *[0-9a-f]+: 5f0877e0 sqshl b0, b31, #0
+ *[0-9a-f]+: 5f0f7400 sqshl b0, b0, #7
+ *[0-9a-f]+: 5f107400 sqshl h0, h0, #0
+ *[0-9a-f]+: 5f10741f sqshl h31, h0, #0
+ *[0-9a-f]+: 5f1077e0 sqshl h0, h31, #0
+ *[0-9a-f]+: 5f1f7400 sqshl h0, h0, #15
+ *[0-9a-f]+: 5f207400 sqshl s0, s0, #0
+ *[0-9a-f]+: 5f20741f sqshl s31, s0, #0
+ *[0-9a-f]+: 5f2077e0 sqshl s0, s31, #0
+ *[0-9a-f]+: 5f3f7400 sqshl s0, s0, #31
+ *[0-9a-f]+: 5f407400 sqshl d0, d0, #0
+ *[0-9a-f]+: 5f40741f sqshl d31, d0, #0
+ *[0-9a-f]+: 5f4077e0 sqshl d0, d31, #0
+ *[0-9a-f]+: 5f7f7400 sqshl d0, d0, #63
+ *[0-9a-f]+: 5f089400 sqshrn b0, h0, #8
+ *[0-9a-f]+: 5f08941f sqshrn b31, h0, #8
+ *[0-9a-f]+: 5f0897e0 sqshrn b0, h31, #8
+ *[0-9a-f]+: 5f0f9400 sqshrn b0, h0, #1
+ *[0-9a-f]+: 5f109400 sqshrn h0, s0, #16
+ *[0-9a-f]+: 5f10941f sqshrn h31, s0, #16
+ *[0-9a-f]+: 5f1097e0 sqshrn h0, s31, #16
+ *[0-9a-f]+: 5f1f9400 sqshrn h0, s0, #1
+ *[0-9a-f]+: 5f209400 sqshrn s0, d0, #32
+ *[0-9a-f]+: 5f20941f sqshrn s31, d0, #32
+ *[0-9a-f]+: 5f2097e0 sqshrn s0, d31, #32
+ *[0-9a-f]+: 5f3f9400 sqshrn s0, d0, #1
+ *[0-9a-f]+: 5f089c00 sqrshrn b0, h0, #8
+ *[0-9a-f]+: 5f089c1f sqrshrn b31, h0, #8
+ *[0-9a-f]+: 5f089fe0 sqrshrn b0, h31, #8
+ *[0-9a-f]+: 5f0f9c00 sqrshrn b0, h0, #1
+ *[0-9a-f]+: 5f109c00 sqrshrn h0, s0, #16
+ *[0-9a-f]+: 5f109c1f sqrshrn h31, s0, #16
+ *[0-9a-f]+: 5f109fe0 sqrshrn h0, s31, #16
+ *[0-9a-f]+: 5f1f9c00 sqrshrn h0, s0, #1
+ *[0-9a-f]+: 5f209c00 sqrshrn s0, d0, #32
+ *[0-9a-f]+: 5f209c1f sqrshrn s31, d0, #32
+ *[0-9a-f]+: 5f209fe0 sqrshrn s0, d31, #32
+ *[0-9a-f]+: 5f3f9c00 sqrshrn s0, d0, #1
+ *[0-9a-f]+: 7f400400 ushr d0, d0, #64
+ *[0-9a-f]+: 7f40041f ushr d31, d0, #64
+ *[0-9a-f]+: 7f4007e0 ushr d0, d31, #64
+ *[0-9a-f]+: 7f7f0400 ushr d0, d0, #1
+ *[0-9a-f]+: 7f401400 usra d0, d0, #64
+ *[0-9a-f]+: 7f40141f usra d31, d0, #64
+ *[0-9a-f]+: 7f4017e0 usra d0, d31, #64
+ *[0-9a-f]+: 7f7f1400 usra d0, d0, #1
+ *[0-9a-f]+: 7f402400 urshr d0, d0, #64
+ *[0-9a-f]+: 7f40241f urshr d31, d0, #64
+ *[0-9a-f]+: 7f4027e0 urshr d0, d31, #64
+ *[0-9a-f]+: 7f7f2400 urshr d0, d0, #1
+ *[0-9a-f]+: 7f403400 ursra d0, d0, #64
+ *[0-9a-f]+: 7f40341f ursra d31, d0, #64
+ *[0-9a-f]+: 7f4037e0 ursra d0, d31, #64
+ *[0-9a-f]+: 7f7f3400 ursra d0, d0, #1
+ *[0-9a-f]+: 7f404400 sri d0, d0, #64
+ *[0-9a-f]+: 7f40441f sri d31, d0, #64
+ *[0-9a-f]+: 7f4047e0 sri d0, d31, #64
+ *[0-9a-f]+: 7f7f4400 sri d0, d0, #1
+ *[0-9a-f]+: 7f405400 sli d0, d0, #0
+ *[0-9a-f]+: 7f40541f sli d31, d0, #0
+ *[0-9a-f]+: 7f4057e0 sli d0, d31, #0
+ *[0-9a-f]+: 7f7f5400 sli d0, d0, #63
+ *[0-9a-f]+: 7f086400 sqshlu b0, b0, #0
+ *[0-9a-f]+: 7f08641f sqshlu b31, b0, #0
+ *[0-9a-f]+: 7f0867e0 sqshlu b0, b31, #0
+ *[0-9a-f]+: 7f0f6400 sqshlu b0, b0, #7
+ *[0-9a-f]+: 7f106400 sqshlu h0, h0, #0
+ *[0-9a-f]+: 7f10641f sqshlu h31, h0, #0
+ *[0-9a-f]+: 7f1067e0 sqshlu h0, h31, #0
+ *[0-9a-f]+: 7f1f6400 sqshlu h0, h0, #15
+ *[0-9a-f]+: 7f206400 sqshlu s0, s0, #0
+ *[0-9a-f]+: 7f20641f sqshlu s31, s0, #0
+ *[0-9a-f]+: 7f2067e0 sqshlu s0, s31, #0
+ *[0-9a-f]+: 7f3f6400 sqshlu s0, s0, #31
+ *[0-9a-f]+: 7f406400 sqshlu d0, d0, #0
+ *[0-9a-f]+: 7f40641f sqshlu d31, d0, #0
+ *[0-9a-f]+: 7f4067e0 sqshlu d0, d31, #0
+ *[0-9a-f]+: 7f7f6400 sqshlu d0, d0, #63
+ *[0-9a-f]+: 7f087400 uqshl b0, b0, #0
+ *[0-9a-f]+: 7f08741f uqshl b31, b0, #0
+ *[0-9a-f]+: 7f0877e0 uqshl b0, b31, #0
+ *[0-9a-f]+: 7f0f7400 uqshl b0, b0, #7
+ *[0-9a-f]+: 7f107400 uqshl h0, h0, #0
+ *[0-9a-f]+: 7f10741f uqshl h31, h0, #0
+ *[0-9a-f]+: 7f1077e0 uqshl h0, h31, #0
+ *[0-9a-f]+: 7f1f7400 uqshl h0, h0, #15
+ *[0-9a-f]+: 7f207400 uqshl s0, s0, #0
+ *[0-9a-f]+: 7f20741f uqshl s31, s0, #0
+ *[0-9a-f]+: 7f2077e0 uqshl s0, s31, #0
+ *[0-9a-f]+: 7f3f7400 uqshl s0, s0, #31
+ *[0-9a-f]+: 7f407400 uqshl d0, d0, #0
+ *[0-9a-f]+: 7f40741f uqshl d31, d0, #0
+ *[0-9a-f]+: 7f4077e0 uqshl d0, d31, #0
+ *[0-9a-f]+: 7f7f7400 uqshl d0, d0, #63
+ *[0-9a-f]+: 7f088400 sqshrun b0, h0, #8
+ *[0-9a-f]+: 7f08841f sqshrun b31, h0, #8
+ *[0-9a-f]+: 7f0887e0 sqshrun b0, h31, #8
+ *[0-9a-f]+: 7f0f8400 sqshrun b0, h0, #1
+ *[0-9a-f]+: 7f108400 sqshrun h0, s0, #16
+ *[0-9a-f]+: 7f10841f sqshrun h31, s0, #16
+ *[0-9a-f]+: 7f1087e0 sqshrun h0, s31, #16
+ *[0-9a-f]+: 7f1f8400 sqshrun h0, s0, #1
+ *[0-9a-f]+: 7f208400 sqshrun s0, d0, #32
+ *[0-9a-f]+: 7f20841f sqshrun s31, d0, #32
+ *[0-9a-f]+: 7f2087e0 sqshrun s0, d31, #32
+ *[0-9a-f]+: 7f3f8400 sqshrun s0, d0, #1
+ *[0-9a-f]+: 7f088c00 sqrshrun b0, h0, #8
+ *[0-9a-f]+: 7f088c1f sqrshrun b31, h0, #8
+ *[0-9a-f]+: 7f088fe0 sqrshrun b0, h31, #8
+ *[0-9a-f]+: 7f0f8c00 sqrshrun b0, h0, #1
+ *[0-9a-f]+: 7f108c00 sqrshrun h0, s0, #16
+ *[0-9a-f]+: 7f108c1f sqrshrun h31, s0, #16
+ *[0-9a-f]+: 7f108fe0 sqrshrun h0, s31, #16
+ *[0-9a-f]+: 7f1f8c00 sqrshrun h0, s0, #1
+ *[0-9a-f]+: 7f208c00 sqrshrun s0, d0, #32
+ *[0-9a-f]+: 7f208c1f sqrshrun s31, d0, #32
+ *[0-9a-f]+: 7f208fe0 sqrshrun s0, d31, #32
+ *[0-9a-f]+: 7f3f8c00 sqrshrun s0, d0, #1
+ *[0-9a-f]+: 7f089400 uqshrn b0, h0, #8
+ *[0-9a-f]+: 7f08941f uqshrn b31, h0, #8
+ *[0-9a-f]+: 7f0897e0 uqshrn b0, h31, #8
+ *[0-9a-f]+: 7f0f9400 uqshrn b0, h0, #1
+ *[0-9a-f]+: 7f109400 uqshrn h0, s0, #16
+ *[0-9a-f]+: 7f10941f uqshrn h31, s0, #16
+ *[0-9a-f]+: 7f1097e0 uqshrn h0, s31, #16
+ *[0-9a-f]+: 7f1f9400 uqshrn h0, s0, #1
+ *[0-9a-f]+: 7f209400 uqshrn s0, d0, #32
+ *[0-9a-f]+: 7f20941f uqshrn s31, d0, #32
+ *[0-9a-f]+: 7f2097e0 uqshrn s0, d31, #32
+ *[0-9a-f]+: 7f3f9400 uqshrn s0, d0, #1
+ *[0-9a-f]+: 7f089c00 uqrshrn b0, h0, #8
+ *[0-9a-f]+: 7f089c1f uqrshrn b31, h0, #8
+ *[0-9a-f]+: 7f089fe0 uqrshrn b0, h31, #8
+ *[0-9a-f]+: 7f0f9c00 uqrshrn b0, h0, #1
+ *[0-9a-f]+: 7f109c00 uqrshrn h0, s0, #16
+ *[0-9a-f]+: 7f109c1f uqrshrn h31, s0, #16
+ *[0-9a-f]+: 7f109fe0 uqrshrn h0, s31, #16
+ *[0-9a-f]+: 7f1f9c00 uqrshrn h0, s0, #1
+ *[0-9a-f]+: 7f209c00 uqrshrn s0, d0, #32
+ *[0-9a-f]+: 7f209c1f uqrshrn s31, d0, #32
+ *[0-9a-f]+: 7f209fe0 uqrshrn s0, d31, #32
+ *[0-9a-f]+: 7f3f9c00 uqrshrn s0, d0, #1
diff --git a/gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.s b/gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.s
new file mode 100644
index 00000000000..bddc9cb2a1a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-scalar-shift-immediate.s
@@ -0,0 +1,183 @@
+ sshr d0, d0, #64
+ sshr d31, d0, #64
+ sshr d0, d31, #64
+ sshr d0, d0, #1
+
+ ssra d0, d0, #64
+ ssra d31, d0, #64
+ ssra d0, d31, #64
+ ssra d0, d0, #1
+
+ srshr d0, d0, #64
+ srshr d31, d0, #64
+ srshr d0, d31, #64
+ srshr d0, d0, #1
+
+ srsra d0, d0, #64
+ srsra d31, d0, #64
+ srsra d0, d31, #64
+ srsra d0, d0, #1
+
+ shl d0, d0, #0
+ shl d31, d0, #0
+ shl d0, d31, #0
+ shl d0, d0, #63
+
+ sqshl b0, b0, #0
+ sqshl b31, b0, #0
+ sqshl b0, b31, #0
+ sqshl b0, b0, #7
+ sqshl h0, h0, #0
+ sqshl h31, h0, #0
+ sqshl h0, h31, #0
+ sqshl h0, h0, #15
+ sqshl s0, s0, #0
+ sqshl s31, s0, #0
+ sqshl s0, s31, #0
+ sqshl s0, s0, #31
+ sqshl d0, d0, #0
+ sqshl d31, d0, #0
+ sqshl d0, d31, #0
+ sqshl d0, d0, #63
+
+ sqshrn b0, h0, #8
+ sqshrn b31, h0, #8
+ sqshrn b0, h31, #8
+ sqshrn b0, h0, #1
+ sqshrn h0, s0, #16
+ sqshrn h31, s0, #16
+ sqshrn h0, s31, #16
+ sqshrn h0, s0, #1
+ sqshrn s0, d0, #32
+ sqshrn s31, d0, #32
+ sqshrn s0, d31, #32
+ sqshrn s0, d0, #1
+
+ sqrshrn b0, h0, #8
+ sqrshrn b31, h0, #8
+ sqrshrn b0, h31, #8
+ sqrshrn b0, h0, #1
+ sqrshrn h0, s0, #16
+ sqrshrn h31, s0, #16
+ sqrshrn h0, s31, #16
+ sqrshrn h0, s0, #1
+ sqrshrn s0, d0, #32
+ sqrshrn s31, d0, #32
+ sqrshrn s0, d31, #32
+ sqrshrn s0, d0, #1
+
+ ushr d0, d0, #64
+ ushr d31, d0, #64
+ ushr d0, d31, #64
+ ushr d0, d0, #1
+
+ usra d0, d0, #64
+ usra d31, d0, #64
+ usra d0, d31, #64
+ usra d0, d0, #1
+
+ urshr d0, d0, #64
+ urshr d31, d0, #64
+ urshr d0, d31, #64
+ urshr d0, d0, #1
+
+ ursra d0, d0, #64
+ ursra d31, d0, #64
+ ursra d0, d31, #64
+ ursra d0, d0, #1
+
+ sri d0, d0, #64
+ sri d31, d0, #64
+ sri d0, d31, #64
+ sri d0, d0, #1
+
+ sli d0, d0, #0
+ sli d31, d0, #0
+ sli d0, d31, #0
+ sli d0, d0, #63
+
+ sqshlu b0, b0, #0
+ sqshlu b31, b0, #0
+ sqshlu b0, b31, #0
+ sqshlu b0, b0, #7
+ sqshlu h0, h0, #0
+ sqshlu h31, h0, #0
+ sqshlu h0, h31, #0
+ sqshlu h0, h0, #15
+ sqshlu s0, s0, #0
+ sqshlu s31, s0, #0
+ sqshlu s0, s31, #0
+ sqshlu s0, s0, #31
+ sqshlu d0, d0, #0
+ sqshlu d31, d0, #0
+ sqshlu d0, d31, #0
+ sqshlu d0, d0, #63
+
+ uqshl b0, b0, #0
+ uqshl b31, b0, #0
+ uqshl b0, b31, #0
+ uqshl b0, b0, #7
+ uqshl h0, h0, #0
+ uqshl h31, h0, #0
+ uqshl h0, h31, #0
+ uqshl h0, h0, #15
+ uqshl s0, s0, #0
+ uqshl s31, s0, #0
+ uqshl s0, s31, #0
+ uqshl s0, s0, #31
+ uqshl d0, d0, #0
+ uqshl d31, d0, #0
+ uqshl d0, d31, #0
+ uqshl d0, d0, #63
+
+ sqshrun b0, h0, #8
+ sqshrun b31, h0, #8
+ sqshrun b0, h31, #8
+ sqshrun b0, h0, #1
+ sqshrun h0, s0, #16
+ sqshrun h31, s0, #16
+ sqshrun h0, s31, #16
+ sqshrun h0, s0, #1
+ sqshrun s0, d0, #32
+ sqshrun s31, d0, #32
+ sqshrun s0, d31, #32
+ sqshrun s0, d0, #1
+
+ sqrshrun b0, h0, #8
+ sqrshrun b31, h0, #8
+ sqrshrun b0, h31, #8
+ sqrshrun b0, h0, #1
+ sqrshrun h0, s0, #16
+ sqrshrun h31, s0, #16
+ sqrshrun h0, s31, #16
+ sqrshrun h0, s0, #1
+ sqrshrun s0, d0, #32
+ sqrshrun s31, d0, #32
+ sqrshrun s0, d31, #32
+ sqrshrun s0, d0, #1
+
+ uqshrn b0, h0, #8
+ uqshrn b31, h0, #8
+ uqshrn b0, h31, #8
+ uqshrn b0, h0, #1
+ uqshrn h0, s0, #16
+ uqshrn h31, s0, #16
+ uqshrn h0, s31, #16
+ uqshrn h0, s0, #1
+ uqshrn s0, d0, #32
+ uqshrn s31, d0, #32
+ uqshrn s0, d31, #32
+ uqshrn s0, d0, #1
+
+ uqrshrn b0, h0, #8
+ uqrshrn b31, h0, #8
+ uqrshrn b0, h31, #8
+ uqrshrn b0, h0, #1
+ uqrshrn h0, s0, #16
+ uqrshrn h31, s0, #16
+ uqrshrn h0, s31, #16
+ uqrshrn h0, s0, #1
+ uqrshrn s0, d0, #32
+ uqrshrn s31, d0, #32
+ uqrshrn s0, d31, #32
+ uqrshrn s0, d0, #1
--
2.50.1

2481
SOURCES/binutils-AArch64-missing-assembler-tests-4.patch Normal file
View File

File diff suppressed because it is too large Load Diff

1498
SOURCES/binutils-AArch64-missing-assembler-tests-5.patch Normal file
View File

File diff suppressed because it is too large Load Diff

860
SOURCES/binutils-AArch64-missing-assembler-tests-6.patch Normal file
View File

@ -0,0 +1,860 @@
From 1bd53f5409d1deb0427b7bd6549a1dde874ff96e Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 22:57:53 +0100
Subject: [PATCH] aarch64: Add new test advsimd-two-reg-misc.d
sqabs, abs, not, mvn, sqneg and neg were already tested, and cmeq was
already assembled in an error test (sve-reg-diagnostic.d), but they are
all included here as part of the same encoding group.
---
.../gas/aarch64/advsimd-two-reg-misc.d | 408 +++++++++++++++++
.../gas/aarch64/advsimd-two-reg-misc.s | 422 ++++++++++++++++++
2 files changed, 830 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/advsimd-two-reg-misc.d
create mode 100644 gas/testsuite/gas/aarch64/advsimd-two-reg-misc.s
diff --git a/gas/testsuite/gas/aarch64/advsimd-two-reg-misc.d b/gas/testsuite/gas/aarch64/advsimd-two-reg-misc.d
new file mode 100644
index 00000000000..cf9d93c34b1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-two-reg-misc.d
@@ -0,0 +1,408 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0e200800 rev64 v0\.8b, v0\.8b
+ *[0-9a-f]+: 0e20081f rev64 v31\.8b, v0\.8b
+ *[0-9a-f]+: 0e200be0 rev64 v0\.8b, v31\.8b
+ *[0-9a-f]+: 0e600800 rev64 v0\.4h, v0\.4h
+ *[0-9a-f]+: 0e60081f rev64 v31\.4h, v0\.4h
+ *[0-9a-f]+: 0e600be0 rev64 v0\.4h, v31\.4h
+ *[0-9a-f]+: 0ea00800 rev64 v0\.2s, v0\.2s
+ *[0-9a-f]+: 0ea0081f rev64 v31\.2s, v0\.2s
+ *[0-9a-f]+: 0ea00be0 rev64 v0\.2s, v31\.2s
+ *[0-9a-f]+: 4e200800 rev64 v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e20081f rev64 v31\.16b, v0\.16b
+ *[0-9a-f]+: 4e200be0 rev64 v0\.16b, v31\.16b
+ *[0-9a-f]+: 4e600800 rev64 v0\.8h, v0\.8h
+ *[0-9a-f]+: 4e60081f rev64 v31\.8h, v0\.8h
+ *[0-9a-f]+: 4e600be0 rev64 v0\.8h, v31\.8h
+ *[0-9a-f]+: 4ea00800 rev64 v0\.4s, v0\.4s
+ *[0-9a-f]+: 4ea0081f rev64 v31\.4s, v0\.4s
+ *[0-9a-f]+: 4ea00be0 rev64 v0\.4s, v31\.4s
+ *[0-9a-f]+: 0e201800 rev16 v0\.8b, v0\.8b
+ *[0-9a-f]+: 0e20181f rev16 v31\.8b, v0\.8b
+ *[0-9a-f]+: 0e201be0 rev16 v0\.8b, v31\.8b
+ *[0-9a-f]+: 4e201800 rev16 v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e20181f rev16 v31\.16b, v0\.16b
+ *[0-9a-f]+: 4e201be0 rev16 v0\.16b, v31\.16b
+ *[0-9a-f]+: 0e202800 saddlp v0\.4h, v0\.8b
+ *[0-9a-f]+: 0e20281f saddlp v31\.4h, v0\.8b
+ *[0-9a-f]+: 0e202be0 saddlp v0\.4h, v31\.8b
+ *[0-9a-f]+: 0e602800 saddlp v0\.2s, v0\.4h
+ *[0-9a-f]+: 0e60281f saddlp v31\.2s, v0\.4h
+ *[0-9a-f]+: 0e602be0 saddlp v0\.2s, v31\.4h
+ *[0-9a-f]+: 0ea02800 saddlp v0\.1d, v0\.2s
+ *[0-9a-f]+: 0ea0281f saddlp v31\.1d, v0\.2s
+ *[0-9a-f]+: 0ea02be0 saddlp v0\.1d, v31\.2s
+ *[0-9a-f]+: 4e202800 saddlp v0\.8h, v0\.16b
+ *[0-9a-f]+: 4e20281f saddlp v31\.8h, v0\.16b
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+ *[0-9a-f]+: 6e605be0 rbit v0\.16b, v31\.16b
+ *[0-9a-f]+: 2e206800 uadalp v0\.4h, v0\.8b
+ *[0-9a-f]+: 2e20681f uadalp v31\.4h, v0\.8b
+ *[0-9a-f]+: 2e206be0 uadalp v0\.4h, v31\.8b
+ *[0-9a-f]+: 2e606800 uadalp v0\.2s, v0\.4h
+ *[0-9a-f]+: 2e60681f uadalp v31\.2s, v0\.4h
+ *[0-9a-f]+: 2e606be0 uadalp v0\.2s, v31\.4h
+ *[0-9a-f]+: 2ea06800 uadalp v0\.1d, v0\.2s
+ *[0-9a-f]+: 2ea0681f uadalp v31\.1d, v0\.2s
+ *[0-9a-f]+: 2ea06be0 uadalp v0\.1d, v31\.2s
+ *[0-9a-f]+: 6e206800 uadalp v0\.8h, v0\.16b
+ *[0-9a-f]+: 6e20681f uadalp v31\.8h, v0\.16b
+ *[0-9a-f]+: 6e206be0 uadalp v0\.8h, v31\.16b
+ *[0-9a-f]+: 6e606800 uadalp v0\.4s, v0\.8h
+ *[0-9a-f]+: 6e60681f uadalp v31\.4s, v0\.8h
+ *[0-9a-f]+: 6e606be0 uadalp v0\.4s, v31\.8h
+ *[0-9a-f]+: 6ea06800 uadalp v0\.2d, v0\.4s
+ *[0-9a-f]+: 6ea0681f uadalp v31\.2d, v0\.4s
+ *[0-9a-f]+: 6ea06be0 uadalp v0\.2d, v31\.4s
+ *[0-9a-f]+: 2e207800 sqneg v0\.8b, v0\.8b
+ *[0-9a-f]+: 2e20781f sqneg v31\.8b, v0\.8b
+ *[0-9a-f]+: 2e207be0 sqneg v0\.8b, v31\.8b
+ *[0-9a-f]+: 2e607800 sqneg v0\.4h, v0\.4h
+ *[0-9a-f]+: 2e60781f sqneg v31\.4h, v0\.4h
+ *[0-9a-f]+: 2e607be0 sqneg v0\.4h, v31\.4h
+ *[0-9a-f]+: 2ea07800 sqneg v0\.2s, v0\.2s
+ *[0-9a-f]+: 2ea0781f sqneg v31\.2s, v0\.2s
+ *[0-9a-f]+: 2ea07be0 sqneg v0\.2s, v31\.2s
+ *[0-9a-f]+: 6e207800 sqneg v0\.16b, v0\.16b
+ *[0-9a-f]+: 6e20781f sqneg v31\.16b, v0\.16b
+ *[0-9a-f]+: 6e207be0 sqneg v0\.16b, v31\.16b
+ *[0-9a-f]+: 6e607800 sqneg v0\.8h, v0\.8h
+ *[0-9a-f]+: 6e60781f sqneg v31\.8h, v0\.8h
+ *[0-9a-f]+: 6e607be0 sqneg v0\.8h, v31\.8h
+ *[0-9a-f]+: 6ea07800 sqneg v0\.4s, v0\.4s
+ *[0-9a-f]+: 6ea0781f sqneg v31\.4s, v0\.4s
+ *[0-9a-f]+: 6ea07be0 sqneg v0\.4s, v31\.4s
+ *[0-9a-f]+: 6ee07800 sqneg v0\.2d, v0\.2d
+ *[0-9a-f]+: 6ee0781f sqneg v31\.2d, v0\.2d
+ *[0-9a-f]+: 6ee07be0 sqneg v0\.2d, v31\.2d
+ *[0-9a-f]+: 2e208800 cmge v0\.8b, v0\.8b, #0
+ *[0-9a-f]+: 2e20881f cmge v31\.8b, v0\.8b, #0
+ *[0-9a-f]+: 2e208be0 cmge v0\.8b, v31\.8b, #0
+ *[0-9a-f]+: 2e608800 cmge v0\.4h, v0\.4h, #0
+ *[0-9a-f]+: 2e60881f cmge v31\.4h, v0\.4h, #0
+ *[0-9a-f]+: 2e608be0 cmge v0\.4h, v31\.4h, #0
+ *[0-9a-f]+: 2ea08800 cmge v0\.2s, v0\.2s, #0
+ *[0-9a-f]+: 2ea0881f cmge v31\.2s, v0\.2s, #0
+ *[0-9a-f]+: 2ea08be0 cmge v0\.2s, v31\.2s, #0
+ *[0-9a-f]+: 6e208800 cmge v0\.16b, v0\.16b, #0
+ *[0-9a-f]+: 6e20881f cmge v31\.16b, v0\.16b, #0
+ *[0-9a-f]+: 6e208be0 cmge v0\.16b, v31\.16b, #0
+ *[0-9a-f]+: 6e608800 cmge v0\.8h, v0\.8h, #0
+ *[0-9a-f]+: 6e60881f cmge v31\.8h, v0\.8h, #0
+ *[0-9a-f]+: 6e608be0 cmge v0\.8h, v31\.8h, #0
+ *[0-9a-f]+: 6ea08800 cmge v0\.4s, v0\.4s, #0
+ *[0-9a-f]+: 6ea0881f cmge v31\.4s, v0\.4s, #0
+ *[0-9a-f]+: 6ea08be0 cmge v0\.4s, v31\.4s, #0
+ *[0-9a-f]+: 6ee08800 cmge v0\.2d, v0\.2d, #0
+ *[0-9a-f]+: 6ee0881f cmge v31\.2d, v0\.2d, #0
+ *[0-9a-f]+: 6ee08be0 cmge v0\.2d, v31\.2d, #0
+ *[0-9a-f]+: 2e209800 cmle v0\.8b, v0\.8b, #0
+ *[0-9a-f]+: 2e20981f cmle v31\.8b, v0\.8b, #0
+ *[0-9a-f]+: 2e209be0 cmle v0\.8b, v31\.8b, #0
+ *[0-9a-f]+: 2e609800 cmle v0\.4h, v0\.4h, #0
+ *[0-9a-f]+: 2e60981f cmle v31\.4h, v0\.4h, #0
+ *[0-9a-f]+: 2e609be0 cmle v0\.4h, v31\.4h, #0
+ *[0-9a-f]+: 2ea09800 cmle v0\.2s, v0\.2s, #0
+ *[0-9a-f]+: 2ea0981f cmle v31\.2s, v0\.2s, #0
+ *[0-9a-f]+: 2ea09be0 cmle v0\.2s, v31\.2s, #0
+ *[0-9a-f]+: 6e209800 cmle v0\.16b, v0\.16b, #0
+ *[0-9a-f]+: 6e20981f cmle v31\.16b, v0\.16b, #0
+ *[0-9a-f]+: 6e209be0 cmle v0\.16b, v31\.16b, #0
+ *[0-9a-f]+: 6e609800 cmle v0\.8h, v0\.8h, #0
+ *[0-9a-f]+: 6e60981f cmle v31\.8h, v0\.8h, #0
+ *[0-9a-f]+: 6e609be0 cmle v0\.8h, v31\.8h, #0
+ *[0-9a-f]+: 6ea09800 cmle v0\.4s, v0\.4s, #0
+ *[0-9a-f]+: 6ea0981f cmle v31\.4s, v0\.4s, #0
+ *[0-9a-f]+: 6ea09be0 cmle v0\.4s, v31\.4s, #0
+ *[0-9a-f]+: 6ee09800 cmle v0\.2d, v0\.2d, #0
+ *[0-9a-f]+: 6ee0981f cmle v31\.2d, v0\.2d, #0
+ *[0-9a-f]+: 6ee09be0 cmle v0\.2d, v31\.2d, #0
+ *[0-9a-f]+: 2e20b800 neg v0\.8b, v0\.8b
+ *[0-9a-f]+: 2e20b81f neg v31\.8b, v0\.8b
+ *[0-9a-f]+: 2e20bbe0 neg v0\.8b, v31\.8b
+ *[0-9a-f]+: 2e60b800 neg v0\.4h, v0\.4h
+ *[0-9a-f]+: 2e60b81f neg v31\.4h, v0\.4h
+ *[0-9a-f]+: 2e60bbe0 neg v0\.4h, v31\.4h
+ *[0-9a-f]+: 2ea0b800 neg v0\.2s, v0\.2s
+ *[0-9a-f]+: 2ea0b81f neg v31\.2s, v0\.2s
+ *[0-9a-f]+: 2ea0bbe0 neg v0\.2s, v31\.2s
+ *[0-9a-f]+: 6e20b800 neg v0\.16b, v0\.16b
+ *[0-9a-f]+: 6e20b81f neg v31\.16b, v0\.16b
+ *[0-9a-f]+: 6e20bbe0 neg v0\.16b, v31\.16b
+ *[0-9a-f]+: 6e60b800 neg v0\.8h, v0\.8h
+ *[0-9a-f]+: 6e60b81f neg v31\.8h, v0\.8h
+ *[0-9a-f]+: 6e60bbe0 neg v0\.8h, v31\.8h
+ *[0-9a-f]+: 6ea0b800 neg v0\.4s, v0\.4s
+ *[0-9a-f]+: 6ea0b81f neg v31\.4s, v0\.4s
+ *[0-9a-f]+: 6ea0bbe0 neg v0\.4s, v31\.4s
+ *[0-9a-f]+: 6ee0b800 neg v0\.2d, v0\.2d
+ *[0-9a-f]+: 6ee0b81f neg v31\.2d, v0\.2d
+ *[0-9a-f]+: 6ee0bbe0 neg v0\.2d, v31\.2d
diff --git a/gas/testsuite/gas/aarch64/advsimd-two-reg-misc.s b/gas/testsuite/gas/aarch64/advsimd-two-reg-misc.s
new file mode 100644
index 00000000000..6a66ff7acc0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-two-reg-misc.s
@@ -0,0 +1,422 @@
+ rev64 v0.8b, v0.8b
+ rev64 v31.8b, v0.8b
+ rev64 v0.8b, v31.8b
+ rev64 v0.4h, v0.4h
+ rev64 v31.4h, v0.4h
+ rev64 v0.4h, v31.4h
+ rev64 v0.2s, v0.2s
+ rev64 v31.2s, v0.2s
+ rev64 v0.2s, v31.2s
+ rev64 v0.16b, v0.16b
+ rev64 v31.16b, v0.16b
+ rev64 v0.16b, v31.16b
+ rev64 v0.8h, v0.8h
+ rev64 v31.8h, v0.8h
+ rev64 v0.8h, v31.8h
+ rev64 v0.4s, v0.4s
+ rev64 v31.4s, v0.4s
+ rev64 v0.4s, v31.4s
+
+ rev16 v0.8b, v0.8b
+ rev16 v31.8b, v0.8b
+ rev16 v0.8b, v31.8b
+ rev16 v0.16b, v0.16b
+ rev16 v31.16b, v0.16b
+ rev16 v0.16b, v31.16b
+
+ saddlp v0.4h, v0.8b
+ saddlp v31.4h, v0.8b
+ saddlp v0.4h, v31.8b
+ saddlp v0.2s, v0.4h
+ saddlp v31.2s, v0.4h
+ saddlp v0.2s, v31.4h
+ saddlp v0.1d, v0.2s
+ saddlp v31.1d, v0.2s
+ saddlp v0.1d, v31.2s
+ saddlp v0.8h, v0.16b
+ saddlp v31.8h, v0.16b
+ saddlp v0.8h, v31.16b
+ saddlp v0.4s, v0.8h
+ saddlp v31.4s, v0.8h
+ saddlp v0.4s, v31.8h
+ saddlp v0.2d, v0.4s
+ saddlp v31.2d, v0.4s
+ saddlp v0.2d, v31.4s
+
+ suqadd v0.8b, v0.8b
+ suqadd v31.8b, v0.8b
+ suqadd v0.8b, v31.8b
+ suqadd v0.4h, v0.4h
+ suqadd v31.4h, v0.4h
+ suqadd v0.4h, v31.4h
+ suqadd v0.2s, v0.2s
+ suqadd v31.2s, v0.2s
+ suqadd v0.2s, v31.2s
+ suqadd v0.16b, v0.16b
+ suqadd v31.16b, v0.16b
+ suqadd v0.16b, v31.16b
+ suqadd v0.8h, v0.8h
+ suqadd v31.8h, v0.8h
+ suqadd v0.8h, v31.8h
+ suqadd v0.4s, v0.4s
+ suqadd v31.4s, v0.4s
+ suqadd v0.4s, v31.4s
+ suqadd v0.2d, v0.2d
+ suqadd v31.2d, v0.2d
+ suqadd v0.2d, v31.2d
+
+ cls v0.8b, v0.8b
+ cls v31.8b, v0.8b
+ cls v0.8b, v31.8b
+ cls v0.4h, v0.4h
+ cls v31.4h, v0.4h
+ cls v0.4h, v31.4h
+ cls v0.2s, v0.2s
+ cls v31.2s, v0.2s
+ cls v0.2s, v31.2s
+ cls v0.16b, v0.16b
+ cls v31.16b, v0.16b
+ cls v0.16b, v31.16b
+ cls v0.8h, v0.8h
+ cls v31.8h, v0.8h
+ cls v0.8h, v31.8h
+ cls v0.4s, v0.4s
+ cls v31.4s, v0.4s
+ cls v0.4s, v31.4s
+
+ cnt v0.8b, v0.8b
+ cnt v31.8b, v0.8b
+ cnt v0.8b, v31.8b
+ cnt v0.16b, v0.16b
+ cnt v31.16b, v0.16b
+ cnt v0.16b, v31.16b
+
+ sadalp v0.4h, v0.8b
+ sadalp v31.4h, v0.8b
+ sadalp v0.4h, v31.8b
+ sadalp v0.2s, v0.4h
+ sadalp v31.2s, v0.4h
+ sadalp v0.2s, v31.4h
+ sadalp v0.1d, v0.2s
+ sadalp v31.1d, v0.2s
+ sadalp v0.1d, v31.2s
+ sadalp v0.8h, v0.16b
+ sadalp v31.8h, v0.16b
+ sadalp v0.8h, v31.16b
+ sadalp v0.4s, v0.8h
+ sadalp v31.4s, v0.8h
+ sadalp v0.4s, v31.8h
+ sadalp v0.2d, v0.4s
+ sadalp v31.2d, v0.4s
+ sadalp v0.2d, v31.4s
+
+ sqabs v0.8b, v0.8b
+ sqabs v31.8b, v0.8b
+ sqabs v0.8b, v31.8b
+ sqabs v0.4h, v0.4h
+ sqabs v31.4h, v0.4h
+ sqabs v0.4h, v31.4h
+ sqabs v0.2s, v0.2s
+ sqabs v31.2s, v0.2s
+ sqabs v0.2s, v31.2s
+ sqabs v0.16b, v0.16b
+ sqabs v31.16b, v0.16b
+ sqabs v0.16b, v31.16b
+ sqabs v0.8h, v0.8h
+ sqabs v31.8h, v0.8h
+ sqabs v0.8h, v31.8h
+ sqabs v0.4s, v0.4s
+ sqabs v31.4s, v0.4s
+ sqabs v0.4s, v31.4s
+ sqabs v0.2d, v0.2d
+ sqabs v31.2d, v0.2d
+ sqabs v0.2d, v31.2d
+
+ cmgt v0.8b, v0.8b, #0
+ cmgt v31.8b, v0.8b, #0
+ cmgt v0.8b, v31.8b, #0
+ cmgt v0.4h, v0.4h, #0
+ cmgt v31.4h, v0.4h, #0
+ cmgt v0.4h, v31.4h, #0
+ cmgt v0.2s, v0.2s, #0
+ cmgt v31.2s, v0.2s, #0
+ cmgt v0.2s, v31.2s, #0
+ cmgt v0.16b, v0.16b, #0
+ cmgt v31.16b, v0.16b, #0
+ cmgt v0.16b, v31.16b, #0
+ cmgt v0.8h, v0.8h, #0
+ cmgt v31.8h, v0.8h, #0
+ cmgt v0.8h, v31.8h, #0
+ cmgt v0.4s, v0.4s, #0
+ cmgt v31.4s, v0.4s, #0
+ cmgt v0.4s, v31.4s, #0
+ cmgt v0.2d, v0.2d, #0
+ cmgt v31.2d, v0.2d, #0
+ cmgt v0.2d, v31.2d, #0
+
+ cmeq v0.8b, v0.8b, #0
+ cmeq v31.8b, v0.8b, #0
+ cmeq v0.8b, v31.8b, #0
+ cmeq v0.4h, v0.4h, #0
+ cmeq v31.4h, v0.4h, #0
+ cmeq v0.4h, v31.4h, #0
+ cmeq v0.2s, v0.2s, #0
+ cmeq v31.2s, v0.2s, #0
+ cmeq v0.2s, v31.2s, #0
+ cmeq v0.16b, v0.16b, #0
+ cmeq v31.16b, v0.16b, #0
+ cmeq v0.16b, v31.16b, #0
+ cmeq v0.8h, v0.8h, #0
+ cmeq v31.8h, v0.8h, #0
+ cmeq v0.8h, v31.8h, #0
+ cmeq v0.4s, v0.4s, #0
+ cmeq v31.4s, v0.4s, #0
+ cmeq v0.4s, v31.4s, #0
+ cmeq v0.2d, v0.2d, #0
+ cmeq v31.2d, v0.2d, #0
+ cmeq v0.2d, v31.2d, #0
+
+ cmlt v0.8b, v0.8b, #0
+ cmlt v31.8b, v0.8b, #0
+ cmlt v0.8b, v31.8b, #0
+ cmlt v0.4h, v0.4h, #0
+ cmlt v31.4h, v0.4h, #0
+ cmlt v0.4h, v31.4h, #0
+ cmlt v0.2s, v0.2s, #0
+ cmlt v31.2s, v0.2s, #0
+ cmlt v0.2s, v31.2s, #0
+ cmlt v0.16b, v0.16b, #0
+ cmlt v31.16b, v0.16b, #0
+ cmlt v0.16b, v31.16b, #0
+ cmlt v0.8h, v0.8h, #0
+ cmlt v31.8h, v0.8h, #0
+ cmlt v0.8h, v31.8h, #0
+ cmlt v0.4s, v0.4s, #0
+ cmlt v31.4s, v0.4s, #0
+ cmlt v0.4s, v31.4s, #0
+ cmlt v0.2d, v0.2d, #0
+ cmlt v31.2d, v0.2d, #0
+ cmlt v0.2d, v31.2d, #0
+
+ abs v0.8b, v0.8b
+ abs v31.8b, v0.8b
+ abs v0.8b, v31.8b
+ abs v0.4h, v0.4h
+ abs v31.4h, v0.4h
+ abs v0.4h, v31.4h
+ abs v0.2s, v0.2s
+ abs v31.2s, v0.2s
+ abs v0.2s, v31.2s
+ abs v0.16b, v0.16b
+ abs v31.16b, v0.16b
+ abs v0.16b, v31.16b
+ abs v0.8h, v0.8h
+ abs v31.8h, v0.8h
+ abs v0.8h, v31.8h
+ abs v0.4s, v0.4s
+ abs v31.4s, v0.4s
+ abs v0.4s, v31.4s
+ abs v0.2d, v0.2d
+ abs v31.2d, v0.2d
+ abs v0.2d, v31.2d
+
+ rev32 v0.8b, v0.8b
+ rev32 v31.8b, v0.8b
+ rev32 v0.8b, v31.8b
+ rev32 v0.4h, v0.4h
+ rev32 v31.4h, v0.4h
+ rev32 v0.4h, v31.4h
+ rev32 v0.16b, v0.16b
+ rev32 v31.16b, v0.16b
+ rev32 v0.16b, v31.16b
+ rev32 v0.8h, v0.8h
+ rev32 v31.8h, v0.8h
+ rev32 v0.8h, v31.8h
+
+ uaddlp v0.4h, v0.8b
+ uaddlp v31.4h, v0.8b
+ uaddlp v0.4h, v31.8b
+ uaddlp v0.2s, v0.4h
+ uaddlp v31.2s, v0.4h
+ uaddlp v0.2s, v31.4h
+ uaddlp v0.1d, v0.2s
+ uaddlp v31.1d, v0.2s
+ uaddlp v0.1d, v31.2s
+ uaddlp v0.8h, v0.16b
+ uaddlp v31.8h, v0.16b
+ uaddlp v0.8h, v31.16b
+ uaddlp v0.4s, v0.8h
+ uaddlp v31.4s, v0.8h
+ uaddlp v0.4s, v31.8h
+ uaddlp v0.2d, v0.4s
+ uaddlp v31.2d, v0.4s
+ uaddlp v0.2d, v31.4s
+
+ usqadd v0.8b, v0.8b
+ usqadd v31.8b, v0.8b
+ usqadd v0.8b, v31.8b
+ usqadd v0.4h, v0.4h
+ usqadd v31.4h, v0.4h
+ usqadd v0.4h, v31.4h
+ usqadd v0.2s, v0.2s
+ usqadd v31.2s, v0.2s
+ usqadd v0.2s, v31.2s
+ usqadd v0.16b, v0.16b
+ usqadd v31.16b, v0.16b
+ usqadd v0.16b, v31.16b
+ usqadd v0.8h, v0.8h
+ usqadd v31.8h, v0.8h
+ usqadd v0.8h, v31.8h
+ usqadd v0.4s, v0.4s
+ usqadd v31.4s, v0.4s
+ usqadd v0.4s, v31.4s
+ usqadd v0.2d, v0.2d
+ usqadd v31.2d, v0.2d
+ usqadd v0.2d, v31.2d
+
+ clz v0.8b, v0.8b
+ clz v31.8b, v0.8b
+ clz v0.8b, v31.8b
+ clz v0.4h, v0.4h
+ clz v31.4h, v0.4h
+ clz v0.4h, v31.4h
+ clz v0.2s, v0.2s
+ clz v31.2s, v0.2s
+ clz v0.2s, v31.2s
+ clz v0.16b, v0.16b
+ clz v31.16b, v0.16b
+ clz v0.16b, v31.16b
+ clz v0.8h, v0.8h
+ clz v31.8h, v0.8h
+ clz v0.8h, v31.8h
+ clz v0.4s, v0.4s
+ clz v31.4s, v0.4s
+ clz v0.4s, v31.4s
+
+ not v0.8b, v0.8b
+ not v31.8b, v0.8b
+ not v0.8b, v31.8b
+ not v0.16b, v0.16b
+ not v31.16b, v0.16b
+ not v0.16b, v31.16b
+
+ mvn v0.8b, v0.8b
+ mvn v31.8b, v0.8b
+ mvn v0.8b, v31.8b
+ mvn v0.16b, v0.16b
+ mvn v31.16b, v0.16b
+ mvn v0.16b, v31.16b
+
+ rbit v0.8b, v0.8b
+ rbit v31.8b, v0.8b
+ rbit v0.8b, v31.8b
+ rbit v0.16b, v0.16b
+ rbit v31.16b, v0.16b
+ rbit v0.16b, v31.16b
+
+ uadalp v0.4h, v0.8b
+ uadalp v31.4h, v0.8b
+ uadalp v0.4h, v31.8b
+ uadalp v0.2s, v0.4h
+ uadalp v31.2s, v0.4h
+ uadalp v0.2s, v31.4h
+ uadalp v0.1d, v0.2s
+ uadalp v31.1d, v0.2s
+ uadalp v0.1d, v31.2s
+ uadalp v0.8h, v0.16b
+ uadalp v31.8h, v0.16b
+ uadalp v0.8h, v31.16b
+ uadalp v0.4s, v0.8h
+ uadalp v31.4s, v0.8h
+ uadalp v0.4s, v31.8h
+ uadalp v0.2d, v0.4s
+ uadalp v31.2d, v0.4s
+ uadalp v0.2d, v31.4s
+
+ sqneg v0.8b, v0.8b
+ sqneg v31.8b, v0.8b
+ sqneg v0.8b, v31.8b
+ sqneg v0.4h, v0.4h
+ sqneg v31.4h, v0.4h
+ sqneg v0.4h, v31.4h
+ sqneg v0.2s, v0.2s
+ sqneg v31.2s, v0.2s
+ sqneg v0.2s, v31.2s
+ sqneg v0.16b, v0.16b
+ sqneg v31.16b, v0.16b
+ sqneg v0.16b, v31.16b
+ sqneg v0.8h, v0.8h
+ sqneg v31.8h, v0.8h
+ sqneg v0.8h, v31.8h
+ sqneg v0.4s, v0.4s
+ sqneg v31.4s, v0.4s
+ sqneg v0.4s, v31.4s
+ sqneg v0.2d, v0.2d
+ sqneg v31.2d, v0.2d
+ sqneg v0.2d, v31.2d
+
+ cmge v0.8b, v0.8b, #0
+ cmge v31.8b, v0.8b, #0
+ cmge v0.8b, v31.8b, #0
+ cmge v0.4h, v0.4h, #0
+ cmge v31.4h, v0.4h, #0
+ cmge v0.4h, v31.4h, #0
+ cmge v0.2s, v0.2s, #0
+ cmge v31.2s, v0.2s, #0
+ cmge v0.2s, v31.2s, #0
+ cmge v0.16b, v0.16b, #0
+ cmge v31.16b, v0.16b, #0
+ cmge v0.16b, v31.16b, #0
+ cmge v0.8h, v0.8h, #0
+ cmge v31.8h, v0.8h, #0
+ cmge v0.8h, v31.8h, #0
+ cmge v0.4s, v0.4s, #0
+ cmge v31.4s, v0.4s, #0
+ cmge v0.4s, v31.4s, #0
+ cmge v0.2d, v0.2d, #0
+ cmge v31.2d, v0.2d, #0
+ cmge v0.2d, v31.2d, #0
+
+ cmle v0.8b, v0.8b, #0
+ cmle v31.8b, v0.8b, #0
+ cmle v0.8b, v31.8b, #0
+ cmle v0.4h, v0.4h, #0
+ cmle v31.4h, v0.4h, #0
+ cmle v0.4h, v31.4h, #0
+ cmle v0.2s, v0.2s, #0
+ cmle v31.2s, v0.2s, #0
+ cmle v0.2s, v31.2s, #0
+ cmle v0.16b, v0.16b, #0
+ cmle v31.16b, v0.16b, #0
+ cmle v0.16b, v31.16b, #0
+ cmle v0.8h, v0.8h, #0
+ cmle v31.8h, v0.8h, #0
+ cmle v0.8h, v31.8h, #0
+ cmle v0.4s, v0.4s, #0
+ cmle v31.4s, v0.4s, #0
+ cmle v0.4s, v31.4s, #0
+ cmle v0.2d, v0.2d, #0
+ cmle v31.2d, v0.2d, #0
+ cmle v0.2d, v31.2d, #0
+
+ neg v0.8b, v0.8b
+ neg v31.8b, v0.8b
+ neg v0.8b, v31.8b
+ neg v0.4h, v0.4h
+ neg v31.4h, v0.4h
+ neg v0.4h, v31.4h
+ neg v0.2s, v0.2s
+ neg v31.2s, v0.2s
+ neg v0.2s, v31.2s
+ neg v0.16b, v0.16b
+ neg v31.16b, v0.16b
+ neg v0.16b, v31.16b
+ neg v0.8h, v0.8h
+ neg v31.8h, v0.8h
+ neg v0.8h, v31.8h
+ neg v0.4s, v0.4s
+ neg v31.4s, v0.4s
+ neg v0.4s, v31.4s
+ neg v0.2d, v0.2d
+ neg v31.2d, v0.2d
+ neg v0.2d, v31.2d
--
2.50.1

1238
SOURCES/binutils-AArch64-missing-assembler-tests-7.patch Normal file
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File diff suppressed because it is too large Load Diff

207
SOURCES/binutils-AArch64-missing-assembler-tests-8.patch Normal file
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@ -0,0 +1,207 @@
From c7fa4b95bb1711b5bd692583d81f4812444aaf18 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:09:08 +0100
Subject: [PATCH] aarch64: Add new test dp-general-two-source.d
lsl was already tested but is included here as part of the same encoding
group.
---
.../gas/aarch64/dp-general-two-source.d | 89 +++++++++++++++++++
.../gas/aarch64/dp-general-two-source.s | 89 +++++++++++++++++++
2 files changed, 178 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/dp-general-two-source.d
create mode 100644 gas/testsuite/gas/aarch64/dp-general-two-source.s
diff --git a/gas/testsuite/gas/aarch64/dp-general-two-source.d b/gas/testsuite/gas/aarch64/dp-general-two-source.d
new file mode 100644
index 00000000000..5c0d816d50e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dp-general-two-source.d
@@ -0,0 +1,89 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 1ac00800 udiv w0, w0, w0
+ *[0-9a-f]+: 1ac0081f udiv wzr, w0, w0
+ *[0-9a-f]+: 1ac00be0 udiv w0, wzr, w0
+ *[0-9a-f]+: 1adf0800 udiv w0, w0, wzr
+ *[0-9a-f]+: 9ac00800 udiv x0, x0, x0
+ *[0-9a-f]+: 9ac0081f udiv xzr, x0, x0
+ *[0-9a-f]+: 9ac00be0 udiv x0, xzr, x0
+ *[0-9a-f]+: 9adf0800 udiv x0, x0, xzr
+ *[0-9a-f]+: 1ac00c00 sdiv w0, w0, w0
+ *[0-9a-f]+: 1ac00c1f sdiv wzr, w0, w0
+ *[0-9a-f]+: 1ac00fe0 sdiv w0, wzr, w0
+ *[0-9a-f]+: 1adf0c00 sdiv w0, w0, wzr
+ *[0-9a-f]+: 9ac00c00 sdiv x0, x0, x0
+ *[0-9a-f]+: 9ac00c1f sdiv xzr, x0, x0
+ *[0-9a-f]+: 9ac00fe0 sdiv x0, xzr, x0
+ *[0-9a-f]+: 9adf0c00 sdiv x0, x0, xzr
+ *[0-9a-f]+: 1ac02000 lsl w0, w0, w0
+ *[0-9a-f]+: 1ac0201f lsl wzr, w0, w0
+ *[0-9a-f]+: 1ac023e0 lsl w0, wzr, w0
+ *[0-9a-f]+: 1adf2000 lsl w0, w0, wzr
+ *[0-9a-f]+: 9ac02000 lsl x0, x0, x0
+ *[0-9a-f]+: 9ac0201f lsl xzr, x0, x0
+ *[0-9a-f]+: 9ac023e0 lsl x0, xzr, x0
+ *[0-9a-f]+: 9adf2000 lsl x0, x0, xzr
+ *[0-9a-f]+: 1ac02000 lsl w0, w0, w0
+ *[0-9a-f]+: 1ac0201f lsl wzr, w0, w0
+ *[0-9a-f]+: 1ac023e0 lsl w0, wzr, w0
+ *[0-9a-f]+: 1adf2000 lsl w0, w0, wzr
+ *[0-9a-f]+: 9ac02000 lsl x0, x0, x0
+ *[0-9a-f]+: 9ac0201f lsl xzr, x0, x0
+ *[0-9a-f]+: 9ac023e0 lsl x0, xzr, x0
+ *[0-9a-f]+: 9adf2000 lsl x0, x0, xzr
+ *[0-9a-f]+: 1ac02400 lsr w0, w0, w0
+ *[0-9a-f]+: 1ac0241f lsr wzr, w0, w0
+ *[0-9a-f]+: 1ac027e0 lsr w0, wzr, w0
+ *[0-9a-f]+: 1adf2400 lsr w0, w0, wzr
+ *[0-9a-f]+: 9ac02400 lsr x0, x0, x0
+ *[0-9a-f]+: 9ac0241f lsr xzr, x0, x0
+ *[0-9a-f]+: 9ac027e0 lsr x0, xzr, x0
+ *[0-9a-f]+: 9adf2400 lsr x0, x0, xzr
+ *[0-9a-f]+: 1ac02400 lsr w0, w0, w0
+ *[0-9a-f]+: 1ac0241f lsr wzr, w0, w0
+ *[0-9a-f]+: 1ac027e0 lsr w0, wzr, w0
+ *[0-9a-f]+: 1adf2400 lsr w0, w0, wzr
+ *[0-9a-f]+: 9ac02400 lsr x0, x0, x0
+ *[0-9a-f]+: 9ac0241f lsr xzr, x0, x0
+ *[0-9a-f]+: 9ac027e0 lsr x0, xzr, x0
+ *[0-9a-f]+: 9adf2400 lsr x0, x0, xzr
+ *[0-9a-f]+: 1ac02800 asr w0, w0, w0
+ *[0-9a-f]+: 1ac0281f asr wzr, w0, w0
+ *[0-9a-f]+: 1ac02be0 asr w0, wzr, w0
+ *[0-9a-f]+: 1adf2800 asr w0, w0, wzr
+ *[0-9a-f]+: 9ac02800 asr x0, x0, x0
+ *[0-9a-f]+: 9ac0281f asr xzr, x0, x0
+ *[0-9a-f]+: 9ac02be0 asr x0, xzr, x0
+ *[0-9a-f]+: 9adf2800 asr x0, x0, xzr
+ *[0-9a-f]+: 1ac02800 asr w0, w0, w0
+ *[0-9a-f]+: 1ac0281f asr wzr, w0, w0
+ *[0-9a-f]+: 1ac02be0 asr w0, wzr, w0
+ *[0-9a-f]+: 1adf2800 asr w0, w0, wzr
+ *[0-9a-f]+: 9ac02800 asr x0, x0, x0
+ *[0-9a-f]+: 9ac0281f asr xzr, x0, x0
+ *[0-9a-f]+: 9ac02be0 asr x0, xzr, x0
+ *[0-9a-f]+: 9adf2800 asr x0, x0, xzr
+ *[0-9a-f]+: 1ac02c00 ror w0, w0, w0
+ *[0-9a-f]+: 1ac02c1f ror wzr, w0, w0
+ *[0-9a-f]+: 1ac02fe0 ror w0, wzr, w0
+ *[0-9a-f]+: 1adf2c00 ror w0, w0, wzr
+ *[0-9a-f]+: 9ac02c00 ror x0, x0, x0
+ *[0-9a-f]+: 9ac02c1f ror xzr, x0, x0
+ *[0-9a-f]+: 9ac02fe0 ror x0, xzr, x0
+ *[0-9a-f]+: 9adf2c00 ror x0, x0, xzr
+ *[0-9a-f]+: 1ac02c00 ror w0, w0, w0
+ *[0-9a-f]+: 1ac02c1f ror wzr, w0, w0
+ *[0-9a-f]+: 1ac02fe0 ror w0, wzr, w0
+ *[0-9a-f]+: 1adf2c00 ror w0, w0, wzr
+ *[0-9a-f]+: 9ac02c00 ror x0, x0, x0
+ *[0-9a-f]+: 9ac02c1f ror xzr, x0, x0
+ *[0-9a-f]+: 9ac02fe0 ror x0, xzr, x0
+ *[0-9a-f]+: 9adf2c00 ror x0, x0, xzr
diff --git a/gas/testsuite/gas/aarch64/dp-general-two-source.s b/gas/testsuite/gas/aarch64/dp-general-two-source.s
new file mode 100644
index 00000000000..95f2f0038a9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dp-general-two-source.s
@@ -0,0 +1,89 @@
+ udiv w0, w0, w0
+ udiv wzr, w0, w0
+ udiv w0, wzr, w0
+ udiv w0, w0, wzr
+ udiv x0, x0, x0
+ udiv xzr, x0, x0
+ udiv x0, xzr, x0
+ udiv x0, x0, xzr
+
+ sdiv w0, w0, w0
+ sdiv wzr, w0, w0
+ sdiv w0, wzr, w0
+ sdiv w0, w0, wzr
+ sdiv x0, x0, x0
+ sdiv xzr, x0, x0
+ sdiv x0, xzr, x0
+ sdiv x0, x0, xzr
+
+ lslv w0, w0, w0
+ lslv wzr, w0, w0
+ lslv w0, wzr, w0
+ lslv w0, w0, wzr
+ lslv x0, x0, x0
+ lslv xzr, x0, x0
+ lslv x0, xzr, x0
+ lslv x0, x0, xzr
+
+ lsl w0, w0, w0
+ lsl wzr, w0, w0
+ lsl w0, wzr, w0
+ lsl w0, w0, wzr
+ lsl x0, x0, x0
+ lsl xzr, x0, x0
+ lsl x0, xzr, x0
+ lsl x0, x0, xzr
+
+ lsrv w0, w0, w0
+ lsrv wzr, w0, w0
+ lsrv w0, wzr, w0
+ lsrv w0, w0, wzr
+ lsrv x0, x0, x0
+ lsrv xzr, x0, x0
+ lsrv x0, xzr, x0
+ lsrv x0, x0, xzr
+
+ lsr w0, w0, w0
+ lsr wzr, w0, w0
+ lsr w0, wzr, w0
+ lsr w0, w0, wzr
+ lsr x0, x0, x0
+ lsr xzr, x0, x0
+ lsr x0, xzr, x0
+ lsr x0, x0, xzr
+
+ asrv w0, w0, w0
+ asrv wzr, w0, w0
+ asrv w0, wzr, w0
+ asrv w0, w0, wzr
+ asrv x0, x0, x0
+ asrv xzr, x0, x0
+ asrv x0, xzr, x0
+ asrv x0, x0, xzr
+
+ asr w0, w0, w0
+ asr wzr, w0, w0
+ asr w0, wzr, w0
+ asr w0, w0, wzr
+ asr x0, x0, x0
+ asr xzr, x0, x0
+ asr x0, xzr, x0
+ asr x0, x0, xzr
+
+ rorv w0, w0, w0
+ rorv wzr, w0, w0
+ rorv w0, wzr, w0
+ rorv w0, w0, wzr
+ rorv x0, x0, x0
+ rorv xzr, x0, x0
+ rorv x0, xzr, x0
+ rorv x0, x0, xzr
+
+ ror w0, w0, w0
+ ror wzr, w0, w0
+ ror w0, wzr, w0
+ ror w0, w0, wzr
+ ror x0, x0, x0
+ ror xzr, x0, x0
+ ror x0, xzr, x0
+ ror x0, x0, xzr
--
2.50.1

181
SOURCES/binutils-AArch64-missing-assembler-tests-9.patch Normal file
View File

@ -0,0 +1,181 @@
From 87d10eecf9db0e77948e701387111d20c1211da0 Mon Sep 17 00:00:00 2001
From: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun, 20 Apr 2025 23:11:29 +0100
Subject: [PATCH] aarch64: Add new test conditional-compare.d
The register form of ccmp was already tested.
---
.../gas/aarch64/conditional-compare.d | 77 +++++++++++++++++++
.../gas/aarch64/conditional-compare.s | 76 ++++++++++++++++++
2 files changed, 153 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/conditional-compare.d
create mode 100644 gas/testsuite/gas/aarch64/conditional-compare.s
diff --git a/gas/testsuite/gas/aarch64/conditional-compare.d b/gas/testsuite/gas/aarch64/conditional-compare.d
new file mode 100644
index 00000000000..294e0c94c30
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/conditional-compare.d
@@ -0,0 +1,77 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 3a400800 ccmn w0, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a400be0 ccmn wzr, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a5f0800 ccmn w0, #0x1f, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a40080f ccmn w0, #0x0, #0xf, eq // eq = none
+ *[0-9a-f]+: 3a40f800 ccmn w0, #0x0, #0x0, nv
+ *[0-9a-f]+: ba400800 ccmn x0, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: ba400be0 ccmn xzr, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: ba5f0800 ccmn x0, #0x1f, #0x0, eq // eq = none
+ *[0-9a-f]+: ba40080f ccmn x0, #0x0, #0xf, eq // eq = none
+ *[0-9a-f]+: ba40f800 ccmn x0, #0x0, #0x0, nv
+ *[0-9a-f]+: 7a400800 ccmp w0, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: 7a400be0 ccmp wzr, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: 7a5f0800 ccmp w0, #0x1f, #0x0, eq // eq = none
+ *[0-9a-f]+: 7a40080f ccmp w0, #0x0, #0xf, eq // eq = none
+ *[0-9a-f]+: 7a40f800 ccmp w0, #0x0, #0x0, nv
+ *[0-9a-f]+: fa400800 ccmp x0, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: fa400be0 ccmp xzr, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: fa5f0800 ccmp x0, #0x1f, #0x0, eq // eq = none
+ *[0-9a-f]+: fa40080f ccmp x0, #0x0, #0xf, eq // eq = none
+ *[0-9a-f]+: fa40f800 ccmp x0, #0x0, #0x0, nv
+ *[0-9a-f]+: 3a400000 ccmn w0, w0, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a4003e0 ccmn wzr, w0, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a5f0000 ccmn w0, wzr, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a40000f ccmn w0, w0, #0xf, eq // eq = none
+ *[0-9a-f]+: 3a40f000 ccmn w0, w0, #0x0, nv
+ *[0-9a-f]+: ba400000 ccmn x0, x0, #0x0, eq // eq = none
+ *[0-9a-f]+: ba4003e0 ccmn xzr, x0, #0x0, eq // eq = none
+ *[0-9a-f]+: ba5f0000 ccmn x0, xzr, #0x0, eq // eq = none
+ *[0-9a-f]+: ba40000f ccmn x0, x0, #0xf, eq // eq = none
+ *[0-9a-f]+: ba40f000 ccmn x0, x0, #0x0, nv
+ *[0-9a-f]+: 7a400000 ccmp w0, w0, #0x0, eq // eq = none
+ *[0-9a-f]+: 7a4003e0 ccmp wzr, w0, #0x0, eq // eq = none
+ *[0-9a-f]+: 7a5f0000 ccmp w0, wzr, #0x0, eq // eq = none
+ *[0-9a-f]+: 7a40000f ccmp w0, w0, #0xf, eq // eq = none
+ *[0-9a-f]+: 7a40f000 ccmp w0, w0, #0x0, nv
+ *[0-9a-f]+: fa400000 ccmp x0, x0, #0x0, eq // eq = none
+ *[0-9a-f]+: fa4003e0 ccmp xzr, x0, #0x0, eq // eq = none
+ *[0-9a-f]+: fa5f0000 ccmp x0, xzr, #0x0, eq // eq = none
+ *[0-9a-f]+: fa40000f ccmp x0, x0, #0xf, eq // eq = none
+ *[0-9a-f]+: fa40f000 ccmp x0, x0, #0x0, nv
+ *[0-9a-f]+: 3a400800 ccmn w0, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a400800 ccmn w0, #0x0, #0x0, eq // eq = none
+ *[0-9a-f]+: 3a401800 ccmn w0, #0x0, #0x0, ne // ne = any
+ *[0-9a-f]+: 3a401800 ccmn w0, #0x0, #0x0, ne // ne = any
+ *[0-9a-f]+: 3a402800 ccmn w0, #0x0, #0x0, cs // cs = hs, nlast
+ *[0-9a-f]+: 3a402800 ccmn w0, #0x0, #0x0, cs // cs = hs, nlast
+ *[0-9a-f]+: 3a402800 ccmn w0, #0x0, #0x0, cs // cs = hs, nlast
+ *[0-9a-f]+: 3a403800 ccmn w0, #0x0, #0x0, cc // cc = lo, ul, last
+ *[0-9a-f]+: 3a403800 ccmn w0, #0x0, #0x0, cc // cc = lo, ul, last
+ *[0-9a-f]+: 3a403800 ccmn w0, #0x0, #0x0, cc // cc = lo, ul, last
+ *[0-9a-f]+: 3a404800 ccmn w0, #0x0, #0x0, mi // mi = first
+ *[0-9a-f]+: 3a404800 ccmn w0, #0x0, #0x0, mi // mi = first
+ *[0-9a-f]+: 3a405800 ccmn w0, #0x0, #0x0, pl // pl = nfrst
+ *[0-9a-f]+: 3a405800 ccmn w0, #0x0, #0x0, pl // pl = nfrst
+ *[0-9a-f]+: 3a406800 ccmn w0, #0x0, #0x0, vs
+ *[0-9a-f]+: 3a407800 ccmn w0, #0x0, #0x0, vc
+ *[0-9a-f]+: 3a408800 ccmn w0, #0x0, #0x0, hi // hi = pmore
+ *[0-9a-f]+: 3a408800 ccmn w0, #0x0, #0x0, hi // hi = pmore
+ *[0-9a-f]+: 3a409800 ccmn w0, #0x0, #0x0, ls // ls = plast
+ *[0-9a-f]+: 3a409800 ccmn w0, #0x0, #0x0, ls // ls = plast
+ *[0-9a-f]+: 3a40a800 ccmn w0, #0x0, #0x0, ge // ge = tcont
+ *[0-9a-f]+: 3a40a800 ccmn w0, #0x0, #0x0, ge // ge = tcont
+ *[0-9a-f]+: 3a40b800 ccmn w0, #0x0, #0x0, lt // lt = tstop
+ *[0-9a-f]+: 3a40b800 ccmn w0, #0x0, #0x0, lt // lt = tstop
+ *[0-9a-f]+: 3a40c800 ccmn w0, #0x0, #0x0, gt
+ *[0-9a-f]+: 3a40d800 ccmn w0, #0x0, #0x0, le
+ *[0-9a-f]+: 3a40e800 ccmn w0, #0x0, #0x0, al
+ *[0-9a-f]+: 3a40f800 ccmn w0, #0x0, #0x0, nv
diff --git a/gas/testsuite/gas/aarch64/conditional-compare.s b/gas/testsuite/gas/aarch64/conditional-compare.s
new file mode 100644
index 00000000000..1fe23d3e701
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/conditional-compare.s
@@ -0,0 +1,76 @@
+ ccmn w0, #0, #0, eq
+ ccmn wzr, #0, #0, eq
+ ccmn w0, #31, #0, eq
+ ccmn w0, #0, #15, eq
+ ccmn w0, #0, #0, nv
+
+ ccmn x0, #0, #0, eq
+ ccmn xzr, #0, #0, eq
+ ccmn x0, #31, #0, eq
+ ccmn x0, #0, #15, eq
+ ccmn x0, #0, #0, nv
+
+ ccmp w0, #0, #0, eq
+ ccmp wzr, #0, #0, eq
+ ccmp w0, #31, #0, eq
+ ccmp w0, #0, #15, eq
+ ccmp w0, #0, #0, nv
+
+ ccmp x0, #0, #0, eq
+ ccmp xzr, #0, #0, eq
+ ccmp x0, #31, #0, eq
+ ccmp x0, #0, #15, eq
+ ccmp x0, #0, #0, nv
+
+ ccmn w0, w0, #0, eq
+ ccmn wzr, w0, #0, eq
+ ccmn w0, wzr, #0, eq
+ ccmn w0, w0, #15, eq
+ ccmn w0, w0, #0, nv
+
+ ccmn x0, x0, #0, eq
+ ccmn xzr, x0, #0, eq
+ ccmn x0, xzr, #0, eq
+ ccmn x0, x0, #15, eq
+ ccmn x0, x0, #0, nv
+
+ ccmp w0, w0, #0, eq
+ ccmp wzr, w0, #0, eq
+ ccmp w0, wzr, #0, eq
+ ccmp w0, w0, #15, eq
+ ccmp w0, w0, #0, nv
+
+ ccmp x0, x0, #0, eq
+ ccmp xzr, x0, #0, eq
+ ccmp x0, xzr, #0, eq
+ ccmp x0, x0, #15, eq
+ ccmp x0, x0, #0, nv
+
+ ccmn w0, #0, #0, eq
+ ccmn w0, #0, #0, none
+ ccmn w0, #0, #0, ne
+ ccmn w0, #0, #0, any
+ ccmn w0, #0, #0, hs
+ ccmn w0, #0, #0, cs
+ ccmn w0, #0, #0, nlast
+ ccmn w0, #0, #0, lo
+ ccmn w0, #0, #0, cc
+ ccmn w0, #0, #0, last
+ ccmn w0, #0, #0, mi
+ ccmn w0, #0, #0, first
+ ccmn w0, #0, #0, pl
+ ccmn w0, #0, #0, nfrst
+ ccmn w0, #0, #0, vs
+ ccmn w0, #0, #0, vc
+ ccmn w0, #0, #0, hi
+ ccmn w0, #0, #0, pmore
+ ccmn w0, #0, #0, ls
+ ccmn w0, #0, #0, plast
+ ccmn w0, #0, #0, ge
+ ccmn w0, #0, #0, tcont
+ ccmn w0, #0, #0, lt
+ ccmn w0, #0, #0, tstop
+ ccmn w0, #0, #0, gt
+ ccmn w0, #0, #0, le
+ ccmn w0, #0, #0, al
+ ccmn w0, #0, #0, nv
--
2.50.1

146
SOURCES/binutils-execstack-error-tests.patch Normal file
View File

@ -0,0 +1,146 @@
commit 17e62fe5f78d33db23bf43eb7c20accd56e65ebe (HEAD -> master, origin/master, origin/HEAD)
Author: Nick Clifton <nickc@redhat.com>
Date: Tue Aug 19 15:25:39 2025 +0100
Add tests of the linker's --errror-execstack and --error-rwx-segments options
diff -rup binutils-2.35.2.orig/ld/testsuite/ld-elf/elf.exp binutils-2.35.2/ld/testsuite/ld-elf/elf.exp
--- binutils-2.35.2.orig/ld/testsuite/ld-elf/elf.exp 2025-08-19 16:49:58.651597488 +0100
+++ binutils-2.35.2/ld/testsuite/ld-elf/elf.exp 2025-08-19 16:50:14.483671894 +0100
@@ -244,6 +244,13 @@ if { [istarget *-*-*linux*]
{pr29072-a.s} \
{{ld pr29072.a.warn}} \
"pr29072-a.exe"] \
+ [list "Test --error-execstack with an executable .note.GNU-stack" \
+ "--warn-execstack --error-execstack" \
+ "" \
+ "" \
+ {pr29072-a.s} \
+ {{ld gnu_execstack.err}} \
+ "gnu_execstack.exe"] \
[list "PR 29072 (warn about -z execstack)" \
"-z execstack --warn-execstack --no-error-execstack" \
"" \
@@ -251,6 +258,13 @@ if { [istarget *-*-*linux*]
{stack.s} \
{{ld pr29072.c.warn}} \
"pr29072-c.exe"] \
+ [list "Test --error-execstack with -z execstack" \
+ "-z execstack --warn-execstack --error-execstack" \
+ "" \
+ "" \
+ {stack.s} \
+ {{ld z_execstack.err}} \
+ "execstack.exe"] \
[list "PR ld/29072 (suppress warnings about executable stack)" \
"-e 0 --no-warn-execstack" \
"" \
@@ -258,13 +272,20 @@ if { [istarget *-*-*linux*]
{pr29072-a.s} \
{} \
"pr29072-d.exe"] \
- [list "Ensure that a warning issued when creating a segment with RWX permissions" \
+ [list "Ensure that a warning is issued when creating a segment with RWX permissions" \
"-e 0 -Tnobits-1.t --warn-rwx-segments --no-error-rwx-segments" \
"" \
"" \
{nobits-1.s} \
{{ld rwx-segments-1.l}} \
"rwx-segments-1.exe"] \
+ [list "Ensure that a error can be issued when creating a segment with RWX permissions" \
+ "-e 0 -Tnobits-1.t --warn-rwx-segments --error-rwx-segments" \
+ "" \
+ "" \
+ {nobits-1.s} \
+ {{ld rwx-segments-3.err}} \
+ "rwx-segments-3.exe"] \
[list "Ensure that a warning issued when creating a TLS segment with execute permission" \
"-e 0 -T rwx-segments-2.t --warn-rwx-segments --no-error-rwx-segments" \
"" \
@@ -272,6 +293,13 @@ if { [istarget *-*-*linux*]
{size-2.s} \
{{ld rwx-segments-2.l}} \
"rwx-segments-2.exe"] \
+ [list "Ensure that an error cn be issued when creating a TLS segment with execute permission" \
+ "-e 0 -T rwx-segments-2.t --warn-rwx-segments --error-rwx-segments" \
+ "" \
+ "" \
+ {size-2.s} \
+ {{ld rwx-segments-4.err}} \
+ "rwx-segments-4.exe"] \
[list "Ensure that the RWX warning can be suppressed" \
"-e 0 -Tnobits-1.t --no-warn-rwx-segments" \
"" \
@@ -293,6 +321,16 @@ if { [istarget *-*-*linux*]
{{ld pr29072.b.warn}} \
"pr29072-b.exe"] \
]
+
+ run_ld_link_tests [list \
+ [list "error when .note.GNU-stack is absent" \
+ "-e 0 -z stack-size=0x123400 --warn-execstack --error-execstack" \
+ "" \
+ "" \
+ {pr29072-b.s} \
+ {{ld missing-execstack.err}} \
+ "missing-execstack.exe"] \
+ ]
} else {
run_ld_link_tests [list \
[list "PR ld/29072 (ignore absent .note.GNU-stack)" \
diff --git a/ld/testsuite/ld-elf/gnu_execstack.err b/ld/testsuite/ld-elf/gnu_execstack.err
new file mode 100644
index 00000000000..be70b63043a
--- /dev/null
+++ b/ld/testsuite/ld-elf/gnu_execstack.err
@@ -0,0 +1,3 @@
+#...
+.*: error: .*: is triggering the generation of an executable stack \(because it has an executable .note.GNU-stack section\)
+#...
diff --git a/ld/testsuite/ld-elf/missing-execstack.err b/ld/testsuite/ld-elf/missing-execstack.err
new file mode 100644
index 00000000000..9549cf5cd28
--- /dev/null
+++ b/ld/testsuite/ld-elf/missing-execstack.err
@@ -0,0 +1,3 @@
+#...
+.*: error: .*\.o: is triggering the generation of an executable stack because it does not have a .note.GNU-stack section
+#...
diff --git a/ld/testsuite/ld-elf/rwx-segments-3.err b/ld/testsuite/ld-elf/rwx-segments-3.err
new file mode 100644
index 00000000000..5a584db19be
--- /dev/null
+++ b/ld/testsuite/ld-elf/rwx-segments-3.err
@@ -0,0 +1,3 @@
+#...
+.* error: .* has a LOAD segment with RWX permissions
+#...
\ No newline at end of file
diff --git a/ld/testsuite/ld-elf/rwx-segments-4.err b/ld/testsuite/ld-elf/rwx-segments-4.err
new file mode 100644
index 00000000000..2603f57db47
--- /dev/null
+++ b/ld/testsuite/ld-elf/rwx-segments-4.err
@@ -0,0 +1,3 @@
+#...
+.*: error: .* has a TLS segment with execute permission
+#...
diff --git a/ld/testsuite/ld-elf/z_execstack.err b/ld/testsuite/ld-elf/z_execstack.err
new file mode 100644
index 00000000000..703b42a9e01
--- /dev/null
+++ b/ld/testsuite/ld-elf/z_execstack.err
@@ -0,0 +1,4 @@
+#...
+.*: error: creating an executable stack because of -z execstack command line option
+#...
+
diff -rup binutils-2.35.2.orig/ld/testsuite/ld-elf/z_execstack.err binutils-2.35.2/ld/testsuite/ld-elf/z_execstack.err
--- binutils-2.35.2.orig/ld/testsuite/ld-elf/z_execstack.err 2025-08-20 15:22:19.495234206 +0100
+++ binutils-2.35.2/ld/testsuite/ld-elf/z_execstack.err 2025-08-20 15:22:55.953388857 +0100
@@ -1,4 +1,3 @@
#...
.*: error: creating an executable stack because of -z execstack command line option
#...
-

85
SOURCES/binutils-s390-z17-cpu-name.patch Normal file
View File

@ -0,0 +1,85 @@
From 981fe5fd80faf511aa265e841a380c9b46be30e6 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Wed, 9 Apr 2025 08:59:24 +0200
Subject: [PATCH] s390: Add support for z17 as CPU name
So far IBM z17 was identified as arch15. Add the real name, as it has
been announced. [1]
[1]: IBM z17 announcement letter, AD25-0015,
https://www.ibm.com/docs/en/announcements/z17-makes-more-possible
gas/
* config/tc-s390.c (s390_parse_cpu): Add z17 as alternate CPU
name for arch15.
* doc/c-s390.texi: Likewise.
* doc/as.texi: Likewise.
opcodes/
* s390-mkopc.c (main): Add z17 as alternate CPU name for arch15.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
diff -rup binutils.orig/gas/config/tc-s390.c binutils-2.35.2/gas/config/tc-s390.c
--- binutils.orig/gas/config/tc-s390.c 2025-04-15 14:56:47.312547273 +0100
+++ binutils-2.35.2/gas/config/tc-s390.c 2025-04-15 14:57:09.926769869 +0100
@@ -295,7 +295,7 @@ s390_parse_cpu (const char * arg
S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX },
{ STRING_COMMA_LEN ("z16"), STRING_COMMA_LEN ("arch14"),
S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX },
- { STRING_COMMA_LEN (""), STRING_COMMA_LEN ("arch15"),
+ { STRING_COMMA_LEN ("z17"), STRING_COMMA_LEN ("arch15"),
S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX }
};
static struct
Only in binutils-2.35.2/gas/config: tc-s390.c.orig
diff -rup binutils.orig/gas/doc/as.texi binutils-2.35.2/gas/doc/as.texi
--- binutils.orig/gas/doc/as.texi 2025-04-15 14:56:47.219547061 +0100
+++ binutils-2.35.2/gas/doc/as.texi 2025-04-15 14:57:09.927100746 +0100
@@ -1873,7 +1873,8 @@ Specify which s390 processor variant is
@samp{arch6}), @samp{z9-109}, @samp{z9-ec} (or @samp{arch7}), @samp{z10} (or
@samp{arch8}), @samp{z196} (or @samp{arch9}), @samp{zEC12} (or @samp{arch10}),
@samp{z13} (or @samp{arch11}), @samp{z14} (or @samp{arch12}), @samp{z15}
-(or @samp{arch13}), @samp{z16} (or @samp{arch14}), or @samp{arch15}.
+(or @samp{arch13}), @samp{z16} (or @samp{arch14}), or @samp{z17} (or
+@samp{arch15}).
@item -mregnames
@itemx -mno-regnames
Allow or disallow symbolic names for registers.
Only in binutils-2.35.2/gas/doc: as.texi.orig
diff -rup binutils.orig/gas/doc/c-s390.texi binutils-2.35.2/gas/doc/c-s390.texi
--- binutils.orig/gas/doc/c-s390.texi 2025-04-15 14:56:47.219547061 +0100
+++ binutils-2.35.2/gas/doc/c-s390.texi 2025-04-15 14:57:09.927358592 +0100
@@ -18,7 +18,8 @@ and eleven chip levels. The architecture
Architecture (ESA) and the newer z/Architecture mode. The chip levels
are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
-(or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or arch15.
+(or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or
+z17 (arch15).
@menu
* s390 Options:: Command-line Options.
@@ -73,7 +74,7 @@ are recognized:
@code{z14} (or @code{arch12}),
@code{z15} (or @code{arch13}),
@code{z16} (or @code{arch14}), and
-@code{arch15}.
+@code{z17} (or @code{arch15}).
Assembling an instruction that is not supported on the target
processor results in an error message.
diff -rup binutils.orig/opcodes/s390-mkopc.c binutils-2.35.2/opcodes/s390-mkopc.c
--- binutils.orig/opcodes/s390-mkopc.c 2025-04-15 14:56:46.996546553 +0100
+++ binutils-2.35.2/opcodes/s390-mkopc.c 2025-04-15 14:57:09.927435074 +0100
@@ -383,7 +383,8 @@ main (void)
else if (strcmp (cpu_string, "z16") == 0
|| strcmp (cpu_string, "arch14") == 0)
min_cpu = S390_OPCODE_ARCH14;
- else if (strcmp (cpu_string, "arch15") == 0)
+ else if (strcmp (cpu_string, "z17") == 0
+ || strcmp (cpu_string, "arch15") == 0)
min_cpu = S390_OPCODE_ARCH15;
else {
fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
Only in binutils-2.35.2/opcodes: s390-mkopc.c.orig

37
SPECS/binutils.spec
View File

@ -2,7 +2,7 @@
Summary: A GNU collection of binary utilities
Name: binutils%{?_with_debug:-debug}
Version: 2.35.2
Release: 63%{?dist}
Release: 67%{?dist}
License: GPLv3+
URL: https://sourceware.org/binutils
@ -510,6 +510,29 @@ Patch91: binutils-linker-diagnostic-message.patch
# Lifetime: Fixed in 2.45
Patch92: binutils-aarch64-small-plt0.patch
# Purpose: Adds support for z17 as an s390 cpu name.
# Lifetime: Fixed in 2.45
Patch93: binutils-s390-z17-cpu-name.patch
# Purpose: Add missing tests of AArch64 instructions to the assembler testsuite.
# Lifetime: Fixed in 2.45
Patch94: binutils-AArch64-missing-assembler-tests-1.patch
Patch95: binutils-AArch64-missing-assembler-tests-2.patch
Patch96: binutils-AArch64-missing-assembler-tests-3.patch
Patch97: binutils-AArch64-missing-assembler-tests-4.patch
Patch98: binutils-AArch64-missing-assembler-tests-5.patch
Patch99: binutils-AArch64-missing-assembler-tests-6.patch
Patch100: binutils-AArch64-missing-assembler-tests-7.patch
Patch101: binutils-AArch64-missing-assembler-tests-8.patch
Patch102: binutils-AArch64-missing-assembler-tests-9.patch
Patch103: binutils-AArch64-missing-assembler-tests-10.patch
Patch104: binutils-AArch64-missing-assembler-tests-11.patch
Patch105: binutils-AArch64-missing-assembler-tests-12.patch
# Purpose: Adds tests for the --error-execstack and --error-rwx-segments linker commmand line options.
# Lifetime: Fixed in 2.46
Patch106: binutils-execstack-error-tests.patch
#----------------------------------------------------------------------------
Provides: bundled(libiberty)
@ -1369,6 +1392,18 @@ exit 0
#----------------------------------------------------------------------------
%changelog
* Tue Aug 19 2025 Nick Clifton <nickc@redhat.com> - 2.35.2-67
- Adds tests for the linker's --error-execstack and --error-rwx-segments command line options. (RHEL-109970)
* Tue Jul 22 2025 Nick Clifton <nickc@redhat.com> - 2.35.2-66
- Add missing tests of AArch64 instructions to the assembler testsuite. (RHEL-104630)
* Mon Jun 02 2025 Nick Clifton <nickc@redhat.com> - 2.35.2-65
- NVR bump to allow rebuilding for RHEL-9.7 (RHEL-87216)
* Tue Apr 15 2025 Nick Clifton <nickc@redhat.com> - 2.35.2-64
- Adds z17 as a cpu name for the s390x architecture. (RHEL-87216)
* Fri Feb 07 2025 Nick Clifton <nickc@redhat.com> - 2.35.2-63
- Fix seg-fault in AArch64 linker when building u-boot. (RHEL-78350)