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Extend support for the arch14 and arch15 extensions to the s390 architecture.

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Resolves: RHEL-56896
This commit is contained in:
Nick Clifton 2024-11-18 13:17:44 +00:00
parent 97293c5143
commit 6a78c4cb8b
3 changed files with 341 additions and 1 deletions
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246
binutils-s390-arch15-15.patch Normal file
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@ -0,0 +1,246 @@
From b0588b2173bf9aeff9eadc0cc024c4c69e69114d Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Mon, 18 Nov 2024 10:42:21 +0100
Subject: [PATCH] s390: Add arch15 instruction names
Commit: b0588b2173bf
opcodes/
* s390-opc.txt: Add arch15 instruction names.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
opcodes/s390-opc.txt | 220 ++++++++++++++++++++++---------------------
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index bbc00b10355..82d6f06a992 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -2076,109 +2076,117 @@ b28f qpaci S_RD "query processor activity counter information" arch14 zarch
# arch15 instructions
-e70000000089 vblend VRR_VVVU0V " " arch15 zarch
-e70000000089 vblendb VRR_VVV0V " " arch15 zarch
-e70001000089 vblendh VRR_VVV0V " " arch15 zarch
-e70002000089 vblendf VRR_VVV0V " " arch15 zarch
-e70003000089 vblendg VRR_VVV0V " " arch15 zarch
-e70004000089 vblendq VRR_VVV0V " " arch15 zarch
-
-e70000000088 veval VRI_VVV0UV " " arch15 zarch
-
-e70000000054 vgem VRR_VV0U " " arch15 zarch
-e70000000054 vgemb VRR_VV " " arch15 zarch
-e70000001054 vgemh VRR_VV " " arch15 zarch
-e70000002054 vgemf VRR_VV " " arch15 zarch
-e70000003054 vgemg VRR_VV " " arch15 zarch
-e70000004054 vgemq VRR_VV " " arch15 zarch
-
-e700000030d7 vuphg VRR_VV " " arch15 zarch
-e700000030d5 vuplhg VRR_VV " " arch15 zarch
-e700000030d6 vuplg VRR_VV " " arch15 zarch
-e700000030d4 vupllg VRR_VV " " arch15 zarch
-
-e700000040f2 vavgq VRR_VVV " " arch15 zarch
-e700000040f0 vavglq VRR_VVV " " arch15 zarch
-e700000040db vecq VRR_VV " " arch15 zarch
-e700000040d9 veclq VRR_VV " " arch15 zarch
-e700000040f8 vceqq VRR_VVV " " arch15 zarch
-e700001040f8 vceqqs VRR_VVV " " arch15 zarch
-e700000040fb vchq VRR_VVV " " arch15 zarch
-e700001040fb vchqs VRR_VVV " " arch15 zarch
-e700000040f9 vchlq VRR_VVV " " arch15 zarch
-e700001040f9 vchlqs VRR_VVV " " arch15 zarch
-e70000004053 vclzq VRR_VV " " arch15 zarch
-e70000004052 vctzq VRR_VV " " arch15 zarch
-e700000040de vlcq VRR_VV " " arch15 zarch
-e700000040df vlpq VRR_VV " " arch15 zarch
-e700000040ff vmxq VRR_VVV " " arch15 zarch
-e700000040fd vmxlq VRR_VVV " " arch15 zarch
-e700000040fe vmnq VRR_VVV " " arch15 zarch
-e700000040fc vmnlq VRR_VVV " " arch15 zarch
-e700030000aa vmalg VRR_VVV0V " " arch15 zarch
-e700040000aa vmalq VRR_VVV0V " " arch15 zarch
-e700030000ab vmahg VRR_VVV0V " " arch15 zarch
-e700040000ab vmahq VRR_VVV0V " " arch15 zarch
-e700030000a9 vmalhg VRR_VVV0V " " arch15 zarch
-e700040000a9 vmalhq VRR_VVV0V " " arch15 zarch
-e700030000ae vmaeg VRR_VVV0V " " arch15 zarch
-e700030000ac vmaleg VRR_VVV0V " " arch15 zarch
-e700030000af vmaog VRR_VVV0V " " arch15 zarch
-e700030000ad vmalog VRR_VVV0V " " arch15 zarch
-e700000030a3 vmhg VRR_VVV " " arch15 zarch
-e700000040a3 vmhq VRR_VVV " " arch15 zarch
-e700000030a1 vmlhg VRR_VVV " " arch15 zarch
-e700000040a1 vmlhq VRR_VVV " " arch15 zarch
-e700000030a2 vmlg VRR_VVV " " arch15 zarch
-e700000040a2 vmlq VRR_VVV " " arch15 zarch
-e700000030a6 vmeg VRR_VVV " " arch15 zarch
-e700000030a4 vmleg VRR_VVV " " arch15 zarch
-e700000030a7 vmog VRR_VVV " " arch15 zarch
-e700000030a5 vmlog VRR_VVV " " arch15 zarch
-
-e700000000b2 vd VRR_VVV0UU " " arch15 zarch
-e700000020b2 vdf VRR_VVV0U02 " " arch15 zarch
-e700000030b2 vdg VRR_VVV0U02 " " arch15 zarch
-e700000040b2 vdq VRR_VVV0U02 " " arch15 zarch
-
-e700000000b0 vdl VRR_VVV0UU " " arch15 zarch
-e700000020b0 vdlf VRR_VVV0U02 " " arch15 zarch
-e700000030b0 vdlg VRR_VVV0U02 " " arch15 zarch
-e700000040b0 vdlq VRR_VVV0U02 " " arch15 zarch
-
-e700000000b3 vr VRR_VVV0UU " " arch15 zarch
-e700000020b3 vrf VRR_VVV0U02 " " arch15 zarch
-e700000030b3 vrg VRR_VVV0U02 " " arch15 zarch
-e700000040b3 vrq VRR_VVV0U02 " " arch15 zarch
-
-e700000000b1 vrl VRR_VVV0UU " " arch15 zarch
-e700000020b1 vrlf VRR_VVV0U02 " " arch15 zarch
-e700000030b1 vrlg VRR_VVV0U02 " " arch15 zarch
-e700000040b1 vrlq VRR_VVV0U02 " " arch15 zarch
-
-b968 clzg RRE_RR " " arch15 zarch
-b969 ctzg RRE_RR " " arch15 zarch
-
-e30000000060 lxab RXY_RRRD " " arch15 zarch
-e30000000062 lxah RXY_RRRD " " arch15 zarch
-e30000000064 lxaf RXY_RRRD " " arch15 zarch
-e30000000066 lxag RXY_RRRD " " arch15 zarch
-e30000000068 lxaq RXY_RRRD " " arch15 zarch
-
-e30000000061 llxab RXY_RRRD " " arch15 zarch
-e30000000063 llxah RXY_RRRD " " arch15 zarch
-e30000000065 llxaf RXY_RRRD " " arch15 zarch
-e30000000067 llxag RXY_RRRD " " arch15 zarch
-e30000000069 llxaq RXY_RRRD " " arch15 zarch
-
-b96c bextg RRF_R0RR2 " " arch15 zarch
-b96d bdepg RRF_R0RR2 " " arch15 zarch
-
-b93e kimd RRF_U0RR " " arch15 zarch optparm
-b93f klmd RRF_U0RR " " arch15 zarch optparm
-
-e6000000004e vcvbq VRR_VV0U2 " " arch15 zarch
-e6000000004a vcvdq VRI_VV0UU " " arch15 zarch
-
-e6000000005f vtp VRR_0V0U " " arch15 zarch optparm
-e6000000007f vtz VRR_0VVU " " arch15 zarch
+# Vector-Enhancements Facility 3
+
+e70000000089 vblend VRR_VVVU0V "vector blend" arch15 zarch
+e70000000089 vblendb VRR_VVV0V "vector blend byte" arch15 zarch
+e70001000089 vblendh VRR_VVV0V "vector blend halfword" arch15 zarch
+e70002000089 vblendf VRR_VVV0V "vector blend word" arch15 zarch
+e70003000089 vblendg VRR_VVV0V "vector blend doubleword" arch15 zarch
+e70004000089 vblendq VRR_VVV0V "vector blend quadword" arch15 zarch
+
+e70000000088 veval VRI_VVV0UV "vector evaluate" arch15 zarch
+
+e70000000054 vgem VRR_VV0U "vector generate element masks" arch15 zarch
+e70000000054 vgemb VRR_VV "vector generate element masks byte" arch15 zarch
+e70000001054 vgemh VRR_VV "vector generate element masks halfword" arch15 zarch
+e70000002054 vgemf VRR_VV "vector generate element masks word" arch15 zarch
+e70000003054 vgemg VRR_VV "vector generate element masks doubleword" arch15 zarch
+e70000004054 vgemq VRR_VV "vector generate element masks quadword" arch15 zarch
+
+e700000030d7 vuphg VRR_VV "vector unpack high doubleword" arch15 zarch
+e700000030d5 vuplhg VRR_VV "vector unpack logical high doubleword" arch15 zarch
+e700000030d6 vuplg VRR_VV "vector unpack low doubleword" arch15 zarch
+e700000030d4 vupllg VRR_VV "vector unpack logical low doubleword" arch15 zarch
+
+e700000040f2 vavgq VRR_VVV "vector average quadword" arch15 zarch
+e700000040f0 vavglq VRR_VVV "vector average logical quadword" arch15 zarch
+e700000040db vecq VRR_VV "vector element compare quadword" arch15 zarch
+e700000040d9 veclq VRR_VV "vector element compare logical quadword" arch15 zarch
+e700000040f8 vceqq VRR_VVV "vector compare equal quadword" arch15 zarch
+e700001040f8 vceqqs VRR_VVV "vector compare equal quadword" arch15 zarch
+e700000040fb vchq VRR_VVV "vector compare high quadword" arch15 zarch
+e700001040fb vchqs VRR_VVV "vector compare high quadword" arch15 zarch
+e700000040f9 vchlq VRR_VVV "vector compare high logical quadword" arch15 zarch
+e700001040f9 vchlqs VRR_VVV "vector compare high logical quadword" arch15 zarch
+e70000004053 vclzq VRR_VV "vector count leading zeros quadword" arch15 zarch
+e70000004052 vctzq VRR_VV "vector count trailing zeros quadword" arch15 zarch
+e700000040de vlcq VRR_VV "vector load complement quadword" arch15 zarch
+e700000040df vlpq VRR_VV "vector load positive quadword" arch15 zarch
+e700000040ff vmxq VRR_VVV "vector maximum quadword" arch15 zarch
+e700000040fd vmxlq VRR_VVV "vector maximum logical quadword" arch15 zarch
+e700000040fe vmnq VRR_VVV "vector minimum quadword" arch15 zarch
+e700000040fc vmnlq VRR_VVV "vector minimum logical quadword" arch15 zarch
+e700030000aa vmalg VRR_VVV0V "vector multiply and add low doubleword" arch15 zarch
+e700040000aa vmalq VRR_VVV0V "vector multiply and add low quadword" arch15 zarch
+e700030000ab vmahg VRR_VVV0V "vector multiply and add high doubleword" arch15 zarch
+e700040000ab vmahq VRR_VVV0V "vector multiply and add high quadword" arch15 zarch
+e700030000a9 vmalhg VRR_VVV0V "vector multiply and add logical high doubleword" arch15 zarch
+e700040000a9 vmalhq VRR_VVV0V "vector multiply and add logical high quadword" arch15 zarch
+e700030000ae vmaeg VRR_VVV0V "vector multiply and add even doubleword" arch15 zarch
+e700030000ac vmaleg VRR_VVV0V "vector multiply and add logical even doubleword" arch15 zarch
+e700030000af vmaog VRR_VVV0V "vector multiply and add odd doubleword" arch15 zarch
+e700030000ad vmalog VRR_VVV0V "vector multiply and add logical odd doubleword" arch15 zarch
+e700000030a3 vmhg VRR_VVV "vector multiply high doubleword" arch15 zarch
+e700000040a3 vmhq VRR_VVV "vector multiply high quadword" arch15 zarch
+e700000030a1 vmlhg VRR_VVV "vector multiply logical high doubleword" arch15 zarch
+e700000040a1 vmlhq VRR_VVV "vector multiply logical high quadword" arch15 zarch
+e700000030a2 vmlg VRR_VVV "vector multiply low doubleword" arch15 zarch
+e700000040a2 vmlq VRR_VVV "vector multiply low quadword" arch15 zarch
+e700000030a6 vmeg VRR_VVV "vector multiply even doubleword" arch15 zarch
+e700000030a4 vmleg VRR_VVV "vector multiply logical even doubleword" arch15 zarch
+e700000030a7 vmog VRR_VVV "vector multiply odd doubleword" arch15 zarch
+e700000030a5 vmlog VRR_VVV "vector multiply logical odd doubleword" arch15 zarch
+
+e700000000b2 vd VRR_VVV0UU "vector divide" arch15 zarch
+e700000020b2 vdf VRR_VVV0U02 "vector divide word" arch15 zarch
+e700000030b2 vdg VRR_VVV0U02 "vector divide doubleword" arch15 zarch
+e700000040b2 vdq VRR_VVV0U02 "vector divide quadword" arch15 zarch
+
+e700000000b0 vdl VRR_VVV0UU "vector divide logical" arch15 zarch
+e700000020b0 vdlf VRR_VVV0U02 "vector divide logical word" arch15 zarch
+e700000030b0 vdlg VRR_VVV0U02 "vector divide logical doubleword" arch15 zarch
+e700000040b0 vdlq VRR_VVV0U02 "vector divide logical quadword" arch15 zarch
+
+e700000000b3 vr VRR_VVV0UU "vector remainder" arch15 zarch
+e700000020b3 vrf VRR_VVV0U02 "vector remainder word" arch15 zarch
+e700000030b3 vrg VRR_VVV0U02 "vector remainder doubleword" arch15 zarch
+e700000040b3 vrq VRR_VVV0U02 "vector remainder quadword" arch15 zarch
+
+e700000000b1 vrl VRR_VVV0UU "vector remainder logical" arch15 zarch
+e700000020b1 vrlf VRR_VVV0U02 "vector remainder logical word" arch15 zarch
+e700000030b1 vrlg VRR_VVV0U02 "vector remainder logical doubleword" arch15 zarch
+e700000040b1 vrlq VRR_VVV0U02 "vector remainder logical quadword" arch15 zarch
+
+# Miscellaneous-Instruction-Extensions Facility 4
+
+b968 clzg RRE_RR "count leading zeros" arch15 zarch
+b969 ctzg RRE_RR "count trailing zeros" arch15 zarch
+
+e30000000060 lxab RXY_RRRD "load indexed address (shift left 0)" arch15 zarch
+e30000000062 lxah RXY_RRRD "load indexed address (shift left 1)" arch15 zarch
+e30000000064 lxaf RXY_RRRD "load indexed address (shift left 2)" arch15 zarch
+e30000000066 lxag RXY_RRRD "load indexed address (shift left 3)" arch15 zarch
+e30000000068 lxaq RXY_RRRD "load indexed address (shift left 4)" arch15 zarch
+
+e30000000061 llxab RXY_RRRD "load logical indexed address (shift left 0)" arch15 zarch
+e30000000063 llxah RXY_RRRD "load logical indexed address (shift left 1)" arch15 zarch
+e30000000065 llxaf RXY_RRRD "load logical indexed address (shift left 2)" arch15 zarch
+e30000000067 llxag RXY_RRRD "load logical indexed address (shift left 3)" arch15 zarch
+e30000000069 llxaq RXY_RRRD "load logical indexed address (shift left 4)" arch15 zarch
+
+b96c bextg RRF_R0RR2 "bit extract" arch15 zarch
+b96d bdepg RRF_R0RR2 "bit deposit" arch15 zarch
+
+# Message-Security-Assist Extension 12
+
+b93e kimd RRF_U0RR "compute intermediate message digest" arch15 zarch optparm
+b93f klmd RRF_U0RR "compute last message digest" arch15 zarch optparm
+
+# Vector-Packed-Decimal-Enhancement Facility 3
+
+e6000000004e vcvbq VRR_VV0U2 "vector convert to binary 128 bit" arch15 zarch
+e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch
+
+e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm
+e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch
--
2.47.0

89
binutils-s390-arch15-16.patch Normal file
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@ -0,0 +1,89 @@
From 76445f36a2f9e41b1744d0327e7ec243cb7fac12 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Mon, 18 Nov 2024 10:42:21 +0100
Subject: [PATCH] s390: Add arch15 Concurrent-Functions Facility insns
Commit: 76445f36a2f9
opcodes/
* s390-opc.txt: Add arch15 Concurrent-Functions Facility
instructions.
* s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF
instruction format variant.
gas/testsuite/
* gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions
Facility instructions.
* gas/s390/zarch-arch15.s: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
gas/testsuite/gas/s390/zarch-arch15.d | 4 ++++
gas/testsuite/gas/s390/zarch-arch15.s | 4 ++++
opcodes/s390-opc.c | 2 ++
opcodes/s390-opc.txt | 8 ++++++++
4 files changed, 18 insertions(+)
diff --git a/gas/testsuite/gas/s390/zarch-arch15.d b/gas/testsuite/gas/s390/zarch-arch15.d
index 955c9706b35..9cd99b7a698 100644
--- a/gas/testsuite/gas/s390/zarch-arch15.d
+++ b/gas/testsuite/gas/s390/zarch-arch15.d
@@ -100,3 +100,7 @@ Disassembly of section .text:
.*: e6 0f 00 00 00 5f [ ]*vtp %v15
.*: e6 0f 0f ff d0 5f [ ]*vtp %v15,65533
.*: e6 0f 1f ff d2 7f [ ]*vtz %v15,%v17,65533
+.*: c8 36 10 0a 20 14 [ ]*cal %r3,10\(%r1\),20\(%r2\)
+.*: c8 37 10 0a 20 14 [ ]*calg %r3,10\(%r1\),20\(%r2\)
+.*: c8 3f 10 0a 20 14 [ ]*calgf %r3,10\(%r1\),20\(%r2\)
+.*: eb 13 28 f0 fd 16 [ ]*pfcr %r1,%r3,-10000\(%r2\)
diff --git a/gas/testsuite/gas/s390/zarch-arch15.s b/gas/testsuite/gas/s390/zarch-arch15.s
index 43be9d46a48..d9b89652fcb 100644
--- a/gas/testsuite/gas/s390/zarch-arch15.s
+++ b/gas/testsuite/gas/s390/zarch-arch15.s
@@ -94,3 +94,7 @@ foo:
vtp %v15
vtp %v15,65533
vtz %v15,%v17,65533
+ cal %r3,10(%r1),20(%r2)
+ calg %r3,10(%r1),20(%r2)
+ calgf %r3,10(%r1),20(%r2)
+ pfcr %r1,%r3,-10000(%r2)
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 49efd714157..23c1c3a24e5 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -468,6 +468,7 @@ unused_s390_operands_static_asserts (void)
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
+#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. cal */
#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */
@@ -700,6 +701,7 @@ unused_s390_operands_static_asserts (void)
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 82d6f06a992..68d8896bf4e 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -2190,3 +2190,11 @@ e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch
e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm
e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch
+
+# Concurrent-Functions Facility
+
+c806 cal SSF_RRDRD2 "compare and load 32" arch15 zarch
+c807 calg SSF_RRDRD2 "compare and load 64" arch15 zarch
+c80f calgf SSF_RRDRD2 "compare and load 64<32" arch15 zarch
+
+eb0000000016 pfcr RSY_RRRD "perform functions with concurrent results" arch15 zarch
--
2.47.0

7
binutils.spec
View File

@ -2,7 +2,7 @@
Summary: A GNU collection of binary utilities Summary: A GNU collection of binary utilities
Name: binutils%{?_with_debug:-debug} Name: binutils%{?_with_debug:-debug}
Version: 2.35.2 Version: 2.35.2
Release: 57%{?dist} Release: 58%{?dist}
License: GPLv3+ License: GPLv3+
URL: https://sourceware.org/binutils URL: https://sourceware.org/binutils
@ -498,6 +498,8 @@ Patch84: binutils-s390-arch15-11.patch
Patch85: binutils-s390-arch15-12.patch Patch85: binutils-s390-arch15-12.patch
Patch86: binutils-s390-arch15-13.patch Patch86: binutils-s390-arch15-13.patch
Patch87: binutils-s390-arch15-14.patch Patch87: binutils-s390-arch15-14.patch
Patch88: binutils-s390-arch15-15.patch
Patch89: binutils-s390-arch15-16.patch
#---------------------------------------------------------------------------- #----------------------------------------------------------------------------
@ -1358,6 +1360,9 @@ exit 0
#---------------------------------------------------------------------------- #----------------------------------------------------------------------------
%changelog %changelog
* Mon Nov 18 2024 Nick Clifton <nickc@redhat.com> - 2.35.2-58
- Extend support for the arch15 and arch16 extensions to the s390 architecture. (RHEL-50068)
* Wed Nov 13 2024 Nick Clifton <nickc@redhat.com> - 2.35.2-57 * Wed Nov 13 2024 Nick Clifton <nickc@redhat.com> - 2.35.2-57
- Add support for the arch15 and arch16 extensions to the s390 architecture. (RHEL-50068) - Add support for the arch15 and arch16 extensions to the s390 architecture. (RHEL-50068)