83 lines
3.7 KiB
Diff
83 lines
3.7 KiB
Diff
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diff -rup binutils.orig/gas/config/tc-aarch64.c binutils-2.30/gas/config/tc-aarch64.c
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--- binutils.orig/gas/config/tc-aarch64.c 2022-04-05 10:30:32.735881142 +0100
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+++ binutils-2.30/gas/config/tc-aarch64.c 2022-04-05 10:31:28.198694747 +0100
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@@ -8553,6 +8553,8 @@ static const struct aarch64_option_cpu_v
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{"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
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| AARCH64_FEATURE_SHA3, 0),
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AARCH64_ARCH_NONE},
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+ {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
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+ AARCH64_ARCH_NONE},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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};
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diff -rup binutils.orig/gas/doc/c-aarch64.texi binutils-2.30/gas/doc/c-aarch64.texi
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--- binutils.orig/gas/doc/c-aarch64.texi 2022-04-05 10:30:32.735881142 +0100
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+++ binutils-2.30/gas/doc/c-aarch64.texi 2022-04-05 10:32:35.814423321 +0100
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@@ -179,6 +179,8 @@ automatically cause those extensions to
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@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
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@tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
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This implies @code{fp16}.
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+@item @code{rng} @tab ARMv8.5-A @tab No
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+ @tab Enable ARMv8.5-A random number instructions.
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@end multitable
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@node AArch64 Syntax
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Only in binutils-2.30/gas/testsuite/gas/aarch64: rng-1.d
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Only in binutils-2.30/gas/testsuite/gas/aarch64: rng-1.s
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diff -rup binutils.orig/include/opcode/aarch64.h binutils-2.30/include/opcode/aarch64.h
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--- binutils.orig/include/opcode/aarch64.h 2022-04-05 10:30:33.256879707 +0100
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+++ binutils-2.30/include/opcode/aarch64.h 2022-04-05 10:42:30.241087320 +0100
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@@ -62,6 +62,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
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#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
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#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
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+#define AARCH64_FEATURE_RNG 0x80000000000ULL /* Random Number instructions. */
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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diff -rup binutils.orig/opcodes/aarch64-opc.c binutils-2.30/opcodes/aarch64-opc.c
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--- binutils.orig/opcodes/aarch64-opc.c 2022-04-05 10:30:33.019880360 +0100
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+++ binutils-2.30/opcodes/aarch64-opc.c 2022-04-05 10:58:07.179526356 +0100
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@@ -3823,6 +3823,8 @@ const aarch64_sys_reg aarch64_sys_regs [
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{ "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
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{ "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
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{ "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
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+ { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT }, /* RO */
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+ { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT }, /* RO */
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{ "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
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{ "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RO */
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{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
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@@ -4254,6 +4256,13 @@ aarch64_sys_reg_supported_p (const aarch
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
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return FALSE;
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+ /* Random Number Instructions. For now they are available
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+ (and optional) only with ARMv8.5-A. */
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+ if (( reg->value == CPENC (3, 3, C2, C4, 0)
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+ || reg->value == CPENC (3, 3, C2, C4, 1))
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+ && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)))
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+ return FALSE;
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+
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return TRUE;
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}
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--- /dev/null 2022-04-05 09:32:54.900867346 +0100
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+++ binutils-2.30/gas/testsuite/gas/aarch64/rng-1.s 2022-04-05 10:36:04.921589937 +0100
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@@ -0,0 +1,3 @@
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+ .arch armv8.4-a+rng
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+ mrs x5, rndr
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+ mrs x6, rndrrs
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--- /dev/null 2022-04-05 09:32:54.900867346 +0100
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+++ binutils-2.30/gas/testsuite/gas/aarch64/rng-1.d 2022-04-05 10:35:48.937653638 +0100
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@@ -0,0 +1,10 @@
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+#source: rng-1.s
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+#objdump: -dr
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+
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+.*: file format .*
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+
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+Disassembly of section \.text:
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+
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+0+ <.*>:
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+.*: d53b2405 mrs x5, rndr
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+.*: d53b2426 mrs x6, rndrrs
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