From 7cf755a92d9e2b7631f9fcd37e86f3e59281d9b8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 5 Sep 2008 05:48:02 +0000 Subject: [PATCH] - latest snapshot - r300 bufmgr code - stop building mach64, patch around some intel issues --- .cvsignore | 2 +- intel-mmio-fix.patch | 57 + ...patch => mesa-7.1-nukeglthread-debug.patch | 13 +- ...ion.patch => mesa-7.1-osmesa-version.patch | 6 +- mesa-fixes.patch | 48 - mesa-no-mach64.patch | 45 + mesa.spec | 29 +- r300-cmdbuf.patch => r300-bufmgr.patch | 1123 ++++++++++------- sources | 2 +- 9 files changed, 780 insertions(+), 545 deletions(-) create mode 100644 intel-mmio-fix.patch rename mesa-7.1pre-nukeglthread-debug.patch => mesa-7.1-nukeglthread-debug.patch (58%) rename mesa-7.1pre-osmesa-version.patch => mesa-7.1-osmesa-version.patch (75%) delete mode 100644 mesa-fixes.patch create mode 100644 mesa-no-mach64.patch rename r300-cmdbuf.patch => r300-bufmgr.patch (93%) diff --git a/.cvsignore b/.cvsignore index ed91d79..3a4010b 100644 --- a/.cvsignore +++ b/.cvsignore @@ -1,2 +1,2 @@ gl-manpages-1.0.1.tar.bz2 -mesa-20080814.tar.bz2 +mesa-20080905.tar.bz2 diff --git a/intel-mmio-fix.patch b/intel-mmio-fix.patch new file mode 100644 index 0000000..4d93c7a --- /dev/null +++ b/intel-mmio-fix.patch @@ -0,0 +1,57 @@ +diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c +index c2ad5a0..18e7348 100644 +--- a/src/mesa/drivers/dri/intel/intel_context.c ++++ b/src/mesa/drivers/dri/intel/intel_context.c +@@ -409,10 +409,12 @@ static const struct dri_extension brw_extensions[] = { + { NULL, NULL } + }; + ++#ifdef I915_MMIO_READ + static const struct dri_extension arb_oc_extensions[] = { + {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, + {NULL, NULL} + }; ++#endif + + static const struct dri_extension ttm_extensions[] = { + {"GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions}, +@@ -437,10 +439,12 @@ void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging) + if (intel == NULL || intel->ttm) + driInitExtensions(ctx, ttm_extensions, GL_FALSE); + ++#ifdef I915_MMIO_READ + if (intel == NULL || + (IS_965(intel->intelScreen->deviceID) && + intel->intelScreen->drmMinor >= 8)) + driInitExtensions(ctx, arb_oc_extensions, GL_FALSE); ++#endif + + if (intel == NULL || IS_965(intel->intelScreen->deviceID)) + driInitExtensions(ctx, brw_extensions, GL_FALSE); +@@ -538,6 +542,7 @@ intelFinish(GLcontext * ctx) + } + } + ++#ifdef I915_MMIO_READ + static void + intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) + { +@@ -568,6 +573,7 @@ intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) + q->Ready = GL_TRUE; + intel->stats_wm--; + } ++#endif + + /** Driver-specific fence emit implementation for the fake memory manager. */ + static unsigned int +@@ -684,8 +690,10 @@ intelInitDriverFunctions(struct dd_function_table *functions) + functions->CopyConvolutionFilter1D = _swrast_CopyConvolutionFilter1D; + functions->CopyConvolutionFilter2D = _swrast_CopyConvolutionFilter2D; + ++#ifdef I915_MMIO_READ + functions->BeginQuery = intelBeginQuery; + functions->EndQuery = intelEndQuery; ++#endif + + intelInitTextureFuncs(functions); + intelInitStateFuncs(functions); diff --git a/mesa-7.1pre-nukeglthread-debug.patch b/mesa-7.1-nukeglthread-debug.patch similarity index 58% rename from mesa-7.1pre-nukeglthread-debug.patch rename to mesa-7.1-nukeglthread-debug.patch index 0ce6298..dc8ad6f 100644 --- a/mesa-7.1pre-nukeglthread-debug.patch +++ b/mesa-7.1-nukeglthread-debug.patch @@ -1,9 +1,8 @@ -diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c -index 94d499f..2ba596e 100644 ---- a/src/mesa/drivers/dri/intel/intel_fbo.c -+++ b/src/mesa/drivers/dri/intel/intel_fbo.c -@@ -615,11 +615,6 @@ intel_render_texture(GLcontext * ctx, - } +diff -up Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c.intel-glthread Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c +--- Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c.intel-glthread 2008-08-25 10:49:40.000000000 -0400 ++++ Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c 2008-08-28 14:26:17.000000000 -0400 +@@ -633,11 +633,6 @@ intel_render_texture(GLcontext * ctx, + return; } - DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", @@ -14,7 +13,7 @@ index 94d499f..2ba596e 100644 /* point the renderbufer's region to the texture image region */ intel_image = intel_texture_image(newImage); if (irb->region != intel_image->mt->region) { -@@ -656,8 +651,6 @@ intel_finish_render_texture(GLcontext * ctx, +@@ -674,8 +669,6 @@ intel_finish_render_texture(GLcontext * { struct intel_renderbuffer *irb = intel_renderbuffer(att->Renderbuffer); diff --git a/mesa-7.1pre-osmesa-version.patch b/mesa-7.1-osmesa-version.patch similarity index 75% rename from mesa-7.1pre-osmesa-version.patch rename to mesa-7.1-osmesa-version.patch index b958f89..cd41ad2 100644 --- a/mesa-7.1pre-osmesa-version.patch +++ b/mesa-7.1-osmesa-version.patch @@ -1,6 +1,6 @@ -diff -up mesa-20080814/src/mesa/drivers/osmesa/Makefile.osmesa mesa-20080814/src/mesa/drivers/osmesa/Makefile ---- mesa-20080814/src/mesa/drivers/osmesa/Makefile.osmesa 2008-08-28 22:33:46.000000000 +1000 -+++ mesa-20080814/src/mesa/drivers/osmesa/Makefile 2008-08-28 22:34:06.000000000 +1000 +diff -up Mesa-7.1/src/mesa/drivers/osmesa/Makefile.jx Mesa-7.1/src/mesa/drivers/osmesa/Makefile +--- Mesa-7.1/src/mesa/drivers/osmesa/Makefile.jx 2008-08-28 14:05:47.000000000 -0400 ++++ Mesa-7.1/src/mesa/drivers/osmesa/Makefile 2008-08-28 14:07:13.000000000 -0400 @@ -46,7 +46,7 @@ osmesa8: $(TOP)/lib/$(OSMESA_LIB_NAME) $(TOP)/lib/$(OSMESA_LIB_NAME): $(OBJECTS) diff --git a/mesa-fixes.patch b/mesa-fixes.patch deleted file mode 100644 index 2abf8e5..0000000 --- a/mesa-fixes.patch +++ /dev/null @@ -1,48 +0,0 @@ -diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c -index 91b835d..ddfdce3 100644 ---- a/src/mesa/drivers/dri/intel/intel_regions.c -+++ b/src/mesa/drivers/dri/intel/intel_regions.c -@@ -455,8 +455,7 @@ static struct intel_region * - intel_recreate_static(struct intel_context *intel, - const char *name, - struct intel_region *region, -- intelRegion *region_desc, -- GLuint mem_type) -+ intelRegion *region_desc) - { - intelScreenPrivate *intelScreen = intel->intelScreen; - int ret; -@@ -537,22 +536,19 @@ intel_recreate_static_regions(struct intel_context *intel) - intel->front_region = - intel_recreate_static(intel, "front", - intel->front_region, -- &intelScreen->front, -- DRM_BO_FLAG_MEM_TT); -+ &intelScreen->front); - - intel->back_region = - intel_recreate_static(intel, "back", - intel->back_region, -- &intelScreen->back, -- DRM_BO_FLAG_MEM_TT); -+ &intelScreen->back); - - #ifdef I915 - if (intelScreen->third.handle) { - intel->third_region = - intel_recreate_static(intel, "third", - intel->third_region, -- &intelScreen->third, -- DRM_BO_FLAG_MEM_TT); -+ &intelScreen->third); - } - #endif /* I915 */ - -@@ -562,6 +558,5 @@ intel_recreate_static_regions(struct intel_context *intel) - intel->depth_region = - intel_recreate_static(intel, "depth", - intel->depth_region, -- &intelScreen->depth, -- DRM_BO_FLAG_MEM_TT); -+ &intelScreen->depth); - } diff --git a/mesa-no-mach64.patch b/mesa-no-mach64.patch new file mode 100644 index 0000000..397531e --- /dev/null +++ b/mesa-no-mach64.patch @@ -0,0 +1,45 @@ +--- configure.ac.mach64 2008-09-05 13:53:24.000000000 +1000 ++++ configure.ac 2008-09-05 13:53:39.000000000 +1000 +@@ -656,7 +656,7 @@ + # because there is no x86-64 system where they could *ever* + # be used. + if test "x$DRI_DIRS" = "xyes"; then +- DRI_DIRS="i915 i965 mach64 mga r128 r200 r300 radeon \ ++ DRI_DIRS="i915 i965 mga r128 r200 r300 radeon \ + savage tdfx unichrome swrast" + fi + ;; +@@ -664,13 +664,13 @@ + # Build only the drivers for cards that exist on PowerPC. + # At some point MGA will be added, but not yet. + if test "x$DRI_DIRS" = "xyes"; then +- DRI_DIRS="mach64 r128 r200 r300 radeon tdfx swrast" ++ DRI_DIRS="r128 r200 r300 radeon tdfx swrast" + fi + ;; + sparc*) + # Build only the drivers for cards that exist on sparc` + if test "x$DRI_DIRS" = "xyes"; then +- DRI_DIRS="mach64 r128 r200 r300 radeon ffb swrast" ++ DRI_DIRS="r128 r200 r300 radeon ffb swrast" + fi + ;; + esac +@@ -689,7 +689,7 @@ + # ffb and gamma are missing because they have not been converted + # to use the new interface. + if test "x$DRI_DIRS" = "xyes"; then +- DRI_DIRS="i810 i915 i965 mach64 mga r128 r200 r300 radeon tdfx \ ++ DRI_DIRS="i810 i915 i965 mga r128 r200 r300 radeon tdfx \ + unichrome savage sis swrast" + fi + ;; +@@ -704,7 +704,7 @@ + + # default drivers + if test "x$DRI_DIRS" = "xyes"; then +- DRI_DIRS="i810 i915 i965 mach64 mga r128 r200 r300 radeon s3v \ ++ DRI_DIRS="i810 i915 i965 mga r128 r200 r300 radeon s3v \ + savage sis tdfx trident unichrome ffb swrast" + fi + diff --git a/mesa.spec b/mesa.spec index b8a850e..ccd5cd5 100644 --- a/mesa.spec +++ b/mesa.spec @@ -12,12 +12,12 @@ %define _default_patch_fuzz 2 %define manpages gl-manpages-1.0.1 -%define gitdate 20080814 +%define gitdate 20080905 Summary: Mesa graphics libraries Name: mesa -Version: 7.1 -Release: 0.38%{?dist} +Version: 7.2 +Release: 0.1%{?dist} License: MIT Group: System Environment/Libraries URL: http://www.mesa3d.org @@ -29,13 +29,14 @@ Source0: %{name}-%{gitdate}.tar.bz2 Source2: %{manpages}.tar.bz2 Source3: make-git-snapshot.sh -Patch0: mesa-7.1pre-osmesa-version.patch -Patch1: mesa-fixes.patch -Patch2: mesa-7.1pre-nukeglthread-debug.patch +Patch0: mesa-7.1-osmesa-version.patch +Patch2: mesa-7.1-nukeglthread-debug.patch +Patch3: mesa-no-mach64.patch -Patch5: r300-cmdbuf.patch +Patch5: r300-bufmgr.patch Patch7: mesa-7.1-link-shared.patch +Patch8: intel-mmio-fix.patch Patch12: mesa-7.1-disable-intel-classic-warn.patch @@ -164,10 +165,11 @@ This package provides some demo applications for testing Mesa. #%setup -q -n Mesa-%{version}pre -b1 -b2 %setup -q -n mesa-%{gitdate} -b2 %patch0 -p1 -b .osmesa -%patch1 -p1 -b .fixes %patch2 -p1 -b .intel-glthread -%patch5 -p1 -b .r300cmdbuf +%patch3 -p0 -b .no-mach64 +%patch5 -p1 -b .r300-bufmgr %patch7 -p1 -b .dricore +%patch8 -p1 -b .intel-mmio %patch12 -p1 -b .intel-nowarn # WARNING: The following files are copyright "Mark J. Kilgard" under the GLUT @@ -240,7 +242,7 @@ make install DESTDIR=$RPM_BUILD_ROOT DRI_DIRS= %if %{with_dri} install -d $RPM_BUILD_ROOT%{_libdir}/dri install -m 0755 -t $RPM_BUILD_ROOT%{_libdir}/dri %{_lib}/libdricore.so >& /dev/null -for f in i810 i915 i965 mach64 mga r128 r200 r300 radeon savage sis swrast tdfx unichrome; do +for f in i810 i915 i965 mga r128 r200 r300 radeon savage sis swrast tdfx unichrome; do so=%{_lib}/${f}_dri.so test -e $so && echo $so done | xargs install -m 0755 -t $RPM_BUILD_ROOT%{_libdir}/dri >& /dev/null || : @@ -308,8 +310,8 @@ rm -rf $RPM_BUILD_ROOT %{_includedir}/GL/xmesa_xf86.h %dir %{_includedir}/GL/internal %{_includedir}/GL/internal/dri_interface.h -%{_includedir}/GL/internal/dri_sarea.h %{_libdir}/libGL.so +%{_libdir}/pkgconfig/dri.pc %{_libdir}/pkgconfig/gl.pc %{_datadir}/man/man3/gl[^uX]*.3gl* %{_datadir}/man/man3/glX*.3gl* @@ -356,6 +358,7 @@ rm -rf $RPM_BUILD_ROOT %{_bindir}/cubemap %{_bindir}/drawpix %{_bindir}/engine +%{_bindir}/fbo_firecube %{_bindir}/fire %{_bindir}/fogcoord %{_bindir}/fplight @@ -402,6 +405,10 @@ rm -rf $RPM_BUILD_ROOT %{_libdir}/mesa-demos-data %changelog +* Fri Sep 05 2008 Dave Airlie 7.2-0.1 +- latest snapshot - r300 bufmgr code +- stop building mach64, patch around some intel issues + * Thu Aug 28 2008 Dave Airlie 7.1-0.38 - latest Mesa snapshot - re-enable tex offset - add r300 command buffer support on top of snapshot diff --git a/r300-cmdbuf.patch b/r300-bufmgr.patch similarity index 93% rename from r300-cmdbuf.patch rename to r300-bufmgr.patch index 50eb918..09c2e95 100644 --- a/r300-cmdbuf.patch +++ b/r300-bufmgr.patch @@ -60,7 +60,7 @@ index 6ca9342..3bb1ff4 100644 ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c -index c069660..493b0ac 100644 +index c069660..dd42bf8 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -51,11 +51,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -124,7 +124,7 @@ index c069660..493b0ac 100644 + } + + dri_bo_unmap(r300->cmdbuf.buf); -+ dri_process_relocs(r300->cmdbuf.buf, 0); ++ dri_process_relocs(r300->cmdbuf.buf); + + cmd.buf = (char *)r300->cmdbuf.buf->virtual + 4*start; + cmd.bufsz = (r300->cmdbuf.committed - start) * 4; @@ -135,14 +135,14 @@ index c069660..493b0ac 100644 radeonWaitForIdleLocked(&r300->radeon); } -+ dri_post_submit(r300->cmdbuf.buf, 0); ++ dri_post_submit(r300->cmdbuf.buf); + dri_bo_unreference(r300->cmdbuf.buf); + r300->dma.nr_released_bufs = 0; - r300->cmdbuf.count_used = 0; - r300->cmdbuf.count_reemit = 0; -+ r300->cmdbuf.buf = dri_bo_alloc(&r300->radeon.bufmgr->base, "cmdbuf", -+ r300->cmdbuf.size*4, 16, DRM_BO_MEM_CMDBUF); ++ r300->cmdbuf.buf = radeon_bufmgr_classic_bo_alloc(&r300->radeon.bufmgr->base, "cmdbuf", ++ r300->cmdbuf.size*4, 16, DRM_BO_MEM_CMDBUF); + r300->cmdbuf.written = 0; + r300->cmdbuf.reserved = 0; + r300->cmdbuf.committed = 0; @@ -426,7 +426,7 @@ index c069660..493b0ac 100644 size * 4, r300->hw.max_state_size * 4); } -+ r300->cmdbuf.buf = dri_bo_alloc(&r300->radeon.bufmgr->base, "cmdbuf", ++ r300->cmdbuf.buf = radeon_bufmgr_classic_bo_alloc(&r300->radeon.bufmgr->base, "cmdbuf", + size*4, 16, DRM_BO_MEM_CMDBUF); r300->cmdbuf.size = size; - r300->cmdbuf.cmd_buf = (uint32_t *) CALLOC(size * 4); @@ -510,7 +510,7 @@ index c069660..493b0ac 100644 - cmd[0].wait.flags = flags; -} diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h -index a8eaa58..4708a4c 100644 +index a8eaa58..5c84b67 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -45,29 +45,88 @@ extern void r300EmitState(r300ContextPtr r300); @@ -573,7 +573,7 @@ index a8eaa58..4708a4c 100644 +#define OUT_BATCH_RELOC(data, bo, offset, flags) \ + do { \ + if (b_l_r300->cmdbuf.written < b_l_r300->cmdbuf.reserved) { \ -+ dri_emit_reloc(b_l_r300->cmdbuf.buf, flags, offset, 4*b_l_r300->cmdbuf.written, bo); \ ++ radeon_bufmgr_classic_emit_reloc(b_l_r300->cmdbuf.buf, flags, offset, 4*b_l_r300->cmdbuf.written, bo); \ + ((uint32_t*)b_l_r300->cmdbuf.buf->virtual)[b_l_r300->cmdbuf.written++] = data; \ + } else { \ + _mesa_problem(b_l_r300->radeon.glCtx, "%s:%i: OUT_BATCH mismatch", __FUNCTION__, __LINE__); \ @@ -666,7 +666,7 @@ index a8eaa58..4708a4c 100644 - #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c -index fcf571d..cc9c11a 100644 +index fcf571d..6c6b5ba 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -59,15 +59,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -859,7 +859,7 @@ index fcf571d..cc9c11a 100644 r300DestroyCmdBuf(r300); if (radeon->state.scissor.pClipRects) { -@@ -521,28 +416,13 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) +@@ -521,29 +416,14 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) radeon->state.scissor.pClipRects = NULL; } @@ -880,18 +880,22 @@ index fcf571d..cc9c11a 100644 radeonCleanupContext(&r300->radeon); -#ifdef USER_BUFFERS - /* the memory manager might be accessed when Mesa frees the shared - * state, so don't destroy it earlier - */ +- /* the memory manager might be accessed when Mesa frees the shared +- * state, so don't destroy it earlier +- */ - r300_mem_destroy(r300); -#endif -+ dri_bufmgr_destroy(&r300->radeon.bufmgr->base); -+ r300->radeon.bufmgr = 0; ++ /* the memory manager might be accessed when Mesa frees the shared ++ * state, so don't destroy it earlier ++ */ ++ dri_bufmgr_destroy(&r300->radeon.bufmgr->base); ++ r300->radeon.bufmgr = 0; /* free the option cache */ driDestroyOptionCache(&r300->radeon.optionCache); + diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h -index d2017f8..5c99740 100644 +index d2017f8..047caae 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -40,6 +40,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -968,7 +972,7 @@ index d2017f8..5c99740 100644 /* Number of "in-flight" DMA buffers, i.e. the number of buffers * for which a DISCARD command is currently queued in the command buffer. */ -@@ -173,15 +151,12 @@ typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr; +@@ -173,17 +151,13 @@ typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr; /* Texture object in locally shared texture space. */ struct r300_tex_obj { @@ -986,9 +990,11 @@ index d2017f8..5c99740 100644 GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ + GLuint override_offset; - GLuint pitch; /* this isn't sent to hardware just used in calculations */ +- GLuint pitch; /* this isn't sent to hardware just used in calculations */ /* hardware register values */ -@@ -191,30 +166,16 @@ struct r300_tex_obj { + /* Note that R200 has 8 registers per texture and R300 only 7 */ + GLuint filter; +@@ -191,30 +165,16 @@ struct r300_tex_obj { GLuint pitch_reg; GLuint size; /* npot only */ GLuint format; @@ -1024,7 +1030,7 @@ index d2017f8..5c99740 100644 /* The blit width for texture uploads */ -@@ -222,7 +183,6 @@ struct r300_texture_env_state { +@@ -222,7 +182,6 @@ struct r300_texture_env_state { #define R300_MAX_TEXTURE_UNITS 8 struct r300_texture_state { @@ -1032,7 +1038,7 @@ index d2017f8..5c99740 100644 int tc_count; /* number of incoming texture coordinates from VAP */ }; -@@ -242,6 +202,7 @@ struct r300_state_atom { +@@ -242,6 +201,7 @@ struct r300_state_atom { GLboolean dirty; int (*check) (r300ContextPtr, struct r300_state_atom * atom); @@ -1040,7 +1046,7 @@ index d2017f8..5c99740 100644 }; #define R300_VPT_CMD_0 0 -@@ -549,6 +510,8 @@ struct r300_hw_state { +@@ -549,6 +509,8 @@ struct r300_hw_state { struct r300_state_atom border_color; } tex; struct r300_state_atom txe; /* tex enable (4104) */ @@ -1049,7 +1055,7 @@ index d2017f8..5c99740 100644 }; /** -@@ -559,10 +522,14 @@ struct r300_hw_state { +@@ -559,10 +521,14 @@ struct r300_hw_state { * otherwise. */ struct r300_cmdbuf { @@ -1068,7 +1074,7 @@ index d2017f8..5c99740 100644 }; /** -@@ -811,18 +778,25 @@ struct r500_fragment_program { +@@ -811,18 +777,25 @@ struct r500_fragment_program { #define REG_COLOR0 1 #define REG_TEX0 2 @@ -1098,7 +1104,7 @@ index d2017f8..5c99740 100644 DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for. They are the same as tnl->render_inputs for fixed pipeline */ -@@ -880,13 +854,6 @@ struct r300_swtcl_info { +@@ -880,13 +853,6 @@ struct r300_swtcl_info { * Offset of the 3UB specular color data within a hardware (swtcl) vertex. */ GLuint specoffset; @@ -1112,7 +1118,7 @@ index d2017f8..5c99740 100644 }; -@@ -905,25 +872,11 @@ struct r300_context { +@@ -905,25 +871,11 @@ struct r300_context { /* Vertex buffers */ struct r300_dma dma; @@ -1604,7 +1610,7 @@ index 5950539..179983d 100644 + #endif diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c -index bd7f060..046f9a2 100644 +index bd7f060..2b8b266 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -55,6 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -2386,7 +2392,7 @@ index bd7f060..046f9a2 100644 - - region->buf = 0; - region->start = 0; -+ rmesa->dma.current = dri_bo_alloc(&rmesa->radeon.bufmgr->base, "DMA regions", ++ rmesa->dma.current = radeon_bufmgr_classic_bo_alloc(&rmesa->radeon.bufmgr->base, "DMA regions", + size, 4, DRM_BO_MEM_DMA); + rmesa->dma.current_used = 0; + rmesa->dma.current_vertexptr = 0; @@ -2648,10 +2654,10 @@ index e1143fb..c743478 100644 extern void r300InitIoctlFuncs(struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/r300/r300_mem.c b/src/mesa/drivers/dri/r300/r300_mem.c -index f8f9d4f..b045393 100644 +index f8f9d4f..1097388 100644 --- a/src/mesa/drivers/dri/r300/r300_mem.c +++ b/src/mesa/drivers/dri/r300/r300_mem.c -@@ -27,359 +27,843 @@ +@@ -27,359 +27,869 @@ /** * \file @@ -2721,12 +2727,20 @@ index f8f9d4f..b045393 100644 + void (*validate)(radeon_bo_classic*); + + /** -+ * Called when a writing map of the buffer is taken, to note that -+ * the buffer will have to be re-validated. ++ * Map the buffer for CPU access. ++ * Only called when the buffer isn't already mapped. + * -+ * May be null for buffer objects that don't need it. ++ * May be null. + */ -+ void (*dirty)(radeon_bo_classic*); ++ void (*map)(radeon_bo_classic*, GLboolean write); ++ ++ /** ++ * Unmap the buffer. ++ * Only called on final unmap. ++ * ++ * May be null. ++ */ ++ void (*unmap)(radeon_bo_classic*); + + /** + * Indicate that the buffer object is now used by the hardware. @@ -2788,12 +2802,12 @@ index f8f9d4f..b045393 100644 - } + unsigned int validated:1; /** whether the buffer is validated for hardware use right now */ + unsigned int used:1; /* only for communication between process_relocs and post_submit */ -+ + +- rmesa->rmm->u_size = nsize; + unsigned int pending:1; + radeon_bo_classic *pending_next; /** Age-sorted linked list of pending buffer objects */ + radeon_bo_classic **pending_pprev; - -- rmesa->rmm->u_size = nsize; ++ + /* The following two variables are intricately linked to the DRM interface, + * and must be in this physical memory order, or else chaos ensues. + * See the DRM's implementation of R300_CMD_SCRATCH for details. @@ -2981,9 +2995,7 @@ index f8f9d4f..b045393 100644 - static int bytes_wasted = 0, allocated = 0; + int baseoffset; + int ret; - -- if (size < 4096) -- bytes_wasted += 4096 - size; ++ + alloc.region = RADEON_MEM_REGION_GART; + alloc.alignment = alignment; + alloc.size = size; @@ -2997,10 +3009,15 @@ index f8f9d4f..b045393 100644 + return 0; + } -- allocated += size; +- if (size < 4096) +- bytes_wasted += 4096 - size; + bo->base.virtual = (char*)bufmgr->rmesa->radeon.radeonScreen->gartTextures.map + baseoffset; + bo->base.offset = bufmgr->rmesa->radeon.radeonScreen->gart_texture_offset + baseoffset; +- allocated += size; ++ return 1; ++} + -#if 0 - static int t = 0; - if (t != time(NULL)) { @@ -3008,9 +3025,6 @@ index f8f9d4f..b045393 100644 - fprintf(stderr, "slots used %d, wasted %d kb, allocated %d\n", - rmesa->rmm->u_last, bytes_wasted / 1024, - allocated / 1024); -+ return 1; -+} -+ +/** + * Allocate a DMA buffer. + */ @@ -3045,8 +3059,7 @@ index f8f9d4f..b045393 100644 - again: + return &bo->base; +} - -- done_age = radeonGetAge((radeonContextPtr) rmesa); ++ +/** + * Free a command buffer + */ @@ -3056,16 +3069,13 @@ index f8f9d4f..b045393 100644 + free(bo); +} -- if (rmesa->rmm->u_last + 1 >= rmesa->rmm->u_size) -- resize_u_list(rmesa); +- done_age = radeonGetAge((radeonContextPtr) rmesa); +static const radeon_bo_functions cmdbuf_bo_functions = { + .free = cmdbuf_free +}; -- for (i = rmesa->rmm->u_last + 1; i > 0; i--) { -- if (rmesa->rmm->u_list[i].ptr == NULL) { -- free = i; -- continue; +- if (rmesa->rmm->u_last + 1 >= rmesa->rmm->u_size) +- resize_u_list(rmesa); +/** + * Allocate a command buffer. + * @@ -3076,25 +3086,75 @@ index f8f9d4f..b045393 100644 + unsigned long size) +{ + radeon_bo_classic* bo = (radeon_bo_classic*)calloc(1, sizeof(radeon_bo_classic)); -+ + +- for (i = rmesa->rmm->u_last + 1; i > 0; i--) { +- if (rmesa->rmm->u_list[i].ptr == NULL) { +- free = i; +- continue; +- } + bo->functions = &cmdbuf_bo_functions; + bo->base.virtual = malloc(size); -+ + +- if (rmesa->rmm->u_list[i].h_pending == 0 && +- rmesa->rmm->u_list[i].pending +- && rmesa->rmm->u_list[i].age <= done_age) { +- memfree.region_offset = +- (char *)rmesa->rmm->u_list[i].ptr - +- (char *)rmesa->radeon.radeonScreen->gartTextures. +- map; + init_buffer(bufmgr, bo, size); + return &bo->base; +} -+ + +- ret = +- drmCommandWrite(rmesa->radeon.radeonScreen-> +- driScreen->fd, DRM_RADEON_FREE, +- &memfree, sizeof(memfree)); +/** + * Free a VRAM-based buffer object. + */ +static void vram_free(radeon_bo_classic *bo_base) +{ + radeon_bo_vram *bo = get_bo_vram(bo_base); -+ + +- if (ret) { +- fprintf(stderr, "Failed to free at %p\n", +- rmesa->rmm->u_list[i].ptr); +- fprintf(stderr, "ret = %s\n", strerror(-ret)); +- exit(1); +- } else { +-#ifdef MM_DEBUG +- fprintf(stderr, "really freed %d at age %x\n", +- i, +- radeonGetAge((radeonContextPtr) rmesa)); +-#endif +- if (i == rmesa->rmm->u_last) +- rmesa->rmm->u_last--; +- +- if (rmesa->rmm->u_list[i].size < 4096) +- bytes_wasted -= +- 4096 - rmesa->rmm->u_list[i].size; +- +- allocated -= rmesa->rmm->u_list[i].size; +- rmesa->rmm->u_list[i].pending = 0; +- rmesa->rmm->u_list[i].ptr = NULL; +- free = i; +- } +- } + if (bo->vram) { + driDestroyTextureObject(&bo->vram->base); + bo->vram = 0; -+ } + } +- rmesa->rmm->u_head = i; +- +- if (free == -1) { +- WARN_ONCE("Ran out of slots!\n"); +- //usleep(100); +- r300FlushCmdBuf(rmesa, __FUNCTION__); +- tries++; +- if (tries > 100) { +- WARN_ONCE("Ran out of slots!\n"); +- exit(1); + + free(bo->base.base.virtual); + free(bo); @@ -3124,129 +3184,14 @@ index f8f9d4f..b045393 100644 + bo->vram = 0; + return; } -+ } -+ -+ assert(bo->vram->base.memBlock); -+ -+ bo->base.base.offset = bufmgr->texture_offset + bo->vram->base.memBlock->ofs; -+ -+ if (bo->backing_store_dirty) { -+ /* Copy to VRAM using a blit. -+ * All memory is 4K aligned. We're using 1024 pixels wide blits. -+ */ -+ drm_radeon_texture_t tex; -+ drm_radeon_tex_image_t tmp; -+ int ret; - -- if (rmesa->rmm->u_list[i].h_pending == 0 && -- rmesa->rmm->u_list[i].pending -- && rmesa->rmm->u_list[i].age <= done_age) { -- memfree.region_offset = -- (char *)rmesa->rmm->u_list[i].ptr - -- (char *)rmesa->radeon.radeonScreen->gartTextures. -- map; -+ tex.offset = bo->base.base.offset; -+ tex.image = &tmp; - -- ret = -- drmCommandWrite(rmesa->radeon.radeonScreen-> -- driScreen->fd, DRM_RADEON_FREE, -- &memfree, sizeof(memfree)); -+ assert(!(tex.offset & 1023)); - -+ tmp.x = 0; -+ tmp.y = 0; -+ if (bo->base.base.size < 4096) { -+ tmp.width = (bo->base.base.size + 3) / 4; -+ tmp.height = 1; -+ } else { -+ tmp.width = 1024; -+ tmp.height = (bo->base.base.size + 4095) / 4096; -+ } -+ tmp.data = bo->base.base.virtual; -+ -+ tex.format = RADEON_TXFORMAT_ARGB8888; -+ tex.width = tmp.width; -+ tex.height = tmp.height; -+ tex.pitch = MAX2(tmp.width / 16, 1); -+ -+ do { -+ ret = drmCommandWriteRead(bufmgr->rmesa->radeon.dri.fd, -+ DRM_RADEON_TEXTURE, &tex, -+ sizeof(drm_radeon_texture_t)); - if (ret) { -- fprintf(stderr, "Failed to free at %p\n", -- rmesa->rmm->u_list[i].ptr); -- fprintf(stderr, "ret = %s\n", strerror(-ret)); -- exit(1); -- } else { --#ifdef MM_DEBUG -- fprintf(stderr, "really freed %d at age %x\n", -- i, -- radeonGetAge((radeonContextPtr) rmesa)); --#endif -- if (i == rmesa->rmm->u_last) -- rmesa->rmm->u_last--; -- -- if (rmesa->rmm->u_list[i].size < 4096) -- bytes_wasted -= -- 4096 - rmesa->rmm->u_list[i].size; -- -- allocated -= rmesa->rmm->u_list[i].size; -- rmesa->rmm->u_list[i].pending = 0; -- rmesa->rmm->u_list[i].ptr = NULL; -- free = i; -+ if (RADEON_DEBUG & DEBUG_IOCTL) -+ fprintf(stderr, -+ "DRM_RADEON_TEXTURE: again!\n"); -+ usleep(1); - } -- } -+ } while (ret == -EAGAIN); -+ -+ bo->backing_store_dirty = 0; - } -- rmesa->rmm->u_head = i; -- -- if (free == -1) { -- WARN_ONCE("Ran out of slots!\n"); -- //usleep(100); -- r300FlushCmdBuf(rmesa, __FUNCTION__); -- tries++; -- if (tries > 100) { -- WARN_ONCE("Ran out of slots!\n"); -- exit(1); -- } - goto again; -+ -+ bo->base.validated = 1; -+} -+ -+static void vram_dirty(radeon_bo_classic *bo_base) -+{ -+ radeon_bo_vram *bo = get_bo_vram(bo_base); -+ -+ bo->base.validated = 0; -+ bo->backing_store_dirty = 1; -+} -+ -+static void vram_bind(radeon_bo_classic *bo_base) -+{ -+ radeon_bo_vram *bo = get_bo_vram(bo_base); -+ -+ if (bo->vram) { -+ bo->vram->base.bound = 1; -+ driUpdateTextureLRU(&bo->vram->base); } -+} - alloc.region = RADEON_MEM_REGION_GART; - alloc.alignment = alignment; - alloc.size = size; - alloc.region_offset = &offset; -+static void vram_unbind(radeon_bo_classic *bo_base) -+{ -+ radeon_bo_vram *bo = get_bo_vram(bo_base); ++ assert(bo->vram->base.memBlock); - ret = - drmCommandWriteRead(rmesa->radeon.dri.fd, DRM_RADEON_ALLOC, &alloc, @@ -3261,7 +3206,30 @@ index f8f9d4f..b045393 100644 - if (tries2 > 100) { - WARN_ONCE("Ran out of GART memory!\n"); - exit(1); -- } ++ bo->base.base.offset = bufmgr->texture_offset + bo->vram->base.memBlock->ofs; ++ ++ if (bo->backing_store_dirty) { ++ /* Copy to VRAM using a blit. ++ * All memory is 4K aligned. We're using 1024 pixels wide blits. ++ */ ++ drm_radeon_texture_t tex; ++ drm_radeon_tex_image_t tmp; ++ int ret; ++ ++ tex.offset = bo->base.base.offset; ++ tex.image = &tmp; ++ ++ assert(!(tex.offset & 1023)); ++ ++ tmp.x = 0; ++ tmp.y = 0; ++ if (bo->base.base.size < 4096) { ++ tmp.width = (bo->base.base.size + 3) / 4; ++ tmp.height = 1; ++ } else { ++ tmp.width = 1024; ++ tmp.height = (bo->base.base.size + 4095) / 4096; + } - goto again; -#else - WARN_ONCE @@ -3269,36 +3237,37 @@ index f8f9d4f..b045393 100644 - size); - return 0; -#endif -+ if (bo->vram) -+ bo->vram->base.bound = 0; -+} ++ tmp.data = bo->base.base.virtual; + -+/** Callback function called by the texture heap when a texture is evicted */ -+static void destroy_vram_wrapper(void *data, driTextureObject *t) -+{ -+ radeon_vram_wrapper *wrapper = (radeon_vram_wrapper*)t; ++ tex.format = RADEON_TXFORMAT_ARGB8888; ++ tex.width = tmp.width; ++ tex.height = tmp.height; ++ tex.pitch = MAX2(tmp.width / 16, 1); + -+ if (wrapper->bo && wrapper->bo->vram == wrapper) { -+ wrapper->bo->base.validated = 0; -+ wrapper->bo->vram = 0; ++ do { ++ ret = drmCommandWriteRead(bufmgr->rmesa->radeon.dri.fd, ++ DRM_RADEON_TEXTURE, &tex, ++ sizeof(drm_radeon_texture_t)); ++ if (ret) { ++ if (RADEON_DEBUG & DEBUG_IOCTL) ++ fprintf(stderr, ++ "DRM_RADEON_TEXTURE: again!\n"); ++ usleep(1); ++ } ++ } while (ret == -EAGAIN); ++ ++ bo->backing_store_dirty = 0; } -+} - i = free; -+static const radeon_bo_functions vram_bo_functions = { -+ .free = vram_free, -+ .validate = vram_validate, -+ .dirty = vram_dirty, -+ .bind = vram_bind, -+ .unbind = vram_unbind -+}; ++ bo->base.validated = 1; ++} - if (i > rmesa->rmm->u_last) - rmesa->rmm->u_last = i; -+/** -+ * Free a VRAM-based buffer object. -+ */ -+static void static_free(radeon_bo_classic *bo_base) ++/* No need for actual mmap actions since we have backing store, ++ * but mark buffer dirty when necessary */ ++static void vram_map(radeon_bo_classic *bo_base, GLboolean write) +{ + radeon_bo_vram *bo = get_bo_vram(bo_base); @@ -3307,24 +3276,29 @@ index f8f9d4f..b045393 100644 - rmesa->rmm->u_list[i].size = size; - rmesa->rmm->u_list[i].age = 0; - //fprintf(stderr, "alloc %p at id %d\n", rmesa->rmm->u_list[i].ptr, i); -+ free(bo); ++ if (write) { ++ bo->base.validated = 0; ++ bo->backing_store_dirty = 1; ++ } +} -#ifdef MM_DEBUG - fprintf(stderr, "allocated %d at age %x\n", i, - radeonGetAge((radeonContextPtr) rmesa)); -#endif -+static void static_bind(radeon_bo_classic *bo_base) ++static void vram_bind(radeon_bo_classic *bo_base) +{ -+} ++ radeon_bo_vram *bo = get_bo_vram(bo_base); - return i; -+static void static_unbind(radeon_bo_classic *bo_base) -+{ ++ if (bo->vram) { ++ bo->vram->base.bound = 1; ++ driUpdateTextureLRU(&bo->vram->base); ++ } } -void r300_mem_use(r300ContextPtr rmesa, int id) -+static void static_validate(radeon_bo_classic *bo_base) ++static void vram_unbind(radeon_bo_classic *bo_base) { - uint64_t ull; -#ifdef MM_DEBUG @@ -3332,22 +3306,25 @@ index f8f9d4f..b045393 100644 - radeonGetAge((radeonContextPtr) rmesa)); -#endif - drm_r300_cmd_header_t *cmd; -+} ++ radeon_bo_vram *bo = get_bo_vram(bo_base); - assert(id <= rmesa->rmm->u_last); -+static void static_dirty(radeon_bo_classic *bo_base) -+{ ++ if (bo->vram) ++ bo->vram->base.bound = 0; +} - if (id == 0) - return; -+static const radeon_bo_functions static_bo_functions = { -+ .free = static_free, -+ .validate = static_validate, -+ .dirty = static_dirty, -+ .bind = static_bind, -+ .unbind = static_unbind -+}; ++/** Callback function called by the texture heap when a texture is evicted */ ++static void destroy_vram_wrapper(void *data, driTextureObject *t) ++{ ++ radeon_vram_wrapper *wrapper = (radeon_vram_wrapper*)t; ++ ++ if (wrapper->bo && wrapper->bo->vram == wrapper) { ++ wrapper->bo->base.validated = 0; ++ wrapper->bo->vram = 0; ++ } ++} - cmd = - (drm_r300_cmd_header_t *) r300AllocCmdBuf(rmesa, @@ -3358,32 +3335,95 @@ index f8f9d4f..b045393 100644 - cmd[0].scratch.n_bufs = 1; - cmd[0].scratch.flags = 0; - cmd++; ++static const radeon_bo_functions vram_bo_functions = { ++ .free = vram_free, ++ .validate = vram_validate, ++ .map = vram_map, ++ .bind = vram_bind, ++ .unbind = vram_unbind ++}; - ull = (uint64_t) (intptr_t) & rmesa->rmm->u_list[id].age; - _mesa_memcpy(cmd, &ull, sizeof(ull)); - cmd += sizeof(ull) / 4; +/** ++ * Free a VRAM-based buffer object. ++ */ ++static void static_free(radeon_bo_classic *bo_base) ++{ ++ radeon_bo_vram *bo = get_bo_vram(bo_base); + +- cmd[0].u = /*id */ 0; ++ free(bo); ++} + +- LOCK_HARDWARE(&rmesa->radeon); /* Protect from DRM. */ +- rmesa->rmm->u_list[id].h_pending++; +- UNLOCK_HARDWARE(&rmesa->radeon); ++static void static_map(radeon_bo_classic *bo_base, GLboolean write) ++{ ++ radeon_bufmgr_classic *bufmgr = get_bufmgr_classic(bo_base->base.bufmgr); ++ ++ bo_base->base.virtual = bufmgr->rmesa->radeon.dri.screen->pFB + ++ (bo_base->base.offset - bufmgr->rmesa->radeon.radeonScreen->fbLocation); ++ ++ /* Read the first pixel in the frame buffer. This should ++ * be a noop, right? In fact without this conform fails as reading ++ * from the framebuffer sometimes produces old results -- the ++ * on-card read cache gets mixed up and doesn't notice that the ++ * framebuffer has been updated. ++ * ++ * Note that we should probably be reading some otherwise unused ++ * region of VRAM, otherwise we might get incorrect results when ++ * reading pixels from the top left of the screen. ++ * ++ * I found this problem on an R420 with glean's texCube test. ++ * Note that the R200 span code also *writes* the first pixel in the ++ * framebuffer, but I've found this to be unnecessary. ++ * -- Nicolai Hähnle, June 2008 ++ */ ++ { ++ int p; ++ volatile int *buf = (int*)bufmgr->rmesa->radeon.dri.screen->pFB; ++ p = *buf; ++ } + } + +-unsigned long r300_mem_offset(r300ContextPtr rmesa, int id) ++static void static_unmap(radeon_bo_classic *bo_base) + { +- unsigned long offset; ++ bo_base->base.virtual = 0; ++} ++ ++static const radeon_bo_functions static_bo_functions = { ++ .free = static_free, ++ .map = static_map, ++ .unmap = static_unmap ++}; + +- assert(id <= rmesa->rmm->u_last); ++/** + * Allocate a backing store buffer object that is validated into VRAM. + */ +static dri_bo *vram_alloc(radeon_bufmgr_classic *bufmgr, const char *name, + unsigned long size, unsigned int alignment) +{ + radeon_bo_vram* bo = (radeon_bo_vram*)calloc(1, sizeof(radeon_bo_vram)); -+ + +- offset = (char *)rmesa->rmm->u_list[id].ptr - +- (char *)rmesa->radeon.radeonScreen->gartTextures.map; +- offset += rmesa->radeon.radeonScreen->gart_texture_offset; + bo->base.functions = &vram_bo_functions; + bo->base.base.virtual = malloc(size); + init_buffer(bufmgr, &bo->base, size); + return &bo->base.base; +} -- cmd[0].u = /*id */ 0; - -- LOCK_HARDWARE(&rmesa->radeon); /* Protect from DRM. */ -- rmesa->rmm->u_list[id].h_pending++; -- UNLOCK_HARDWARE(&rmesa->radeon); -+static dri_bo *bufmgr_classic_bo_alloc(dri_bufmgr *bufmgr_ctx, const char *name, -+ unsigned long size, unsigned int alignment, -+ uint64_t location_mask) +- return offset; ++dri_bo *radeon_bufmgr_classic_bo_alloc(dri_bufmgr *bufmgr_ctx, const char *name, ++ unsigned long size, unsigned int alignment, ++ uint32_t location_mask) +{ + radeon_bufmgr_classic* bufmgr = get_bufmgr_classic(bufmgr_ctx); + @@ -3396,34 +3436,10 @@ index f8f9d4f..b045393 100644 + } } --unsigned long r300_mem_offset(r300ContextPtr rmesa, int id) -+static dri_bo *bufmgr_classic_bo_alloc_static(dri_bufmgr *bufmgr_ctx, const char *name, -+ unsigned long offset, unsigned long size, -+ void *virtual, uint64_t location_mask) - { -- unsigned long offset; -+ radeon_bufmgr_classic* bufmgr = get_bufmgr_classic(bufmgr_ctx); -+ radeon_bo_vram* bo = (radeon_bo_vram*)calloc(1, sizeof(radeon_bo_vram)); - -- assert(id <= rmesa->rmm->u_last); -+ bo->base.functions = &static_bo_functions; -+ bo->base.base.virtual = virtual; -+ bo->base.base.offset = offset + bufmgr->rmesa->radeon.radeonScreen->fbLocation; -+ bo->base.validated = 1; /* Static buffer offsets are always valid */ - -- offset = (char *)rmesa->rmm->u_list[id].ptr - -- (char *)rmesa->radeon.radeonScreen->gartTextures.map; -- offset += rmesa->radeon.radeonScreen->gart_texture_offset; -+ init_buffer(bufmgr, &bo->base, size); -+ return &bo->base.base; - -- return offset; - } - -void *r300_mem_map(r300ContextPtr rmesa, int id, int access) -+ -+ -+static void bufmgr_classic_bo_reference(dri_bo *bo_base) ++dri_bo *radeon_bufmgr_classic_bo_alloc_static(dri_bufmgr *bufmgr_ctx, const char *name, ++ unsigned long offset, unsigned long size, ++ void *virtual, uint32_t initial_domain) { -#ifdef MM_DEBUG - fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, @@ -3431,38 +3447,58 @@ index f8f9d4f..b045393 100644 -#endif - void *ptr; - int tries = 0; ++ radeon_bufmgr_classic* bufmgr = get_bufmgr_classic(bufmgr_ctx); ++ radeon_bo_vram* bo = (radeon_bo_vram*)calloc(1, sizeof(radeon_bo_vram)); ++ ++ bo->base.functions = &static_bo_functions; ++ bo->base.base.virtual = virtual; ++ bo->base.base.offset = offset + bufmgr->rmesa->radeon.radeonScreen->fbLocation; ++ bo->base.validated = 1; /* Static buffer offsets are always valid */ ++ ++ init_buffer(bufmgr, &bo->base, size); ++ return &bo->base.base; ++ ++} + +- assert(id <= rmesa->rmm->u_last); ++static void bufmgr_classic_bo_reference(dri_bo *bo_base) ++{ + radeon_bo_classic *bo = get_bo_classic(bo_base); + bo->refcount++; + assert(bo->refcount > 0); +} -- assert(id <= rmesa->rmm->u_last); +- if (access == R300_MEM_R) { +static void bufmgr_classic_bo_unreference(dri_bo *bo_base) +{ + radeon_bo_classic *bo = get_bo_classic(bo_base); -- if (access == R300_MEM_R) { +- if (rmesa->rmm->u_list[id].mapped == 1) +- WARN_ONCE("buffer %d already mapped\n", id); + if (!bo_base) + return; -- if (rmesa->rmm->u_list[id].mapped == 1) -- WARN_ONCE("buffer %d already mapped\n", id); +- rmesa->rmm->u_list[id].mapped = 1; +- ptr = r300_mem_ptr(rmesa, id); + assert(bo->refcount > 0); + bo->refcount--; + if (!bo->refcount) { + // Ugly HACK - figure out whether this is really necessary + get_bufmgr_classic(bo_base->bufmgr)->rmesa->dma.nr_released_bufs++; -- rmesa->rmm->u_list[id].mapped = 1; -- ptr = r300_mem_ptr(rmesa, id); +- return ptr; + assert(!bo->mapcount); + if (!bo->pending) + bo_free(bo); -+ } + } +} -- return ptr; -+static int bufmgr_classic_bo_map(dri_bo *bo_base, GLboolean write_enable) +- if (rmesa->rmm->u_list[id].h_pending) +- r300FlushCmdBuf(rmesa, __FUNCTION__); +- +- if (rmesa->rmm->u_list[id].h_pending) { +- return NULL; ++static int bufmgr_classic_bo_map(dri_bo *bo_base, int write_enable) +{ + radeon_bufmgr_classic *bufmgr = get_bufmgr_classic(bo_base->bufmgr); + radeon_bo_classic *bo = get_bo_classic(bo_base); @@ -3483,28 +3519,27 @@ index f8f9d4f..b045393 100644 + } } -- if (rmesa->rmm->u_list[id].h_pending) -- r300FlushCmdBuf(rmesa, __FUNCTION__); -+ if (write_enable && bo->functions->dirty) -+ bo->functions->dirty(bo); - -- if (rmesa->rmm->u_list[id].h_pending) { -- return NULL; -- } +- while (rmesa->rmm->u_list[id].age > +- radeonGetAge((radeonContextPtr) rmesa) && tries++ < 1000) +- usleep(10); ++ if (!bo->mapcount && bo->functions->map) ++ bo->functions->map(bo, write_enable); ++ + bo->mapcount++; + assert(bo->mapcount > 0); + return 0; +} - -- while (rmesa->rmm->u_list[id].age > -- radeonGetAge((radeonContextPtr) rmesa) && tries++ < 1000) -- usleep(10); ++ +static int bufmgr_classic_bo_unmap(dri_bo *buf) +{ + radeon_bo_classic *bo = get_bo_classic(buf); + assert(bo->refcount > 0); + assert(bo->mapcount > 0); + bo->mapcount--; ++ ++ if (!bo->mapcount && bo->functions->unmap) ++ bo->functions->unmap(bo); ++ + return 0; +} @@ -3571,8 +3606,8 @@ index f8f9d4f..b045393 100644 } -void r300_mem_unmap(r300ContextPtr rmesa, int id) -+static int bufmgr_classic_emit_reloc(dri_bo *batch_buf, uint64_t flags, GLuint delta, -+ GLuint offset, dri_bo *target) ++int radeon_bufmgr_classic_emit_reloc(dri_bo *batch_buf, uint64_t flags, GLuint delta, ++ GLuint offset, dri_bo *target) { -#ifdef MM_DEBUG - fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, @@ -3580,19 +3615,16 @@ index f8f9d4f..b045393 100644 -#endif + radeon_bo_classic *bo = get_bo_classic(batch_buf); + radeon_reloc *reloc; - -- assert(id <= rmesa->rmm->u_last); ++ + if (bo->relocs_used >= bo->relocs_size) { + bo->relocs_size *= 2; + if (bo->relocs_size < 32) + bo->relocs_size = 32; - -- if (rmesa->rmm->u_list[id].mapped == 0) -- WARN_ONCE("buffer %d not mapped\n", id); ++ + bo->relocs = (radeon_reloc*)realloc(bo->relocs, bo->relocs_size*sizeof(radeon_reloc)); + } -- rmesa->rmm->u_list[id].mapped = 0; +- assert(id <= rmesa->rmm->u_last); + reloc = &bo->relocs[bo->relocs_used++]; + reloc->flags = flags; + reloc->offset = offset; @@ -3600,23 +3632,20 @@ index f8f9d4f..b045393 100644 + reloc->target = get_bo_classic(target); + dri_bo_reference(target); + return 0; - } ++} --void r300_mem_free(r300ContextPtr rmesa, int id) +- if (rmesa->rmm->u_list[id].mapped == 0) +- WARN_ONCE("buffer %d not mapped\n", id); +/* process_relocs is called just before the given command buffer + * is executed. It ensures that all referenced buffers are in + * the right GPU domain. + */ -+static void *bufmgr_classic_process_relocs(dri_bo *batch_buf, GLuint *count) - { --#ifdef MM_DEBUG -- fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, -- radeonGetAge((radeonContextPtr) rmesa)); --#endif ++static void *bufmgr_classic_process_relocs(dri_bo *batch_buf) ++{ + radeon_bo_classic *batch_bo = get_bo_classic(batch_buf); + int i; -- assert(id <= rmesa->rmm->u_last); +- rmesa->rmm->u_list[id].mapped = 0; + // Warning: At this point, we append something to the batch buffer + // during flush. + emit_age_for_buffer(batch_bo); @@ -3641,27 +3670,33 @@ index f8f9d4f..b045393 100644 + } + dri_bo_unmap(batch_buf); + return 0; -+} + } -- if (id == 0) -- return; +-void r300_mem_free(r300ContextPtr rmesa, int id) +/* post_submit is called just after the given command buffer + * is executed. It ensures that buffers are properly marked as + * pending. + */ -+static void bufmgr_classic_post_submit(dri_bo *batch_buf, dri_fence **fence) -+{ ++static void bufmgr_classic_post_submit(dri_bo *batch_buf) + { +-#ifdef MM_DEBUG +- fprintf(stderr, "%s: %d at age %x\n", __FUNCTION__, id, +- radeonGetAge((radeonContextPtr) rmesa)); +-#endif + radeon_bo_classic *batch_bo = get_bo_classic(batch_buf); + int i; +- assert(id <= rmesa->rmm->u_last); ++ assert(!batch_bo->pending_count); + +- if (id == 0) +- return; ++ for(i = 0; i < batch_bo->relocs_used; ++i) { ++ radeon_reloc *reloc = &batch_bo->relocs[i]; + - if (rmesa->rmm->u_list[id].ptr == NULL) { - WARN_ONCE("Not allocated!\n"); - return; -+ assert(!batch_bo->pending_count); -+ -+ for(i = 0; i < batch_bo->relocs_used; ++i) { -+ radeon_reloc *reloc = &batch_bo->relocs[i]; -+ + if (reloc->target->used) { + reloc->target->used = 0; + assert(!reloc->target->pending_count); @@ -3686,9 +3721,9 @@ index f8f9d4f..b045393 100644 + track_pending_buffers(bufmgr); + + if (bufmgr->buffers) { -+ fprintf(stderr, "Warning: Buffer objects have leaked\n"); ++ //fprintf(stderr, "Warning: Buffer objects have leaked\n"); + while(bufmgr->buffers) { -+ fprintf(stderr, " Leak of size %ld\n", bufmgr->buffers->base.size); ++ //fprintf(stderr, " Leak of size %ld\n", bufmgr->buffers->base.size); + bufmgr->buffers->refcount = 0; + bufmgr->buffers->mapcount = 0; + bufmgr->buffers->pending = 0; @@ -3709,13 +3744,11 @@ index f8f9d4f..b045393 100644 + radeon_bufmgr_classic* bufmgr = (radeon_bufmgr_classic*)calloc(1, sizeof(radeon_bufmgr_classic)); + + bufmgr->rmesa = rmesa; -+ bufmgr->base.base.bo_alloc = &bufmgr_classic_bo_alloc; -+ bufmgr->base.base.bo_alloc_static = bufmgr_classic_bo_alloc_static; ++ // bufmgr->base.base.bo_alloc = &bufmgr_classic_bo_alloc; + bufmgr->base.base.bo_reference = &bufmgr_classic_bo_reference; + bufmgr->base.base.bo_unreference = &bufmgr_classic_bo_unreference; + bufmgr->base.base.bo_map = &bufmgr_classic_bo_map; + bufmgr->base.base.bo_unmap = &bufmgr_classic_bo_unmap; -+ bufmgr->base.base.emit_reloc = &bufmgr_classic_emit_reloc; + bufmgr->base.base.process_relocs = &bufmgr_classic_process_relocs; + bufmgr->base.base.post_submit = &bufmgr_classic_post_submit; + bufmgr->base.base.destroy = &bufmgr_classic_destroy; @@ -3798,7 +3831,7 @@ index 625a7f6..4e9be65 100644 #endif diff --git a/src/mesa/drivers/dri/r300/r300_mipmap_tree.c b/src/mesa/drivers/dri/r300/r300_mipmap_tree.c new file mode 100644 -index 0000000..c3b918c +index 0000000..75b7d32 --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_mipmap_tree.c @@ -0,0 +1,248 @@ @@ -3957,7 +3990,7 @@ index 0000000..c3b918c + + calculate_miptree_layout(mt); + -+ mt->bo = dri_bo_alloc(&rmesa->radeon.bufmgr->base, "texture", mt->totalsize, 1024, 0); ++ mt->bo = radeon_bufmgr_classic_bo_alloc(&rmesa->radeon.bufmgr->base, "texture", mt->totalsize, 1024, 0); + + return mt; +} @@ -4317,7 +4350,7 @@ index 0a199e6..209fae9 100644 return GL_FALSE; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c -index cce07d3..b314764 100644 +index 15cd053..589327d 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -55,6 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -4328,7 +4361,7 @@ index cce07d3..b314764 100644 #include "r300_context.h" #include "r300_ioctl.h" #include "r300_state.h" -@@ -1148,39 +1149,25 @@ void r300UpdateDrawBuffer(GLcontext * ctx) +@@ -1146,39 +1147,25 @@ void r300UpdateDrawBuffer(GLcontext * ctx) r300ContextPtr rmesa = R300_CONTEXT(ctx); r300ContextPtr r300 = rmesa; struct gl_framebuffer *fb = ctx->DrawBuffer; @@ -4374,7 +4407,7 @@ index cce07d3..b314764 100644 #if 0 R200_STATECHANGE(rmesa, ctx); -@@ -1499,14 +1486,9 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1497,14 +1484,9 @@ static void r300SetupTextures(GLcontext * ctx) /* We cannot let disabled tmu offsets pass DRM */ for (i = 0; i < mtu; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { @@ -4390,7 +4423,7 @@ index cce07d3..b314764 100644 if (!t) continue; -@@ -1532,21 +1514,20 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1530,21 +1512,20 @@ static void r300SetupTextures(GLcontext * ctx) */ r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->filter_1 | @@ -4416,7 +4449,7 @@ index cce07d3..b314764 100644 WARN_ONCE("micro tiling enabled!\n"); } -@@ -2373,20 +2354,6 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2371,20 +2352,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300BlendColor(ctx, ctx->Color.BlendColor); @@ -4437,7 +4470,7 @@ index cce07d3..b314764 100644 r300->hw.rb3d_dither_ctl.cmd[1] = 0; r300->hw.rb3d_dither_ctl.cmd[2] = 0; r300->hw.rb3d_dither_ctl.cmd[3] = 0; -@@ -2402,10 +2369,6 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2400,10 +2367,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; @@ -5944,7 +5977,7 @@ index 69847a4..b3b501b 100644 if (RADEON_DEBUG & DEBUG_SYNC) { diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c -index bdd20b1..1b24738 100644 +index d19832f..5cb9010 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -48,6 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -6147,7 +6180,7 @@ index bdd20b1..1b24738 100644 /* Set the hardware texture format */ -@@ -335,107 +276,59 @@ static void r300SetTexImages(r300ContextPtr rmesa, +@@ -335,112 +276,66 @@ static void r300SetTexImages(r300ContextPtr rmesa, } texelBytes = baseImage->TexFormat->TexelBytes; @@ -6230,52 +6263,58 @@ index bdd20b1..1b24738 100644 + texelBytes, t->tile_bits, compressed); + memset(t->dirty_images, 0xff, sizeof(t->dirty_images)); } -- } else { + } else { + if (tObj->Target == GL_TEXTURE_3D) + t->format |= R300_TX_FORMAT_3D; +- - for (i = 0; i < numLevels; i++) - compute_tex_image_offset(tObj, 0, i, &curOffset); } -- /* Align the total size of texture memory block. -- */ + /* Align the total size of texture memory block. + */ - t->base.totalSize = - (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; -- -- t->size = ++ // dritex->totalSize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; + + t->size = - (((tObj->Image[0][t->base.firstLevel]->Width - -- 1) << R300_TX_WIDTHMASK_SHIFT) ++ (((tObj->Image[0][firstLevel]->Width - + 1) << R300_TX_WIDTHMASK_SHIFT) - | ((tObj->Image[0][t->base.firstLevel]->Height - 1) << -- R300_TX_HEIGHTMASK_SHIFT)) ++ | ((tObj->Image[0][firstLevel]->Height - 1) << + R300_TX_HEIGHTMASK_SHIFT) +- | ((tObj->Image[0][t->base.firstLevel]->DepthLog2) << ++ | ((tObj->Image[0][firstLevel]->DepthLog2) << + R300_TX_DEPTHMASK_SHIFT)) - | ((numLevels - 1) << R300_TX_MAX_MIP_LEVEL_SHIFT); -- -+ t->size = (((tObj->Image[0][firstLevel]->Width - 1) << R300_TX_WIDTHMASK_SHIFT) -+ | ((tObj->Image[0][firstLevel]->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)) -+ | ((lastLevel - firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT); - t->pitch = 0; ++ | ((lastLevel - firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT); + +- t->pitch = 0; ++ // t->pitch = 0; - /* Only need to round to nearest 32 for textures, but the blitter - * requires 64-byte aligned pitches, and we may/may not need the - * blitter. NPOT only! - */ - if (baseImage->IsCompressed) { +- if (baseImage->IsCompressed) { - t->pitch |= - (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); -+ t->pitch |= (tObj->Image[0][firstLevel]->Width + 63) & ~(63); - } else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) { +- } else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) { ++ if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) { unsigned int align = (64 / texelBytes) - 1; - t->pitch |= ((tObj->Image[0][t->base.firstLevel]->Width * -+ t->pitch |= ((tObj->Image[0][firstLevel]->Width * - texelBytes) + 63) & ~(63); +- texelBytes) + 63) & ~(63); t->size |= R300_TX_SIZE_TXPITCH_EN; if (!t->image_override) - t->pitch_reg = - (((tObj->Image[0][t->base.firstLevel]->Width) + - align) & ~align) - 1; -+ t->pitch_reg = (((tObj->Image[0][firstLevel]->Width) + align) & ~align) - 1; - } else { +- } else { - t->pitch |= - ((tObj->Image[0][t->base.firstLevel]->Width * - texelBytes) + 63) & ~(63); -+ t->pitch |= ((tObj->Image[0][firstLevel]->Width * texelBytes) + 63) & ~(63); ++ t->pitch_reg = (((tObj->Image[0][firstLevel]->Width) + align) & ~align) - 1; } if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { @@ -6287,7 +6326,7 @@ index bdd20b1..1b24738 100644 t->pitch_reg |= R500_TXHEIGHT_BIT11; } } -@@ -449,17 +342,15 @@ static GLboolean r300EnableTexture2D(GLcontext * ctx, int unit) +@@ -454,17 +349,15 @@ static GLboolean r300EnableTexture2D(GLcontext * ctx, int unit) r300ContextPtr rmesa = R300_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; @@ -6308,7 +6347,7 @@ index bdd20b1..1b24738 100644 } return GL_TRUE; -@@ -470,7 +361,7 @@ static GLboolean r300EnableTexture3D(GLcontext * ctx, int unit) +@@ -475,7 +368,7 @@ static GLboolean r300EnableTexture3D(GLcontext * ctx, int unit) r300ContextPtr rmesa = R300_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; @@ -6317,7 +6356,7 @@ index bdd20b1..1b24738 100644 ASSERT(tObj->Target == GL_TEXTURE_3D); -@@ -479,12 +370,10 @@ static GLboolean r300EnableTexture3D(GLcontext * ctx, int unit) +@@ -484,12 +377,10 @@ static GLboolean r300EnableTexture3D(GLcontext * ctx, int unit) return GL_FALSE; } @@ -6332,7 +6371,7 @@ index bdd20b1..1b24738 100644 } return GL_TRUE; -@@ -495,14 +384,15 @@ static GLboolean r300EnableTextureCube(GLcontext * ctx, int unit) +@@ -500,14 +391,15 @@ static GLboolean r300EnableTextureCube(GLcontext * ctx, int unit) r300ContextPtr rmesa = R300_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; @@ -6352,7 +6391,7 @@ index bdd20b1..1b24738 100644 /* flush */ R300_FIREVERTICES(rmesa); /* layout memory space, once for all faces */ -@@ -511,18 +401,11 @@ static GLboolean r300EnableTextureCube(GLcontext * ctx, int unit) +@@ -516,18 +408,11 @@ static GLboolean r300EnableTextureCube(GLcontext * ctx, int unit) /* upload (per face) */ for (face = 0; face < 6; face++) { @@ -6373,7 +6412,7 @@ index bdd20b1..1b24738 100644 return GL_TRUE; } -@@ -531,18 +414,15 @@ static GLboolean r300EnableTextureRect(GLcontext * ctx, int unit) +@@ -536,18 +421,15 @@ static GLboolean r300EnableTextureRect(GLcontext * ctx, int unit) r300ContextPtr rmesa = R300_CONTEXT(ctx); struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *tObj = texUnit->_Current; @@ -6395,7 +6434,7 @@ index bdd20b1..1b24738 100644 } return GL_TRUE; -@@ -550,34 +430,19 @@ static GLboolean r300EnableTextureRect(GLcontext * ctx, int unit) +@@ -555,34 +437,19 @@ static GLboolean r300EnableTextureRect(GLcontext * ctx, int unit) static GLboolean r300UpdateTexture(GLcontext * ctx, int unit) { @@ -6435,7 +6474,7 @@ index bdd20b1..1b24738 100644 } void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, -@@ -586,20 +451,18 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, +@@ -591,20 +458,18 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, r300ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); @@ -6459,7 +6498,7 @@ index bdd20b1..1b24738 100644 pitch_val = pitch; diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c -index 3fc724a..a84c8fc 100644 +index 3fc724a..a9d36a2 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -6470,7 +6509,7 @@ index 3fc724a..a84c8fc 100644 #include "drivers/common/driverfuncs.h" #include "swrast/swrast.h" -@@ -258,6 +259,52 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, +@@ -258,6 +259,59 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, } } @@ -6483,47 +6522,54 @@ index 3fc724a..a84c8fc 100644 + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + uint32_t offset; ++ + if (!radeon->bufmgr) + return; + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + -+ offset = radeon->radeonScreen->kernel_mm ? radeon->radeonScreen->front.offset : radeon->radeonScreen->frontOffset; -+ if (!rb->bo) -+ rb->bo = dri_bo_alloc_static(&radeon->bufmgr->base, "front buffer", -+ radeon->radeonScreen->frontOffset, size, map, -+ DRM_BO_FLAG_MEM_VRAM); -+ fprintf(stderr,"front is %p\n", rb->bo); ++ if (radeon->radeonScreen->kernel_mm) ++ map = radeon->radeonScreen->front.map; ++ ++ offset = radeon->radeonScreen->kernel_mm ? radeon->radeonScreen->front.offset : radeon->radeonScreen->frontOffset; ++ if (!rb->bo) ++ rb->bo = radeon_bufmgr_classic_bo_alloc_static(&radeon->bufmgr->base, "front buffer", ++ offset, size, map, ++ 0); + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { -+ offset = radeon->radeonScreen->kernel_mm ? radeon->radeonScreen->back.offset : radeon->radeonScreen->backOffset; -+ if (!rb->bo) -+ rb->bo = dri_bo_alloc_static(&radeon->bufmgr->base, "back buffer", -+ radeon->radeonScreen->backOffset, size, map, -+ DRM_BO_FLAG_MEM_VRAM); -+ fprintf(stderr,"back is %p\n", rb->bo); ++ ++ if (radeon->radeonScreen->kernel_mm) ++ map = radeon->radeonScreen->back.map; ++ ++ offset = radeon->radeonScreen->kernel_mm ? radeon->radeonScreen->back.offset : radeon->radeonScreen->backOffset; ++ if (!rb->bo) ++ rb->bo = radeon_bufmgr_classic_bo_alloc_static(&radeon->bufmgr->base, "back buffer", ++ offset, size, map, 0); + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + offset = radeon->radeonScreen->kernel_mm ? radeon->radeonScreen->depth.offset : radeon->radeonScreen->depthOffset; ++ ++ if (radeon->radeonScreen->kernel_mm) ++ map = radeon->radeonScreen->depth.map; ++ + if (!rb->bo) -+ rb->bo = dri_bo_alloc_static(&radeon->bufmgr->base, "depth buffer", -+ radeon->radeonScreen->depthOffset, size, map, -+ DRM_BO_FLAG_MEM_VRAM); -+ fprintf(stderr,"depth is %p\n", rb->bo); ++ rb->bo = radeon_bufmgr_classic_bo_alloc_static(&radeon->bufmgr->base, "depth buffer", ++ offset, size, map, 0); + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch; + } +} + -+ ++ /* Force the context `c' to be the current context and associate with it * buffer `b'. */ -@@ -265,51 +312,57 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, +@@ -265,51 +319,57 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, __DRIdrawablePrivate * driReadPriv) { @@ -6556,31 +6602,22 @@ index 3fc724a..a84c8fc 100644 + radeon = (radeonContextPtr) driContextPriv->driverPrivate; + dfb = driDrawPriv->driverPrivate; + rfb = driReadPriv->driverPrivate; - -- radeon->dri.readable = driReadPriv; ++ + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); ++ ++ driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); ++ if (driReadPriv != driDrawPriv) ++ driUpdateFramebufferSize(radeon->glCtx, driReadPriv); ++ ++ radeon_make_renderbuffer_current(radeon, dfb); + +- radeon->dri.readable = driReadPriv; ++ _mesa_make_current(radeon->glCtx, dfb, rfb); - if (radeon->dri.drawable != driDrawPriv || - radeon->lastStamp != driDrawPriv->lastStamp) { - radeon->dri.drawable = driDrawPriv; -+ driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); -+ if (driReadPriv != driDrawPriv) -+ driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - -- radeonSetCliprects(radeon); -- r300UpdateViewportOffset(radeon->glCtx); -- } -+ radeon_make_renderbuffer_current(radeon, dfb); - -- _mesa_make_current(radeon->glCtx, -- (GLframebuffer *) driDrawPriv-> -- driverPrivate, -- (GLframebuffer *) driReadPriv-> -- driverPrivate); -+ _mesa_make_current(radeon->glCtx, dfb, rfb); - -- _mesa_update_state(radeon->glCtx); + if (radeon->dri.drawable != driDrawPriv) { + if (driDrawPriv->swap_interval == (unsigned)-1) { + driDrawPriv->vblFlags = @@ -6588,27 +6625,35 @@ index 3fc724a..a84c8fc 100644 + ? driGetDefaultVBlankFlags(&radeon-> + optionCache) + : VBLANK_FLAG_NO_IRQ; -+ + +- radeonSetCliprects(radeon); +- r300UpdateViewportOffset(radeon->glCtx); + driDrawableInitVBlank(driDrawPriv); -+ } + } + } +- _mesa_make_current(radeon->glCtx, +- (GLframebuffer *) driDrawPriv-> +- driverPrivate, +- (GLframebuffer *) driReadPriv-> +- driverPrivate); ++ radeon->dri.readable = driReadPriv; + +- _mesa_update_state(radeon->glCtx); ++ if (radeon->dri.drawable != driDrawPriv || ++ radeon->lastStamp != driDrawPriv->lastStamp) { ++ radeon->dri.drawable = driDrawPriv; + - radeonUpdatePageFlipping(radeon); - } else { - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current(0, 0, 0); -+ radeon->dri.readable = driReadPriv; -+ -+ if (radeon->dri.drawable != driDrawPriv || -+ radeon->lastStamp != driDrawPriv->lastStamp) { -+ radeon->dri.drawable = driDrawPriv; -+ + radeonSetCliprects(radeon); + r300UpdateViewportOffset(radeon->glCtx); } -+ _mesa_update_state(radeon->glCtx); ++ _mesa_update_state(radeon->glCtx); + + radeonUpdatePageFlipping(radeon); + @@ -6726,7 +6771,7 @@ index 0c1a195..486ce8e 100644 void radeonWaitForIdleLocked(radeonContextPtr radeon) diff --git a/src/mesa/drivers/dri/r300/radeon_lock.c b/src/mesa/drivers/dri/r300/radeon_lock.c -index d54a821..3529555 100644 +index d54a821..4df6a9c 100644 --- a/src/mesa/drivers/dri/r300/radeon_lock.c +++ b/src/mesa/drivers/dri/r300/radeon_lock.c @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -6737,7 +6782,7 @@ index d54a821..3529555 100644 #include "framebuffer.h" -@@ -59,6 +60,8 @@ int prevLockLine = 0; +@@ -59,11 +60,11 @@ int prevLockLine = 0; void radeonUpdatePageFlipping(radeonContextPtr rmesa) { int use_back; @@ -6746,7 +6791,12 @@ index d54a821..3529555 100644 rmesa->doPageFlip = rmesa->sarea->pfState; if (rmesa->glCtx->WinSysDrawBuffer) { -@@ -72,16 +75,12 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa) +- driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, +- rmesa->sarea->pfCurrentPage); + r300UpdateDrawBuffer(rmesa->glCtx); + } + +@@ -72,16 +73,12 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa) BUFFER_BACK_LEFT) : 1; use_back ^= (rmesa->sarea->pfCurrentPage == 1); @@ -6769,7 +6819,7 @@ index d54a821..3529555 100644 } /* Update the hardware state. This is called if another context has -@@ -125,12 +124,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) +@@ -125,12 +122,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) } if (sarea->ctx_owner != rmesa->dri.hwContext) { @@ -6784,7 +6834,7 @@ index d54a821..3529555 100644 rmesa->lost_context = GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c -index f1bc56e..7ea0842 100644 +index 3616d8b..58b00ff 100644 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ b/src/mesa/drivers/dri/r300/radeon_span.c @@ -48,7 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -6872,9 +6922,9 @@ index f1bc56e..7ea0842 100644 return 2 * (x + y * pitch); } else { GLuint ba, address = 0; /* a[0] = 0 */ -@@ -173,10 +174,10 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) - /* 16-bit depth buffer functions - */ +@@ -175,10 +176,10 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) + #define VALUE_TYPE GLushort + #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d; + *(GLushort *)(buf + radeon_mba_z16( rrb, _x + xo, _y + yo )) = d; @@ -6885,7 +6935,7 @@ index f1bc56e..7ea0842 100644 #define TAG(x) radeon##x##_z16 #include "depthtmp.h" -@@ -189,7 +190,7 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) +@@ -193,7 +194,7 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ @@ -6894,7 +6944,7 @@ index f1bc56e..7ea0842 100644 GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ -@@ -198,7 +199,7 @@ do { \ +@@ -202,7 +203,7 @@ do { \ #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ @@ -6903,7 +6953,7 @@ index f1bc56e..7ea0842 100644 GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ -@@ -209,12 +210,12 @@ do { \ +@@ -213,12 +214,12 @@ do { \ #ifdef COMPILE_R300 #define READ_DEPTH( d, _x, _y ) \ do { \ @@ -6918,7 +6968,7 @@ index f1bc56e..7ea0842 100644 _y + yo )) & 0x00ffffff; #endif -@@ -230,7 +231,7 @@ do { \ +@@ -234,7 +235,7 @@ do { \ #ifdef COMPILE_R300 #define WRITE_STENCIL( _x, _y, d ) \ do { \ @@ -6927,7 +6977,7 @@ index f1bc56e..7ea0842 100644 GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ -@@ -239,7 +240,7 @@ do { \ +@@ -243,7 +244,7 @@ do { \ #else #define WRITE_STENCIL( _x, _y, d ) \ do { \ @@ -6936,7 +6986,7 @@ index f1bc56e..7ea0842 100644 GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ -@@ -250,14 +251,14 @@ do { \ +@@ -254,14 +255,14 @@ do { \ #ifdef COMPILE_R300 #define READ_STENCIL( d, _x, _y ) \ do { \ @@ -6953,21 +7003,106 @@ index f1bc56e..7ea0842 100644 GLuint tmp = *(GLuint *)(buf + offset); \ d = (tmp & 0xff000000) >> 24; \ } while (0) -@@ -300,10 +301,10 @@ static void radeonSpanRenderStart(GLcontext * ctx) - */ - { - int p; +@@ -270,6 +271,22 @@ do { \ + #define TAG(x) radeon##x##_z24_s8 + #include "stenciltmp.h" + ++static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) ++{ ++ struct radeon_renderbuffer *rrb = (void*)rb; ++ ++ if (rrb->bo) ++ dri_bo_map(rrb->bo, write); ++} ++ ++static void unmap_buffer(struct gl_renderbuffer *rb) ++{ ++ struct radeon_renderbuffer *rrb = (void*)rb; ++ ++ if (rrb->bo) ++ dri_bo_unmap(rrb->bo); ++} ++ + /* Move locking out to get reasonable span performance (10x better + * than doing this in HW_LOCK above). WaitForIdle() is the main + * culprit. +@@ -278,45 +295,51 @@ do { \ + static void radeonSpanRenderStart(GLcontext * ctx) + { + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); ++ int i; + #ifdef COMPILE_R300 + r300ContextPtr r300 = (r300ContextPtr) rmesa; + R300_FIREVERTICES(r300); + #else + RADEON_FIREVERTICES(rmesa); + #endif ++ ++ /* color draw buffers */ ++ for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) ++ map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); ++ ++ map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); ++ ++ if (ctx->DrawBuffer->_DepthBuffer) ++ map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); ++ if (ctx->DrawBuffer->_StencilBuffer) ++ map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); ++ ++ /* The locking and wait for idle should really only be needed in classic mode. ++ * In a future memory manager based implementation, this should become ++ * unnecessary due to the fact that mapping our buffers, textures, etc. ++ * should implicitly wait for any previous rendering commands that must ++ * be waited on. */ + LOCK_HARDWARE(rmesa); + radeonWaitForIdleLocked(rmesa); +- +- /* Read the first pixel in the frame buffer. This should +- * be a noop, right? In fact without this conform fails as reading +- * from the framebuffer sometimes produces old results -- the +- * on-card read cache gets mixed up and doesn't notice that the +- * framebuffer has been updated. +- * +- * Note that we should probably be reading some otherwise unused +- * region of VRAM, otherwise we might get incorrect results when +- * reading pixels from the top left of the screen. +- * +- * I found this problem on an R420 with glean's texCube test. +- * Note that the R200 span code also *writes* the first pixel in the +- * framebuffer, but I've found this to be unnecessary. +- * -- Nicolai Hähnle, June 2008 +- */ +- { +- int p; - driRenderbuffer *drb = - (driRenderbuffer *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0]; -+ struct radeon_renderbuffer *rrb = -+ (void *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0]; - volatile int *buf = +- volatile int *buf = - (volatile int *)(rmesa->dri.screen->pFB + drb->offset); -+ (volatile int *)(rmesa->dri.screen->pFB + rrb->bo->offset); - p = *buf; - } +- p = *buf; +- } } -@@ -326,20 +327,17 @@ void radeonInitSpanFuncs(GLcontext * ctx) + + static void radeonSpanRenderFinish(GLcontext * ctx) + { + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); ++ int i; + _swrast_flush(ctx); + UNLOCK_HARDWARE(rmesa); ++ ++ /* color draw buffers */ ++ for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) ++ unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); ++ ++ unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); ++ ++ if (ctx->DrawBuffer->_DepthBuffer) ++ unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); ++ if (ctx->DrawBuffer->_StencilBuffer) ++ unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); + } + + void radeonInitSpanFuncs(GLcontext * ctx) +@@ -330,20 +353,17 @@ void radeonInitSpanFuncs(GLcontext * ctx) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ @@ -6987,18 +7122,17 @@ index f1bc56e..7ea0842 100644 - radeonInitDepthPointers_z24_s8(&drb->Base); - } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&drb->Base); -- } -+ if (rrb->base.InternalFormat == GL_RGB5) { -+ radeonInitPointers_RGB565(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_RGBA8) { -+ radeonInitPointers_ARGB8888(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { -+ radeonInitDepthPointers_z16(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { -+ radeonInitDepthPointers_z24_s8(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { -+ radeonInitStencilPointers_z24_s8(&rrb->base); -+ } ++ if (rrb->base.InternalFormat == GL_RGB5) { ++ radeonInitPointers_RGB565(&rrb->base); ++ } else if (rrb->base.InternalFormat == GL_RGBA8) { ++ radeonInitPointers_ARGB8888(&rrb->base); ++ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { ++ radeonInitDepthPointers_z16(&rrb->base); ++ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { ++ radeonInitDepthPointers_z24_s8(&rrb->base); ++ } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { ++ radeonInitStencilPointers_z24_s8(&rrb->base); + } } diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c index d81318c..a7720da 100644 @@ -7021,10 +7155,10 @@ index d81318c..a7720da 100644 diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer.h b/src/mesa/drivers/dri/radeon/radeon_buffer.h new file mode 100644 -index 0000000..730c40b +index 0000000..a5e4529 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_buffer.h -@@ -0,0 +1,50 @@ +@@ -0,0 +1,62 @@ +/* + * Copyright 2008 Red Hat, Inc. + * @@ -7072,11 +7206,23 @@ index 0000000..730c40b + +struct radeon_bufmgr { + dri_bufmgr base; ++ void (*emit_reloc)(dri_bo *buf, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); +}; + ++void radeon_bufmgr_emit_reloc(dri_bo *buf, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); ++ ++dri_bo *radeon_bufmgr_classic_bo_alloc_static(dri_bufmgr *bufmgr_ctx, const char *name, ++ unsigned long offset, unsigned long size, ++ void *virtual, uint32_t initial_domain); ++dri_bo *radeon_bufmgr_classic_bo_alloc(dri_bufmgr *bufmgr_ctx, const char *name, ++ unsigned long size, unsigned int alignment, ++ uint32_t location_mask); ++ ++int radeon_bufmgr_classic_emit_reloc(dri_bo *batch_buf, uint64_t flags, GLuint delta, ++ GLuint offset, dri_bo *target); +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c -index 84b5c46..10a49d2 100644 +index 84b5c46..cc384e1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -46,6 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -7097,10 +7243,18 @@ index 84b5c46..10a49d2 100644 /* Radeon configuration */ #include "xmlpool.h" -@@ -350,6 +354,79 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { - }; +@@ -344,11 +348,99 @@ static const __DRItexOffsetExtension r200texOffsetExtension = { #endif + #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) ++#if 0 + static const __DRItexOffsetExtension r300texOffsetExtension = { + { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, + r300SetTexOffset, + }; + #endif ++#endif ++ + +static void +radeon_gem_update_handle(radeonScreenPtr screen, __DRIscreenPrivate *sPriv, @@ -7122,8 +7276,10 @@ index 84b5c46..10a49d2 100644 + /* do open */ + args.name = gem_obj->gem_name; + ret = ioctl(sPriv->fd, DRM_IOCTL_GEM_OPEN, &args); -+ if (ret) ++ if (ret) { ++ fprintf(stderr," failed to open handle %d\n", gem_obj->gem_name); + return; ++ } + + gem_obj->gem_handle = args.handle; + gem_obj->size = args.size; @@ -7151,8 +7307,6 @@ index 84b5c46..10a49d2 100644 + + gem_obj->offset = pin_args.offset; + -+ fprintf(stderr,"handle %d, size %llx, ptr %p, offset %llx\n", gem_obj->gem_handle, -+ gem_obj->size, gem_obj->map, gem_obj->offset); +} + +static int @@ -7163,21 +7317,33 @@ index 84b5c46..10a49d2 100644 + + screen->front.gem_name = dri_priv->frontOffset; + radeon_gem_update_handle(screen, sPriv, &screen->front); ++ screen->frontOffset = screen->front.offset; ++ + screen->back.gem_name = dri_priv->backOffset; + radeon_gem_update_handle(screen, sPriv, &screen->back); ++ ++ screen->backOffset = screen->back.offset; ++ + screen->depth.gem_name = dri_priv->depthOffset; + radeon_gem_update_handle(screen, sPriv, &screen->depth); ++ screen->depthOffset = screen->depth.offset; + + screen->vram_texture.gem_name = dri_priv->textureOffset; + radeon_gem_update_handle(screen, sPriv, &screen->vram_texture); -+ screen->vram_texture.gem_name = dri_priv->gartTexHandle; -+ radeon_gem_update_handle(screen, sPriv, &screen->gart_texture); -+} + ++ screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->vram_texture.offset + screen->fbLocation; ++ screen->texSize[RADEON_LOCAL_TEX_HEAP] = screen->vram_texture.size; ++ ++ screen->gart_texture.gem_name = dri_priv->gartTexHandle; ++ radeon_gem_update_handle(screen, sPriv, &screen->gart_texture); ++ screen->gartTextures.map = screen->gart_texture.map; ++ screen->gart_texture_offset = screen->gart_texture.offset + screen->gart_base; ++ ++} + /* Create the device specific screen private data struct. */ - static radeonScreenPtr -@@ -389,6 +466,21 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -389,6 +481,21 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); { int ret; @@ -7199,7 +7365,7 @@ index 84b5c46..10a49d2 100644 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, &screen->gart_buffer_offset); -@@ -422,32 +514,34 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -422,32 +529,34 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); } @@ -7257,7 +7423,7 @@ index 84b5c46..10a49d2 100644 screen->buffers = drmMapBufs( sPriv->fd ); if ( !screen->buffers ) { -@@ -458,22 +552,24 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -458,22 +567,24 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) return NULL; } @@ -7297,7 +7463,7 @@ index 84b5c46..10a49d2 100644 } screen->chip_flags = 0; -@@ -840,7 +936,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -840,7 +951,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, &temp); if (ret) { @@ -7306,32 +7472,27 @@ index 84b5c46..10a49d2 100644 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; else { FREE( screen ); -@@ -881,55 +977,58 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -881,55 +992,59 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) } } - if ( sPriv->drm_version.minor >= 10 ) { - drm_radeon_setparam_t sp; -+ if (!screen->kernel_mm) { -+ if ( sPriv->drm_version.minor >= 10 ) { -+ drm_radeon_setparam_t sp; - +- - sp.param = RADEON_SETPARAM_FB_LOCATION; - sp.value = screen->fbLocation; -+ sp.param = RADEON_SETPARAM_FB_LOCATION; -+ sp.value = screen->fbLocation; - +- - drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, - &sp, sizeof( sp ) ); - } - - screen->frontOffset = dri_priv->frontOffset; -- screen->frontPitch = dri_priv->frontPitch; + screen->frontPitch = dri_priv->frontPitch; - screen->backOffset = dri_priv->backOffset; -- screen->backPitch = dri_priv->backPitch; + screen->backPitch = dri_priv->backPitch; - screen->depthOffset = dri_priv->depthOffset; -- screen->depthPitch = dri_priv->depthPitch; -- + screen->depthPitch = dri_priv->depthPitch; + - /* Check if ddx has set up a surface reg to cover depth buffer */ - screen->depthHasSurface = (sPriv->ddx_version.major > 4) || - /* these chips don't use tiled z without hyperz. So always pretend @@ -7351,6 +7512,13 @@ index 84b5c46..10a49d2 100644 - screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = - dri_priv->log2TexGran; - } ++ if (!screen->kernel_mm) { ++ if ( sPriv->drm_version.minor >= 10 ) { ++ drm_radeon_setparam_t sp; ++ ++ sp.param = RADEON_SETPARAM_FB_LOCATION; ++ sp.value = screen->fbLocation; ++ + drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, + &sp, sizeof( sp ) ); + } @@ -7362,11 +7530,8 @@ index 84b5c46..10a49d2 100644 - screen->texSize[RADEON_GART_TEX_HEAP] = 0; - screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; + screen->frontOffset = dri_priv->frontOffset; -+ screen->frontPitch = dri_priv->frontPitch; + screen->backOffset = dri_priv->backOffset; -+ screen->backPitch = dri_priv->backPitch; + screen->depthOffset = dri_priv->depthOffset; -+ screen->depthPitch = dri_priv->depthPitch; + + /* Check if ddx has set up a surface reg to cover depth buffer */ + screen->depthHasSurface = (sPriv->ddx_version.major > 4) || @@ -7410,7 +7575,18 @@ index 84b5c46..10a49d2 100644 } i = 0; -@@ -975,12 +1074,14 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +@@ -954,8 +1069,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) + #endif + + #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) ++#if 0 + screen->extensions[i++] = &r300texOffsetExtension.base; + #endif ++#endif + + screen->extensions[i++] = NULL; + sPriv->extensions = screen->extensions; +@@ -975,12 +1092,14 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) if (!screen) return; @@ -7430,7 +7606,7 @@ index 84b5c46..10a49d2 100644 /* free all option information */ driDestroyOptionInfo (&screen->optionCache); -@@ -1004,6 +1105,158 @@ radeonInitDriver( __DRIscreenPrivate *sPriv ) +@@ -1004,6 +1123,160 @@ radeonInitDriver( __DRIscreenPrivate *sPriv ) return GL_TRUE; } @@ -7448,7 +7624,7 @@ index 84b5c46..10a49d2 100644 + + +static struct radeon_renderbuffer * -+radeon_create_renderbuffer(GLenum format) ++radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) +{ + struct radeon_renderbuffer *ret; + @@ -7480,7 +7656,7 @@ index 84b5c46..10a49d2 100644 + case GL_STENCIL_INDEX8_EXT: + ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; + ret->base._BaseFormat = GL_STENCIL_INDEX; -+ ret->base.StencilBits = 8; ++ ret->base.StencilBits = 8; + ret->base.DataType = GL_UNSIGNED_BYTE; + break; + case GL_DEPTH_COMPONENT16: @@ -7503,10 +7679,12 @@ index 84b5c46..10a49d2 100644 + ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; + break; + default: -+ /* whoops */ -+ break; ++ fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); ++ _mesa_delete_renderbuffer(&ret->base); ++ return NULL; + } + ++ ret->dPriv = driDrawPriv; + ret->base.InternalFormat = format; + + ret->base.AllocStorage = radeon_alloc_window_storage; @@ -7547,21 +7725,21 @@ index 84b5c46..10a49d2 100644 + /* front color renderbuffer */ + { + struct radeon_renderbuffer *front = -+ radeon_create_renderbuffer(rgbFormat); ++ radeon_create_renderbuffer(rgbFormat, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); + } + + /* back color renderbuffer */ + if (mesaVis->doubleBufferMode) { + struct radeon_renderbuffer *back = -+ radeon_create_renderbuffer(GL_RGBA); ++ radeon_create_renderbuffer(rgbFormat, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); + } + + /* depth renderbuffer */ + if (depthFormat != GL_NONE) { + struct radeon_renderbuffer *depth = -+ radeon_create_renderbuffer(depthFormat); ++ radeon_create_renderbuffer(depthFormat, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); + depth->depthHasSurface = screen->depthHasSurface; + } @@ -7569,7 +7747,7 @@ index 84b5c46..10a49d2 100644 + /* stencil renderbuffer */ + if (mesaVis->stencilBits > 0 && !swStencil) { + struct radeon_renderbuffer *stencil = -+ radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT); ++ radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); + _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); + stencil->depthHasSurface = screen->depthHasSurface; + } @@ -7589,19 +7767,16 @@ index 84b5c46..10a49d2 100644 /** * Create the Mesa framebuffer and renderbuffers for a given window/drawable. -@@ -1105,6 +1358,11 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, +@@ -1103,7 +1376,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, + return (driDrawPriv->driverPrivate != NULL); + } } - - -+ -+ +- +#endif -+ -+ + static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) - { -@@ -1199,11 +1457,11 @@ radeonInitScreen(__DRIscreenPrivate *psp) +@@ -1199,11 +1472,11 @@ radeonInitScreen(__DRIscreenPrivate *psp) if (!radeonInitDriver(psp)) return NULL; diff --git a/sources b/sources index d1667ae..8c9b49d 100644 --- a/sources +++ b/sources @@ -1,2 +1,2 @@ 6ae05158e678f4594343f32c2ca50515 gl-manpages-1.0.1.tar.bz2 -937234d8b7b8528295b7080fbcf0a532 mesa-20080814.tar.bz2 +d5e2a6d63b4611ec38aaab19b8f68117 mesa-20080905.tar.bz2