From 660cc27a8b2f0218c9eff19726e4ae5ff3a7b1f7 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 14 Aug 2017 09:36:07 +0100 Subject: [PATCH] 17.2.0-rc4 --- 0001-Fix-linkage-against-shared-glapi.patch | 2 +- mesa-7.1-vc4-fixes.patch | 1450 ------------------- mesa-7.1.2-etnaviv-fixes.patch | 122 -- mesa-7.1.2-etnaviv-upstream-fixes.patch | 640 -------- mesa.spec | 17 +- sources | 2 +- 6 files changed, 11 insertions(+), 2222 deletions(-) delete mode 100644 mesa-7.1-vc4-fixes.patch delete mode 100644 mesa-7.1.2-etnaviv-fixes.patch delete mode 100644 mesa-7.1.2-etnaviv-upstream-fixes.patch diff --git a/0001-Fix-linkage-against-shared-glapi.patch b/0001-Fix-linkage-against-shared-glapi.patch index 7f8f716..bc70028 100644 --- a/0001-Fix-linkage-against-shared-glapi.patch +++ b/0001-Fix-linkage-against-shared-glapi.patch @@ -20,7 +20,7 @@ index 5d39486..04add87 100644 + $(top_builddir)/src/mapi/shared-glapi/libglapi.la \ $(SHARED_GLAPI_LIB) \ $(OSMESA_LIB_DEPS) \ - $(CLOCK_LIB) + $(CLOCK_LIB) \ -- 2.9.3 diff --git a/mesa-7.1-vc4-fixes.patch b/mesa-7.1-vc4-fixes.patch deleted file mode 100644 index 7bbefa7..0000000 --- a/mesa-7.1-vc4-fixes.patch +++ /dev/null @@ -1,1450 +0,0 @@ -From de31fe81a869c80b3cc08cb648640cf617e0d09c Mon Sep 17 00:00:00 2001 -From: Eric Anholt -Date: Thu, 15 Jun 2017 16:52:22 -0700 -Subject: [PATCH] vc4: Switch back to using a local copy of vc4_drm.h. - -Needing to get our uapi header from libdrm has only complicated things. -Follow intel's lead and drop our requirement for it. - -Generated from 056f4f02abb7e9e4a0cf0cda0211586df5e43842 of drm-misc-next - -(cherry picked from commit 1facea3486e3dd4e4a6cf561a725b9c4312ca58a) ---- - configure.ac | 2 - - src/gallium/drivers/vc4/Makefile.am | 3 +- - src/gallium/drivers/vc4/Makefile.sources | 1 + - src/gallium/drivers/vc4/drm_fourcc.h | 379 +++++++++++++++++++++++++++++++ - src/gallium/drivers/vc4/vc4_drm.h | 318 ++++++++++++++++++++++++++ - 5 files changed, 699 insertions(+), 4 deletions(-) - create mode 100644 src/gallium/drivers/vc4/drm_fourcc.h - create mode 100644 src/gallium/drivers/vc4/vc4_drm.h - -diff --git a/configure.ac b/configure.ac -index b069f54155..81258715b5 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -79,7 +79,6 @@ LIBDRM_INTEL_REQUIRED=2.4.75 - LIBDRM_NVVIEUX_REQUIRED=2.4.66 - LIBDRM_NOUVEAU_REQUIRED=2.4.66 - LIBDRM_FREEDRENO_REQUIRED=2.4.74 --LIBDRM_VC4_REQUIRED=2.4.69 - LIBDRM_ETNAVIV_REQUIRED=2.4.80 - - dnl Versions for external dependencies -@@ -2495,7 +2494,6 @@ if test -n "$with_gallium_drivers"; then - ;; - xvc4) - HAVE_GALLIUM_VC4=yes -- PKG_CHECK_MODULES([VC4], [libdrm >= $LIBDRM_VC4_REQUIRED libdrm_vc4 >= $LIBDRM_VC4_REQUIRED]) - require_libdrm "vc4" - - PKG_CHECK_MODULES([SIMPENROSE], [simpenrose], -diff --git a/src/gallium/drivers/vc4/Makefile.am b/src/gallium/drivers/vc4/Makefile.am -index b361a0c588..f6b87b2261 100644 ---- a/src/gallium/drivers/vc4/Makefile.am -+++ b/src/gallium/drivers/vc4/Makefile.am -@@ -29,7 +29,6 @@ endif - AM_CFLAGS = \ - -I$(top_builddir)/src/compiler/nir \ - $(LIBDRM_CFLAGS) \ -- $(VC4_CFLAGS) \ - $(GALLIUM_DRIVER_CFLAGS) \ - $(SIM_CFLAGS) \ - $(VALGRIND_CFLAGS) \ -@@ -38,7 +37,7 @@ AM_CFLAGS = \ - noinst_LTLIBRARIES = libvc4.la - - libvc4_la_SOURCES = $(C_SOURCES) --libvc4_la_LIBADD = $(SIM_LIB) $(VC4_LIBS) -+libvc4_la_LIBADD = $(SIM_LIB) - libvc4_la_LDFLAGS = $(SIM_LDFLAGS) - - noinst_LTLIBRARIES += libvc4_neon.la -diff --git a/src/gallium/drivers/vc4/Makefile.sources b/src/gallium/drivers/vc4/Makefile.sources -index 10de343612..cb04cc9c0a 100644 ---- a/src/gallium/drivers/vc4/Makefile.sources -+++ b/src/gallium/drivers/vc4/Makefile.sources -@@ -14,6 +14,7 @@ C_SOURCES := \ - vc4_context.c \ - vc4_context.h \ - vc4_draw.c \ -+ vc4_drm.h \ - vc4_emit.c \ - vc4_fence.c \ - vc4_formats.c \ -diff --git a/src/gallium/drivers/vc4/drm_fourcc.h b/src/gallium/drivers/vc4/drm_fourcc.h -new file mode 100644 -index 0000000000..7586c46f68 ---- /dev/null -+++ b/src/gallium/drivers/vc4/drm_fourcc.h -@@ -0,0 +1,379 @@ -+/* -+ * Copyright 2011 Intel Corporation -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#ifndef DRM_FOURCC_H -+#define DRM_FOURCC_H -+ -+#include "drm.h" -+ -+#if defined(__cplusplus) -+extern "C" { -+#endif -+ -+#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ -+ ((__u32)(c) << 16) | ((__u32)(d) << 24)) -+ -+#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ -+ -+/* color index */ -+#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ -+ -+/* 8 bpp Red */ -+#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ -+ -+/* 16 bpp Red */ -+#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ -+ -+/* 16 bpp RG */ -+#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ -+#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ -+ -+/* 32 bpp RG */ -+#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ -+#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ -+ -+/* 8 bpp RGB */ -+#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ -+#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ -+ -+/* 16 bpp RGB */ -+#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ -+#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ -+#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ -+#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ -+ -+#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ -+#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ -+#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ -+#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ -+ -+#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ -+#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ -+#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ -+#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ -+ -+#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ -+#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ -+#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ -+#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ -+ -+#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ -+#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ -+ -+/* 24 bpp RGB */ -+#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ -+#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ -+ -+/* 32 bpp RGB */ -+#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ -+#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ -+#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ -+#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ -+ -+#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ -+#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ -+#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ -+#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ -+ -+#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ -+#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ -+#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ -+#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ -+ -+#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ -+#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ -+#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ -+#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ -+ -+/* packed YCbCr */ -+#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ -+#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ -+#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ -+#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ -+ -+#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ -+ -+/* -+ * 2 plane RGB + A -+ * index 0 = RGB plane, same format as the corresponding non _A8 format has -+ * index 1 = A plane, [7:0] A -+ */ -+#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') -+#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') -+#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') -+#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') -+#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') -+#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') -+#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') -+#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') -+ -+/* -+ * 2 plane YCbCr -+ * index 0 = Y plane, [7:0] Y -+ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian -+ * or -+ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian -+ */ -+#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ -+#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ -+#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ -+ -+/* -+ * 3 plane YCbCr -+ * index 0: Y plane, [7:0] Y -+ * index 1: Cb plane, [7:0] Cb -+ * index 2: Cr plane, [7:0] Cr -+ * or -+ * index 1: Cr plane, [7:0] Cr -+ * index 2: Cb plane, [7:0] Cb -+ */ -+#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ -+ -+ -+/* -+ * Format Modifiers: -+ * -+ * Format modifiers describe, typically, a re-ordering or modification -+ * of the data in a plane of an FB. This can be used to express tiled/ -+ * swizzled formats, or compression, or a combination of the two. -+ * -+ * The upper 8 bits of the format modifier are a vendor-id as assigned -+ * below. The lower 56 bits are assigned as vendor sees fit. -+ */ -+ -+/* Vendor Ids: */ -+#define DRM_FORMAT_MOD_NONE 0 -+#define DRM_FORMAT_MOD_VENDOR_NONE 0 -+#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 -+#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 -+#define DRM_FORMAT_MOD_VENDOR_NV 0x03 -+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 -+#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 -+#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 -+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 -+/* add more to the end as needed */ -+ -+#define fourcc_mod_code(vendor, val) \ -+ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) -+ -+/* -+ * Format Modifier tokens: -+ * -+ * When adding a new token please document the layout with a code comment, -+ * similar to the fourcc codes above. drm_fourcc.h is considered the -+ * authoritative source for all of these. -+ */ -+ -+/* -+ * Linear Layout -+ * -+ * Just plain linear layout. Note that this is different from no specifying any -+ * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), -+ * which tells the driver to also take driver-internal information into account -+ * and so might actually result in a tiled framebuffer. -+ */ -+#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) -+ -+/* Intel framebuffer modifiers */ -+ -+/* -+ * Intel X-tiling layout -+ * -+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) -+ * in row-major layout. Within the tile bytes are laid out row-major, with -+ * a platform-dependent stride. On top of that the memory can apply -+ * platform-depending swizzling of some higher address bits into bit6. -+ * -+ * This format is highly platforms specific and not useful for cross-driver -+ * sharing. It exists since on a given platform it does uniquely identify the -+ * layout in a simple way for i915-specific userspace. -+ */ -+#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) -+ -+/* -+ * Intel Y-tiling layout -+ * -+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) -+ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) -+ * chunks column-major, with a platform-dependent height. On top of that the -+ * memory can apply platform-depending swizzling of some higher address bits -+ * into bit6. -+ * -+ * This format is highly platforms specific and not useful for cross-driver -+ * sharing. It exists since on a given platform it does uniquely identify the -+ * layout in a simple way for i915-specific userspace. -+ */ -+#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) -+ -+/* -+ * Intel Yf-tiling layout -+ * -+ * This is a tiled layout using 4Kb tiles in row-major layout. -+ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which -+ * are arranged in four groups (two wide, two high) with column-major layout. -+ * Each group therefore consits out of four 256 byte units, which are also laid -+ * out as 2x2 column-major. -+ * 256 byte units are made out of four 64 byte blocks of pixels, producing -+ * either a square block or a 2:1 unit. -+ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width -+ * in pixel depends on the pixel depth. -+ */ -+#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) -+ -+/* -+ * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks -+ * -+ * Macroblocks are laid in a Z-shape, and each pixel data is following the -+ * standard NV12 style. -+ * As for NV12, an image is the result of two frame buffers: one for Y, -+ * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). -+ * Alignment requirements are (for each buffer): -+ * - multiple of 128 pixels for the width -+ * - multiple of 32 pixels for the height -+ * -+ * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html -+ */ -+#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) -+ -+/* Vivante framebuffer modifiers */ -+ -+/* -+ * Vivante 4x4 tiling layout -+ * -+ * This is a simple tiled layout using tiles of 4x4 pixels in a row-major -+ * layout. -+ */ -+#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) -+ -+/* -+ * Vivante 64x64 super-tiling layout -+ * -+ * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile -+ * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- -+ * major layout. -+ * -+ * For more information: see -+ * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling -+ */ -+#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) -+ -+/* -+ * Vivante 4x4 tiling layout for dual-pipe -+ * -+ * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a -+ * different base address. Offsets from the base addresses are therefore halved -+ * compared to the non-split tiled layout. -+ */ -+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) -+ -+/* -+ * Vivante 64x64 super-tiling layout for dual-pipe -+ * -+ * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile -+ * starts at a different base address. Offsets from the base addresses are -+ * therefore halved compared to the non-split super-tiled layout. -+ */ -+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) -+ -+/* NVIDIA Tegra frame buffer modifiers */ -+ -+/* -+ * Some modifiers take parameters, for example the number of vertical GOBs in -+ * a block. Reserve the lower 32 bits for parameters -+ */ -+#define __fourcc_mod_tegra_mode_shift 32 -+#define fourcc_mod_tegra_code(val, params) \ -+ fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) -+#define fourcc_mod_tegra_mod(m) \ -+ (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -+#define fourcc_mod_tegra_param(m) \ -+ (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -+ -+/* -+ * Tegra Tiled Layout, used by Tegra 2, 3 and 4. -+ * -+ * Pixels are arranged in simple tiles of 16 x 16 bytes. -+ */ -+#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) -+ -+/* -+ * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 -+ * -+ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked -+ * vertically by a power of 2 (1 to 32 GOBs) to form a block. -+ * -+ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. -+ * -+ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. -+ * Valid values are: -+ * -+ * 0 == ONE_GOB -+ * 1 == TWO_GOBS -+ * 2 == FOUR_GOBS -+ * 3 == EIGHT_GOBS -+ * 4 == SIXTEEN_GOBS -+ * 5 == THIRTYTWO_GOBS -+ * -+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format -+ * in full detail. -+ */ -+#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) -+ -+/* -+ * Broadcom VC4 "T" format -+ * -+ * This is the primary layout that the V3D GPU can texture from (it -+ * can't do linear). The T format has: -+ * -+ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 -+ * pixels at 32 bit depth. -+ * -+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually -+ * 16x16 pixels). -+ * -+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On -+ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows -+ * they're (TR, BR, BL, TL), where bottom left is start of memory. -+ * -+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k -+ * tiles) or right-to-left (odd rows of 4k tiles). -+ */ -+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) -+ -+#if defined(__cplusplus) -+} -+#endif -+ -+#endif /* DRM_FOURCC_H */ -diff --git a/src/gallium/drivers/vc4/vc4_drm.h b/src/gallium/drivers/vc4/vc4_drm.h -new file mode 100644 -index 0000000000..0caeaf3a1f ---- /dev/null -+++ b/src/gallium/drivers/vc4/vc4_drm.h -@@ -0,0 +1,318 @@ -+/* -+ * Copyright © 2014-2015 Broadcom -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ */ -+ -+#ifndef _VC4_DRM_H_ -+#define _VC4_DRM_H_ -+ -+#include "drm.h" -+ -+#if defined(__cplusplus) -+extern "C" { -+#endif -+ -+#define DRM_VC4_SUBMIT_CL 0x00 -+#define DRM_VC4_WAIT_SEQNO 0x01 -+#define DRM_VC4_WAIT_BO 0x02 -+#define DRM_VC4_CREATE_BO 0x03 -+#define DRM_VC4_MMAP_BO 0x04 -+#define DRM_VC4_CREATE_SHADER_BO 0x05 -+#define DRM_VC4_GET_HANG_STATE 0x06 -+#define DRM_VC4_GET_PARAM 0x07 -+#define DRM_VC4_SET_TILING 0x08 -+#define DRM_VC4_GET_TILING 0x09 -+ -+#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) -+#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) -+#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) -+#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) -+#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) -+#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) -+#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) -+#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) -+#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) -+#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) -+ -+struct drm_vc4_submit_rcl_surface { -+ __u32 hindex; /* Handle index, or ~0 if not present. */ -+ __u32 offset; /* Offset to start of buffer. */ -+ /* -+ * Bits for either render config (color_write) or load/store packet. -+ * Bits should all be 0 for MSAA load/stores. -+ */ -+ __u16 bits; -+ -+#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) -+ __u16 flags; -+}; -+ -+/** -+ * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D -+ * engine. -+ * -+ * Drivers typically use GPU BOs to store batchbuffers / command lists and -+ * their associated state. However, because the VC4 lacks an MMU, we have to -+ * do validation of memory accesses by the GPU commands. If we were to store -+ * our commands in BOs, we'd need to do uncached readback from them to do the -+ * validation process, which is too expensive. Instead, userspace accumulates -+ * commands and associated state in plain memory, then the kernel copies the -+ * data to its own address space, and then validates and stores it in a GPU -+ * BO. -+ */ -+struct drm_vc4_submit_cl { -+ /* Pointer to the binner command list. -+ * -+ * This is the first set of commands executed, which runs the -+ * coordinate shader to determine where primitives land on the screen, -+ * then writes out the state updates and draw calls necessary per tile -+ * to the tile allocation BO. -+ */ -+ __u64 bin_cl; -+ -+ /* Pointer to the shader records. -+ * -+ * Shader records are the structures read by the hardware that contain -+ * pointers to uniforms, shaders, and vertex attributes. The -+ * reference to the shader record has enough information to determine -+ * how many pointers are necessary (fixed number for shaders/uniforms, -+ * and an attribute count), so those BO indices into bo_handles are -+ * just stored as __u32s before each shader record passed in. -+ */ -+ __u64 shader_rec; -+ -+ /* Pointer to uniform data and texture handles for the textures -+ * referenced by the shader. -+ * -+ * For each shader state record, there is a set of uniform data in the -+ * order referenced by the record (FS, VS, then CS). Each set of -+ * uniform data has a __u32 index into bo_handles per texture -+ * sample operation, in the order the QPU_W_TMUn_S writes appear in -+ * the program. Following the texture BO handle indices is the actual -+ * uniform data. -+ * -+ * The individual uniform state blocks don't have sizes passed in, -+ * because the kernel has to determine the sizes anyway during shader -+ * code validation. -+ */ -+ __u64 uniforms; -+ __u64 bo_handles; -+ -+ /* Size in bytes of the binner command list. */ -+ __u32 bin_cl_size; -+ /* Size in bytes of the set of shader records. */ -+ __u32 shader_rec_size; -+ /* Number of shader records. -+ * -+ * This could just be computed from the contents of shader_records and -+ * the address bits of references to them from the bin CL, but it -+ * keeps the kernel from having to resize some allocations it makes. -+ */ -+ __u32 shader_rec_count; -+ /* Size in bytes of the uniform state. */ -+ __u32 uniforms_size; -+ -+ /* Number of BO handles passed in (size is that times 4). */ -+ __u32 bo_handle_count; -+ -+ /* RCL setup: */ -+ __u16 width; -+ __u16 height; -+ __u8 min_x_tile; -+ __u8 min_y_tile; -+ __u8 max_x_tile; -+ __u8 max_y_tile; -+ struct drm_vc4_submit_rcl_surface color_read; -+ struct drm_vc4_submit_rcl_surface color_write; -+ struct drm_vc4_submit_rcl_surface zs_read; -+ struct drm_vc4_submit_rcl_surface zs_write; -+ struct drm_vc4_submit_rcl_surface msaa_color_write; -+ struct drm_vc4_submit_rcl_surface msaa_zs_write; -+ __u32 clear_color[2]; -+ __u32 clear_z; -+ __u8 clear_s; -+ -+ __u32 pad:24; -+ -+#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) -+ __u32 flags; -+ -+ /* Returned value of the seqno of this render job (for the -+ * wait ioctl). -+ */ -+ __u64 seqno; -+}; -+ -+/** -+ * struct drm_vc4_wait_seqno - ioctl argument for waiting for -+ * DRM_VC4_SUBMIT_CL completion using its returned seqno. -+ * -+ * timeout_ns is the timeout in nanoseconds, where "0" means "don't -+ * block, just return the status." -+ */ -+struct drm_vc4_wait_seqno { -+ __u64 seqno; -+ __u64 timeout_ns; -+}; -+ -+/** -+ * struct drm_vc4_wait_bo - ioctl argument for waiting for -+ * completion of the last DRM_VC4_SUBMIT_CL on a BO. -+ * -+ * This is useful for cases where multiple processes might be -+ * rendering to a BO and you want to wait for all rendering to be -+ * completed. -+ */ -+struct drm_vc4_wait_bo { -+ __u32 handle; -+ __u32 pad; -+ __u64 timeout_ns; -+}; -+ -+/** -+ * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. -+ * -+ * There are currently no values for the flags argument, but it may be -+ * used in a future extension. -+ */ -+struct drm_vc4_create_bo { -+ __u32 size; -+ __u32 flags; -+ /** Returned GEM handle for the BO. */ -+ __u32 handle; -+ __u32 pad; -+}; -+ -+/** -+ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. -+ * -+ * This doesn't actually perform an mmap. Instead, it returns the -+ * offset you need to use in an mmap on the DRM device node. This -+ * means that tools like valgrind end up knowing about the mapped -+ * memory. -+ * -+ * There are currently no values for the flags argument, but it may be -+ * used in a future extension. -+ */ -+struct drm_vc4_mmap_bo { -+ /** Handle for the object being mapped. */ -+ __u32 handle; -+ __u32 flags; -+ /** offset into the drm node to use for subsequent mmap call. */ -+ __u64 offset; -+}; -+ -+/** -+ * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 -+ * shader BOs. -+ * -+ * Since allowing a shader to be overwritten while it's also being -+ * executed from would allow privlege escalation, shaders must be -+ * created using this ioctl, and they can't be mmapped later. -+ */ -+struct drm_vc4_create_shader_bo { -+ /* Size of the data argument. */ -+ __u32 size; -+ /* Flags, currently must be 0. */ -+ __u32 flags; -+ -+ /* Pointer to the data. */ -+ __u64 data; -+ -+ /** Returned GEM handle for the BO. */ -+ __u32 handle; -+ /* Pad, must be 0. */ -+ __u32 pad; -+}; -+ -+struct drm_vc4_get_hang_state_bo { -+ __u32 handle; -+ __u32 paddr; -+ __u32 size; -+ __u32 pad; -+}; -+ -+/** -+ * struct drm_vc4_hang_state - ioctl argument for collecting state -+ * from a GPU hang for analysis. -+*/ -+struct drm_vc4_get_hang_state { -+ /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ -+ __u64 bo; -+ /** -+ * On input, the size of the bo array. Output is the number -+ * of bos to be returned. -+ */ -+ __u32 bo_count; -+ -+ __u32 start_bin, start_render; -+ -+ __u32 ct0ca, ct0ea; -+ __u32 ct1ca, ct1ea; -+ __u32 ct0cs, ct1cs; -+ __u32 ct0ra0, ct1ra0; -+ -+ __u32 bpca, bpcs; -+ __u32 bpoa, bpos; -+ -+ __u32 vpmbase; -+ -+ __u32 dbge; -+ __u32 fdbgo; -+ __u32 fdbgb; -+ __u32 fdbgr; -+ __u32 fdbgs; -+ __u32 errstat; -+ -+ /* Pad that we may save more registers into in the future. */ -+ __u32 pad[16]; -+}; -+ -+#define DRM_VC4_PARAM_V3D_IDENT0 0 -+#define DRM_VC4_PARAM_V3D_IDENT1 1 -+#define DRM_VC4_PARAM_V3D_IDENT2 2 -+#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 -+#define DRM_VC4_PARAM_SUPPORTS_ETC1 4 -+#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 -+ -+struct drm_vc4_get_param { -+ __u32 param; -+ __u32 pad; -+ __u64 value; -+}; -+ -+struct drm_vc4_get_tiling { -+ __u32 handle; -+ __u32 flags; -+ __u64 modifier; -+}; -+ -+struct drm_vc4_set_tiling { -+ __u32 handle; -+ __u32 flags; -+ __u64 modifier; -+}; -+ -+#if defined(__cplusplus) -+} -+#endif -+ -+#endif /* _VC4_DRM_H_ */ -From 0670340bc6730e3de453e064b8a883a829900945 Mon Sep 17 00:00:00 2001 -From: Eric Anholt -Date: Mon, 8 May 2017 16:43:06 -0700 -Subject: [PATCH] vc4: Drop the u_resource_vtbl no-op layer. - -We only ever attached one vtbl, so it was a waste of space and -indirections. - -(cherry picked from commit 76e4ab57158de8a568572f1acb1d679ce8abb288) ---- - src/gallium/drivers/vc4/vc4_resource.c | 50 +++++++++++++++------------------ - src/gallium/drivers/vc4/vc4_resource.h | 2 +- - src/gallium/drivers/vc4/vc4_simulator.c | 4 +-- - src/gallium/drivers/vc4/vc4_state.c | 4 +-- - 4 files changed, 27 insertions(+), 33 deletions(-) - -diff --git a/src/gallium/drivers/vc4/vc4_resource.c b/src/gallium/drivers/vc4/vc4_resource.c -index 596f73dfbf..3b326adbdc 100644 ---- a/src/gallium/drivers/vc4/vc4_resource.c -+++ b/src/gallium/drivers/vc4/vc4_resource.c -@@ -39,7 +39,7 @@ static bool miptree_debug = false; - static bool - vc4_resource_bo_alloc(struct vc4_resource *rsc) - { -- struct pipe_resource *prsc = &rsc->base.b; -+ struct pipe_resource *prsc = &rsc->base; - struct pipe_screen *pscreen = prsc->screen; - struct vc4_bo *bo; - -@@ -379,8 +379,10 @@ vc4_resource_destroy(struct pipe_screen *pscreen, - - static boolean - vc4_resource_get_handle(struct pipe_screen *pscreen, -+ struct pipe_context *pctx, - struct pipe_resource *prsc, -- struct winsys_handle *handle) -+ struct winsys_handle *handle, -+ unsigned usage) - { - struct vc4_resource *rsc = vc4_resource(prsc); - -@@ -388,18 +390,10 @@ vc4_resource_get_handle(struct pipe_screen *pscreen, - handle); - } - --static const struct u_resource_vtbl vc4_resource_vtbl = { -- .resource_get_handle = vc4_resource_get_handle, -- .resource_destroy = vc4_resource_destroy, -- .transfer_map = vc4_resource_transfer_map, -- .transfer_flush_region = u_default_transfer_flush_region, -- .transfer_unmap = vc4_resource_transfer_unmap, --}; -- - static void - vc4_setup_slices(struct vc4_resource *rsc) - { -- struct pipe_resource *prsc = &rsc->base.b; -+ struct pipe_resource *prsc = &rsc->base; - uint32_t width = prsc->width0; - uint32_t height = prsc->height0; - if (prsc->format == PIPE_FORMAT_ETC1_RGB8) { -@@ -502,14 +496,13 @@ vc4_resource_setup(struct pipe_screen *pscreen, - struct vc4_resource *rsc = CALLOC_STRUCT(vc4_resource); - if (!rsc) - return NULL; -- struct pipe_resource *prsc = &rsc->base.b; -+ struct pipe_resource *prsc = &rsc->base; - - *prsc = *tmpl; - - pipe_reference_init(&prsc->reference, 1); - prsc->screen = pscreen; - -- rsc->base.vtbl = &vc4_resource_vtbl; - if (prsc->nr_samples <= 1) - rsc->cpp = util_format_get_blocksize(tmpl->format); - else -@@ -543,7 +536,7 @@ vc4_resource_create(struct pipe_screen *pscreen, - const struct pipe_resource *tmpl) - { - struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl); -- struct pipe_resource *prsc = &rsc->base.b; -+ struct pipe_resource *prsc = &rsc->base; - - /* We have to make shared be untiled, since we don't have any way to - * communicate metadata about tiling currently. -@@ -579,7 +572,7 @@ vc4_resource_from_handle(struct pipe_screen *pscreen, - unsigned usage) - { - struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl); -- struct pipe_resource *prsc = &rsc->base.b; -+ struct pipe_resource *prsc = &rsc->base; - struct vc4_resource_slice *slice = &rsc->slices[0]; - uint32_t expected_stride = - align(prsc->width0, vc4_utile_width(rsc->cpp)) * rsc->cpp; -@@ -925,16 +918,16 @@ vc4_update_shadow_baselevel_texture(struct pipe_context *pctx, - return; - - perf_debug("Updating %dx%d@%d shadow texture due to %s\n", -- orig->base.b.width0, orig->base.b.height0, -+ orig->base.width0, orig->base.height0, - view->u.tex.first_level, - view->u.tex.first_level ? "base level" : "raster layout"); - -- for (int i = 0; i <= shadow->base.b.last_level; i++) { -- unsigned width = u_minify(shadow->base.b.width0, i); -- unsigned height = u_minify(shadow->base.b.height0, i); -+ for (int i = 0; i <= shadow->base.last_level; i++) { -+ unsigned width = u_minify(shadow->base.width0, i); -+ unsigned height = u_minify(shadow->base.height0, i); - struct pipe_blit_info info = { - .dst = { -- .resource = &shadow->base.b, -+ .resource = &shadow->base, - .level = i, - .box = { - .x = 0, -@@ -944,10 +937,10 @@ vc4_update_shadow_baselevel_texture(struct pipe_context *pctx, - .height = height, - .depth = 1, - }, -- .format = shadow->base.b.format, -+ .format = shadow->base.format, - }, - .src = { -- .resource = &orig->base.b, -+ .resource = &orig->base, - .level = view->u.tex.first_level + i, - .box = { - .x = 0, -@@ -957,7 +950,7 @@ vc4_update_shadow_baselevel_texture(struct pipe_context *pctx, - .height = height, - .depth = 1, - }, -- .format = orig->base.b.format, -+ .format = orig->base.format, - }, - .mask = ~0, - }; -@@ -999,7 +992,7 @@ vc4_get_shadow_index_buffer(struct pipe_context *pctx, - if (ib->user_buffer) { - src = ib->user_buffer; - } else { -- src = pipe_buffer_map_range(pctx, &orig->base.b, -+ src = pipe_buffer_map_range(pctx, &orig->base, - ib->offset, - count * 4, - PIPE_TRANSFER_READ, &src_transfer); -@@ -1022,16 +1015,17 @@ vc4_resource_screen_init(struct pipe_screen *pscreen) - { - pscreen->resource_create = vc4_resource_create; - pscreen->resource_from_handle = vc4_resource_from_handle; -- pscreen->resource_get_handle = u_resource_get_handle_vtbl; - pscreen->resource_destroy = u_resource_destroy_vtbl; -+ pscreen->resource_get_handle = vc4_resource_get_handle; -+ pscreen->resource_destroy = vc4_resource_destroy; - } - - void - vc4_resource_context_init(struct pipe_context *pctx) - { -- pctx->transfer_map = u_transfer_map_vtbl; -- pctx->transfer_flush_region = u_transfer_flush_region_vtbl; -- pctx->transfer_unmap = u_transfer_unmap_vtbl; -+ pctx->transfer_map = vc4_resource_transfer_map; -+ pctx->transfer_flush_region = u_default_transfer_flush_region; -+ pctx->transfer_unmap = vc4_resource_transfer_unmap; - pctx->buffer_subdata = u_default_buffer_subdata; - pctx->texture_subdata = u_default_texture_subdata; - pctx->create_surface = vc4_create_surface; -diff --git a/src/gallium/drivers/vc4/vc4_resource.h b/src/gallium/drivers/vc4/vc4_resource.h -index 27aa4e8728..1a771ff299 100644 ---- a/src/gallium/drivers/vc4/vc4_resource.h -+++ b/src/gallium/drivers/vc4/vc4_resource.h -@@ -52,7 +52,7 @@ struct vc4_surface { - }; - - struct vc4_resource { -- struct u_resource base; -+ struct pipe_resource base; - struct vc4_bo *bo; - struct vc4_resource_slice slices[VC4_MAX_MIP_LEVELS]; - uint32_t cube_map_stride; -diff --git a/src/gallium/drivers/vc4/vc4_simulator.c b/src/gallium/drivers/vc4/vc4_simulator.c -index 9565c49efb..ab701ab560 100644 ---- a/src/gallium/drivers/vc4/vc4_simulator.c -+++ b/src/gallium/drivers/vc4/vc4_simulator.c -@@ -387,7 +387,7 @@ vc4_simulator_flush(struct vc4_context *vc4, - ctex->bo->size); - #endif - -- for (int y = 0; y < ctex->base.b.height0; y++) { -+ for (int y = 0; y < ctex->base.height0; y++) { - memcpy(ctex->bo->map + y * sim_stride, - csim_bo->winsys_map + y * winsys_stride, - row_len); -@@ -448,7 +448,7 @@ vc4_simulator_flush(struct vc4_context *vc4, - } - - if (ctex && csim_bo->winsys_map) { -- for (int y = 0; y < ctex->base.b.height0; y++) { -+ for (int y = 0; y < ctex->base.height0; y++) { - memcpy(csim_bo->winsys_map + y * winsys_stride, - ctex->bo->map + y * sim_stride, - row_len); -diff --git a/src/gallium/drivers/vc4/vc4_state.c b/src/gallium/drivers/vc4/vc4_state.c -index 2e00104e45..31ec19bcbe 100644 ---- a/src/gallium/drivers/vc4/vc4_state.c -+++ b/src/gallium/drivers/vc4/vc4_state.c -@@ -575,7 +575,7 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, - (cso->u.tex.first_level != cso->u.tex.last_level)) || - rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R) { - struct vc4_resource *shadow_parent = vc4_resource(prsc); -- struct pipe_resource tmpl = shadow_parent->base.b; -+ struct pipe_resource tmpl = shadow_parent->base; - struct vc4_resource *clone; - - tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; -@@ -590,7 +590,7 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, - } - rsc = vc4_resource(prsc); - clone = vc4_resource(prsc); -- clone->shadow_parent = &shadow_parent->base.b; -+ clone->shadow_parent = &shadow_parent->base; - /* Flag it as needing update of the contents from the parent. */ - clone->writes = shadow_parent->writes - 1; - -From 64a91342aeb0c4a795f2184e22b15cf3079fc6ca Mon Sep 17 00:00:00 2001 -From: Eric Anholt -Date: Mon, 8 May 2017 16:46:59 -0700 -Subject: [PATCH] vc4: Drop pointless indirections around BO import/export. - -I've since found them to be more confusing by adding indirections than -clarifying by screening off resources from the handle/fd import/export -process. - -(cherry picked from commit 50e78cd04f6b40c4cf02774861380d843b00ebb9) ---- - src/gallium/drivers/vc4/vc4_resource.c | 57 +++++++++++++++++++++++++++++----- - src/gallium/drivers/vc4/vc4_screen.c | 54 -------------------------------- - src/gallium/drivers/vc4/vc4_screen.h | 7 ----- - 3 files changed, 49 insertions(+), 69 deletions(-) - -diff --git a/src/gallium/drivers/vc4/vc4_resource.c b/src/gallium/drivers/vc4/vc4_resource.c -index 3b326adbdc..7c868b39ec 100644 ---- a/src/gallium/drivers/vc4/vc4_resource.c -+++ b/src/gallium/drivers/vc4/vc4_resource.c -@@ -381,13 +381,31 @@ static boolean - vc4_resource_get_handle(struct pipe_screen *pscreen, - struct pipe_context *pctx, - struct pipe_resource *prsc, -- struct winsys_handle *handle, -+ struct winsys_handle *whandle, - unsigned usage) - { - struct vc4_resource *rsc = vc4_resource(prsc); - -- return vc4_screen_bo_get_handle(pscreen, rsc->bo, rsc->slices[0].stride, -- handle); -+ whandle->stride = rsc->slices[0].stride; -+ -+ /* If we're passing some reference to our BO out to some other part of -+ * the system, then we can't do any optimizations about only us being -+ * the ones seeing it (like BO caching or shadow update avoidance). -+ */ -+ rsc->bo->private = false; -+ -+ switch (whandle->type) { -+ case DRM_API_HANDLE_TYPE_SHARED: -+ return vc4_bo_flink(rsc->bo, &whandle->handle); -+ case DRM_API_HANDLE_TYPE_KMS: -+ whandle->handle = rsc->bo->handle; -+ return TRUE; -+ case DRM_API_HANDLE_TYPE_FD: -+ whandle->handle = vc4_bo_get_dmabuf(rsc->bo); -+ return whandle->handle != -1; -+ } -+ -+ return FALSE; - } - - static void -@@ -568,9 +586,10 @@ vc4_resource_create(struct pipe_screen *pscreen, - static struct pipe_resource * - vc4_resource_from_handle(struct pipe_screen *pscreen, - const struct pipe_resource *tmpl, -- struct winsys_handle *handle, -+ struct winsys_handle *whandle, - unsigned usage) - { -+ struct vc4_screen *screen = vc4_screen(pscreen); - struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl); - struct pipe_resource *prsc = &rsc->base; - struct vc4_resource_slice *slice = &rsc->slices[0]; -@@ -580,7 +599,7 @@ vc4_resource_from_handle(struct pipe_screen *pscreen, - if (!rsc) - return NULL; - -- if (handle->stride != expected_stride) { -+ if (whandle->stride != expected_stride) { - static bool warned = false; - if (!warned) { - warned = true; -@@ -589,18 +608,40 @@ vc4_resource_from_handle(struct pipe_screen *pscreen, - "unsupported stride %d instead of %d\n", - prsc->width0, prsc->height0, - util_format_short_name(prsc->format), -- handle->stride, -+ whandle->stride, - expected_stride); - } - goto fail; - } - - rsc->tiled = false; -- rsc->bo = vc4_screen_bo_from_handle(pscreen, handle); -+ -+ if (whandle->offset != 0) { -+ fprintf(stderr, -+ "Attempt to import unsupported winsys offset %u\n", -+ whandle->offset); -+ return NULL; -+ } -+ -+ switch (whandle->type) { -+ case DRM_API_HANDLE_TYPE_SHARED: -+ rsc->bo = vc4_bo_open_name(screen, -+ whandle->handle, whandle->stride); -+ break; -+ case DRM_API_HANDLE_TYPE_FD: -+ rsc->bo = vc4_bo_open_dmabuf(screen, -+ whandle->handle, whandle->stride); -+ break; -+ default: -+ fprintf(stderr, -+ "Attempt to import unsupported handle type %d\n", -+ whandle->type); -+ } -+ - if (!rsc->bo) - goto fail; - -- slice->stride = handle->stride; -+ slice->stride = whandle->stride; - slice->tiling = VC4_TILING_FORMAT_LINEAR; - - rsc->vc4_format = get_resource_texture_format(prsc); -diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c -index 27d23dc964..405a13f16e 100644 ---- a/src/gallium/drivers/vc4/vc4_screen.c -+++ b/src/gallium/drivers/vc4/vc4_screen.c -@@ -654,57 +654,3 @@ vc4_screen_create(int fd) - ralloc_free(pscreen); - return NULL; - } -- --boolean --vc4_screen_bo_get_handle(struct pipe_screen *pscreen, -- struct vc4_bo *bo, -- unsigned stride, -- struct winsys_handle *whandle) --{ -- whandle->stride = stride; -- -- /* If we're passing some reference to our BO out to some other part of -- * the system, then we can't do any optimizations about only us being -- * the ones seeing it (like BO caching or shadow update avoidance). -- */ -- bo->private = false; -- -- switch (whandle->type) { -- case DRM_API_HANDLE_TYPE_SHARED: -- return vc4_bo_flink(bo, &whandle->handle); -- case DRM_API_HANDLE_TYPE_KMS: -- whandle->handle = bo->handle; -- return TRUE; -- case DRM_API_HANDLE_TYPE_FD: -- whandle->handle = vc4_bo_get_dmabuf(bo); -- return whandle->handle != -1; -- } -- -- return FALSE; --} -- --struct vc4_bo * --vc4_screen_bo_from_handle(struct pipe_screen *pscreen, -- struct winsys_handle *whandle) --{ -- struct vc4_screen *screen = vc4_screen(pscreen); -- -- if (whandle->offset != 0) { -- fprintf(stderr, -- "Attempt to import unsupported winsys offset %u\n", -- whandle->offset); -- return NULL; -- } -- -- switch (whandle->type) { -- case DRM_API_HANDLE_TYPE_SHARED: -- return vc4_bo_open_name(screen, whandle->handle, whandle->stride); -- case DRM_API_HANDLE_TYPE_FD: -- return vc4_bo_open_dmabuf(screen, whandle->handle, whandle->stride); -- default: -- fprintf(stderr, -- "Attempt to import unsupported handle type %d\n", -- whandle->type); -- return NULL; -- } --} -diff --git a/src/gallium/drivers/vc4/vc4_screen.h b/src/gallium/drivers/vc4/vc4_screen.h -index 34d15381ae..0f80ffb346 100644 ---- a/src/gallium/drivers/vc4/vc4_screen.h -+++ b/src/gallium/drivers/vc4/vc4_screen.h -@@ -102,13 +102,6 @@ vc4_screen(struct pipe_screen *screen) - } - - struct pipe_screen *vc4_screen_create(int fd); --boolean vc4_screen_bo_get_handle(struct pipe_screen *pscreen, -- struct vc4_bo *bo, -- unsigned stride, -- struct winsys_handle *whandle); --struct vc4_bo * --vc4_screen_bo_from_handle(struct pipe_screen *pscreen, -- struct winsys_handle *whandle); - - const void * - vc4_screen_get_compiler_options(struct pipe_screen *pscreen, -From 427bd8275b9d4bb7a52d4e0dd4881a91a96c9c5b Mon Sep 17 00:00:00 2001 -From: Eric Anholt -Date: Mon, 5 Jun 2017 14:50:26 -0700 -Subject: [PATCH] vc4: Set shareable BOs as T tiled if possible. - -X11 and GL compositor performance on VC4 has been terrible because of our -SHARED-usage buffers all being forced to linear. This swaps SHARED && -!LINEAR buffers over to being tiled. - -This is an expected win for all GL compositors during rendering (a full -copy of each shared texture per draw call), allows X11 to be used with -decent performance without a GL compositor, and improves X11 windowed -swapbuffers performance as well. It also halves the memory usage of -shared buffers that get textured from. The only cost should be idle -systems with a scanout-only buffer that isn't flagged as LINEAR, in which -case the memory bandwidth cost of scanout goes up ~25%. - -(cherry picked from commit ba654a2fc194f38262a290c378f581fbf280efe2) ---- - src/gallium/drivers/vc4/vc4_bufmgr.c | 7 +++ - src/gallium/drivers/vc4/vc4_resource.c | 108 ++++++++++++++++++++++---------- - src/gallium/drivers/vc4/vc4_simulator.c | 8 +++ - 3 files changed, 90 insertions(+), 33 deletions(-) - -diff --git a/src/gallium/drivers/vc4/vc4_bufmgr.c b/src/gallium/drivers/vc4/vc4_bufmgr.c -index 12af7f8a9e..25e95ff3c5 100644 ---- a/src/gallium/drivers/vc4/vc4_bufmgr.c -+++ b/src/gallium/drivers/vc4/vc4_bufmgr.c -@@ -27,6 +27,7 @@ - #include - #include - #include -+#include - - #include "util/u_hash_table.h" - #include "util/u_memory.h" -@@ -282,6 +283,12 @@ vc4_bo_last_unreference_locked_timed(struct vc4_bo *bo, time_t time) - return; - } - -+ struct drm_vc4_set_tiling set_tiling = { -+ .handle = bo->handle, -+ .modifier = DRM_FORMAT_MOD_NONE, -+ }; -+ (void)vc4_ioctl(screen->fd, DRM_IOCTL_VC4_SET_TILING, &set_tiling); -+ - if (cache->size_list_size <= page_index) { - struct list_head *new_list = - ralloc_array(screen, struct list_head, page_index + 1); -diff --git a/src/gallium/drivers/vc4/vc4_resource.c b/src/gallium/drivers/vc4/vc4_resource.c -index 7c868b39ec..eb462707a7 100644 ---- a/src/gallium/drivers/vc4/vc4_resource.c -+++ b/src/gallium/drivers/vc4/vc4_resource.c -@@ -29,10 +29,12 @@ - #include "util/u_surface.h" - #include "util/u_upload_mgr.h" - -+#include "vc4_drm.h" - #include "vc4_screen.h" - #include "vc4_context.h" - #include "vc4_resource.h" - #include "vc4_tiling.h" -+#include "drm_fourcc.h" - - static bool miptree_debug = false; - -@@ -553,30 +555,67 @@ struct pipe_resource * - vc4_resource_create(struct pipe_screen *pscreen, - const struct pipe_resource *tmpl) - { -+ struct vc4_screen *screen = vc4_screen(pscreen); - struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl); - struct pipe_resource *prsc = &rsc->base; - -- /* We have to make shared be untiled, since we don't have any way to -- * communicate metadata about tiling currently. -+ /* Use a tiled layout if we can, for better 3D performance. */ -+ rsc->tiled = true; -+ -+ /* VBOs/PBOs are untiled (and 1 height). */ -+ if (tmpl->target == PIPE_BUFFER) -+ rsc->tiled = false; -+ -+ /* MSAA buffers are linear. */ -+ if (tmpl->nr_samples > 1) -+ rsc->tiled = false; -+ -+ /* Cursors are always linear, and the user can request linear as -+ * well. - */ -- if (tmpl->target == PIPE_BUFFER || -- tmpl->nr_samples > 1 || -- (tmpl->bind & (PIPE_BIND_SCANOUT | -- PIPE_BIND_LINEAR | -- PIPE_BIND_SHARED | -- PIPE_BIND_CURSOR))) { -+ if (tmpl->bind & (PIPE_BIND_LINEAR | -+ PIPE_BIND_CURSOR)) { - rsc->tiled = false; -- } else { -- rsc->tiled = true; - } - -- if (tmpl->target != PIPE_BUFFER) -- rsc->vc4_format = get_resource_texture_format(prsc); -+ /* No shared objects with LT format -- the kernel only has T-format -+ * metadata. LT objects are small enough it's not worth the trouble -+ * to give them metadata to tile. -+ */ -+ if ((tmpl->bind & PIPE_BIND_SHARED) && -+ vc4_size_is_lt(prsc->width0, prsc->height0, rsc->cpp)) { -+ rsc->tiled = false; -+ } - - vc4_setup_slices(rsc); - if (!vc4_resource_bo_alloc(rsc)) - goto fail; - -+ if (tmpl->bind & PIPE_BIND_SHARED) { -+ assert(rsc->slices[0].tiling == VC4_TILING_FORMAT_T); -+ -+ struct drm_vc4_set_tiling set_tiling = { -+ .handle = rsc->bo->handle, -+ .modifier = DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED, -+ }; -+ int ret = vc4_ioctl(screen->fd, -+ DRM_IOCTL_VC4_SET_TILING, -+ &set_tiling); -+ -+ /* If we hit this, we're probably on an old kernel. Fall back -+ * to linear. -+ */ -+ if (ret != 0) { -+ rsc->tiled = false; -+ vc4_setup_slices(rsc); -+ if (!vc4_resource_bo_alloc(rsc)) -+ goto fail; -+ } -+ } -+ -+ if (tmpl->target != PIPE_BUFFER) -+ rsc->vc4_format = get_resource_texture_format(prsc); -+ - return prsc; - fail: - vc4_resource_destroy(pscreen, prsc); -@@ -593,29 +632,10 @@ vc4_resource_from_handle(struct pipe_screen *pscreen, - struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl); - struct pipe_resource *prsc = &rsc->base; - struct vc4_resource_slice *slice = &rsc->slices[0]; -- uint32_t expected_stride = -- align(prsc->width0, vc4_utile_width(rsc->cpp)) * rsc->cpp; - - if (!rsc) - return NULL; - -- if (whandle->stride != expected_stride) { -- static bool warned = false; -- if (!warned) { -- warned = true; -- fprintf(stderr, -- "Attempting to import %dx%d %s with " -- "unsupported stride %d instead of %d\n", -- prsc->width0, prsc->height0, -- util_format_short_name(prsc->format), -- whandle->stride, -- expected_stride); -- } -- goto fail; -- } -- -- rsc->tiled = false; -- - if (whandle->offset != 0) { - fprintf(stderr, - "Attempt to import unsupported winsys offset %u\n", -@@ -641,10 +661,17 @@ vc4_resource_from_handle(struct pipe_screen *pscreen, - if (!rsc->bo) - goto fail; - -- slice->stride = whandle->stride; -- slice->tiling = VC4_TILING_FORMAT_LINEAR; -+ struct drm_vc4_get_tiling get_tiling = { -+ .handle = rsc->bo->handle, -+ }; -+ int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_TILING, &get_tiling); -+ if (ret == 0 && -+ get_tiling.modifier == DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED) { -+ rsc->tiled = true; -+ } - - rsc->vc4_format = get_resource_texture_format(prsc); -+ vc4_setup_slices(rsc); - - if (miptree_debug) { - fprintf(stderr, -@@ -655,6 +682,21 @@ vc4_resource_from_handle(struct pipe_screen *pscreen, - slice->stride, slice->offset); - } - -+ if (whandle->stride != rsc->slices[0].stride) { -+ static bool warned = false; -+ if (!warned) { -+ warned = true; -+ fprintf(stderr, -+ "Attempting to import %dx%d %s with " -+ "unsupported stride %d instead of %d\n", -+ prsc->width0, prsc->height0, -+ util_format_short_name(prsc->format), -+ whandle->stride, -+ rsc->slices[0].stride); -+ } -+ goto fail; -+ } -+ - return prsc; - - fail: -diff --git a/src/gallium/drivers/vc4/vc4_simulator.c b/src/gallium/drivers/vc4/vc4_simulator.c -index ab701ab560..bd063a8432 100644 ---- a/src/gallium/drivers/vc4/vc4_simulator.c -+++ b/src/gallium/drivers/vc4/vc4_simulator.c -@@ -658,9 +658,17 @@ vc4_simulator_ioctl(int fd, unsigned long request, void *args) - case DRM_IOCTL_GEM_CLOSE: - return vc4_simulator_gem_close_ioctl(fd, args); - -+ case DRM_IOCTL_VC4_GET_TILING: -+ case DRM_IOCTL_VC4_SET_TILING: -+ /* Disable these for now, since the sharing with i965 requires -+ * linear buffers. -+ */ -+ return -1; -+ - case DRM_IOCTL_GEM_OPEN: - case DRM_IOCTL_GEM_FLINK: - return drmIoctl(fd, request, args); -+ - default: - fprintf(stderr, "Unknown ioctl 0x%08x\n", (int)request); - abort(); diff --git a/mesa-7.1.2-etnaviv-fixes.patch b/mesa-7.1.2-etnaviv-fixes.patch deleted file mode 100644 index cdaba29..0000000 --- a/mesa-7.1.2-etnaviv-fixes.patch +++ /dev/null @@ -1,122 +0,0 @@ -From patchwork Thu Jun 8 16:25:34 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [Mesa-dev,1/2] etnaviv: fix varying interpolation -From: Lucas Stach -X-Patchwork-Id: 160584 -Message-Id: <20170608162535.2198-1-l.stach@pengutronix.de> -To: mesa-dev@lists.freedesktop.org -Cc: graphics@pengutronix.de, etnaviv@lists.freedesktop.org, - patchwork-lst@pengutronix.de -Date: Thu, 8 Jun 2017 18:25:34 +0200 - -It seems that newer cores don't use the PA_ATTRIBUTES to decide if the -varying should bypass the flat shading, but derive this from the component -use. This fixes flat shading on GC880+. - -VARYING_COMPONENT_USE_POINTCOORD is a bit of a misnomer now, as it isn't -only used for pointcoords, but missing a better name I left it as-is. - -Signed-off-by: Lucas Stach ---- - src/gallium/drivers/etnaviv/etnaviv_compiler.c | 24 ++++++++++-------------- - 1 file changed, 10 insertions(+), 14 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c b/src/gallium/drivers/etnaviv/etnaviv_compiler.c -index eafb511bb813..2605924613c7 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c -@@ -2552,6 +2552,7 @@ etna_link_shader(struct etna_shader_link_info *info, - const struct etna_shader_inout *fsio = &fs->infile.reg[idx]; - const struct etna_shader_inout *vsio = etna_shader_vs_lookup(vs, fsio); - struct etna_varying *varying; -+ bool interpolate = fsio->semantic.Name != TGSI_SEMANTIC_COLOR; - - assert(fsio->reg > 0 && fsio->reg <= ARRAY_SIZE(info->varyings)); - -@@ -2561,28 +2562,23 @@ etna_link_shader(struct etna_shader_link_info *info, - varying = &info->varyings[fsio->reg - 1]; - varying->num_components = fsio->num_components; - -- if (fsio->semantic.Name == TGSI_SEMANTIC_COLOR) /* colors affected by flat shading */ -+ if (!interpolate) /* colors affected by flat shading */ - varying->pa_attributes = 0x200; - else /* texture coord or other bypasses flat shading */ - varying->pa_attributes = 0x2f1; - -- if (fsio->semantic.Name == TGSI_SEMANTIC_PCOORD) { -- varying->use[0] = VARYING_COMPONENT_USE_POINTCOORD_X; -- varying->use[1] = VARYING_COMPONENT_USE_POINTCOORD_Y; -- varying->use[2] = VARYING_COMPONENT_USE_USED; -- varying->use[3] = VARYING_COMPONENT_USE_USED; -- varying->reg = 0; /* replaced by point coord -- doesn't matter */ -+ varying->use[0] = interpolate ? VARYING_COMPONENT_USE_POINTCOORD_X : VARYING_COMPONENT_USE_USED; -+ varying->use[1] = interpolate ? VARYING_COMPONENT_USE_POINTCOORD_Y : VARYING_COMPONENT_USE_USED; -+ varying->use[2] = VARYING_COMPONENT_USE_USED; -+ varying->use[3] = VARYING_COMPONENT_USE_USED; -+ varying->reg = vsio->reg; /* replaced by point coord -- doesn't matter */ -+ -+ -+ if (fsio->semantic.Name == TGSI_SEMANTIC_PCOORD) - continue; -- } - - if (vsio == NULL) - return true; /* not found -- link error */ -- -- varying->use[0] = VARYING_COMPONENT_USE_USED; -- varying->use[1] = VARYING_COMPONENT_USE_USED; -- varying->use[2] = VARYING_COMPONENT_USE_USED; -- varying->use[3] = VARYING_COMPONENT_USE_USED; -- varying->reg = vsio->reg; - } - - assert(info->num_varyings == fs->infile.num_reg); -From patchwork Thu Jun 8 16:25:35 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [Mesa-dev,2/2] etnaviv: remove flat shading workaround -From: Lucas Stach -X-Patchwork-Id: 160585 -Message-Id: <20170608162535.2198-2-l.stach@pengutronix.de> -To: mesa-dev@lists.freedesktop.org -Cc: graphics@pengutronix.de, etnaviv@lists.freedesktop.org, - patchwork-lst@pengutronix.de -Date: Thu, 8 Jun 2017 18:25:35 +0200 - -It turned out not to be a hardware bug, but the shader compiler -emitting wrong varying component use information. With that fixed -we can turn flat shading back on. - -Signed-off-by: Lucas Stach -Reviewed-by: Philipp Zabel ---- - src/gallium/drivers/etnaviv/etnaviv_rasterizer.c | 6 +----- - 1 file changed, 1 insertion(+), 5 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c b/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c -index 4990fd180257..56f2735e8a18 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c -@@ -38,10 +38,6 @@ etna_rasterizer_state_create(struct pipe_context *pctx, - struct etna_rasterizer_state *cs; - struct etna_context *ctx = etna_context(pctx); - -- /* Disregard flatshading on GC880+, as a HW bug there seem to disable all -- * varying interpolation if it's enabled */ -- bool flatshade = ctx->screen->model < 880 ? so->flatshade : false; -- - if (so->fill_front != so->fill_back) - DBG("Different front and back fill mode not supported"); - -@@ -51,7 +47,7 @@ etna_rasterizer_state_create(struct pipe_context *pctx, - - cs->base = *so; - -- cs->PA_CONFIG = (flatshade ? VIVS_PA_CONFIG_SHADE_MODEL_FLAT : VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH) | -+ cs->PA_CONFIG = (so->flatshade ? VIVS_PA_CONFIG_SHADE_MODEL_FLAT : VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH) | - translate_cull_face(so->cull_face, so->front_ccw) | - translate_polygon_mode(so->fill_front) | - COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) | diff --git a/mesa-7.1.2-etnaviv-upstream-fixes.patch b/mesa-7.1.2-etnaviv-upstream-fixes.patch deleted file mode 100644 index a3ceabf..0000000 --- a/mesa-7.1.2-etnaviv-upstream-fixes.patch +++ /dev/null @@ -1,640 +0,0 @@ -From f8a39914586de004759ea9cbda1335bdf0790cdc Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Wed, 10 May 2017 18:01:06 +0200 -Subject: [PATCH 0479/1430] etnaviv: apply feature overrides in one central - location - -This way we can just test the feature bits and don't need to spread -the debug overrides to all locations touching a feature. - -Signed-off-by: Lucas Stach -Reviewed-By: Wladimir J. van der Laan -Reviewed-by: Christian Gmeiner ---- - src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 6 ++---- - src/gallium/drivers/etnaviv/etnaviv_resource.c | 2 +- - src/gallium/drivers/etnaviv/etnaviv_screen.c | 10 ++++++++++ - src/gallium/drivers/etnaviv/etnaviv_surface.c | 2 +- - src/gallium/drivers/etnaviv/etnaviv_zsa.c | 9 +++++---- - 5 files changed, 19 insertions(+), 10 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c -index 528b57389d..ae1c586288 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c -@@ -111,8 +111,7 @@ etna_blit_clear_color(struct pipe_context *pctx, struct pipe_surface *dst, - if (surf->surf.ts_size) { /* TS: use precompiled clear command */ - ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value; - -- if (!DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE) && -- VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) { -+ if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) { - /* Set number of color tiles to be filled */ - etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT, - surf->surf.padded_width * surf->surf.padded_height / 16); -@@ -171,8 +170,7 @@ etna_blit_clear_zs(struct pipe_context *pctx, struct pipe_surface *dst, - if (surf->surf.ts_size) { /* TS: use precompiled clear command */ - /* Set new clear depth value */ - ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value; -- if (!DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE) && -- VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) { -+ if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) { - /* Set number of depth tiles to be filled */ - etna_set_state(ctx->stream, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT, - surf->surf.padded_width * surf->surf.padded_height / 16); -diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c -index 26f2ed7334..103b53c1c3 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_resource.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c -@@ -247,7 +247,7 @@ etna_resource_create(struct pipe_screen *pscreen, - layout = ETNA_LAYOUT_LINEAR; - } else if (templat->target != PIPE_BUFFER) { - bool want_multitiled = false; -- bool want_supertiled = screen->specs.can_supertile && !DBG_ENABLED(ETNA_DBG_NO_SUPERTILE); -+ bool want_supertiled = screen->specs.can_supertile; - - /* When this GPU supports single-buffer rendering, don't ever enable - * multi-tiling. This replicates the blob behavior on GC3000. -diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c -index d8a970b910..9f1b44922a 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_screen.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c -@@ -831,6 +831,16 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, - if (!etna_get_specs(screen)) - goto fail; - -+ /* apply debug options that disable individual features */ -+ if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) -+ screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; -+ if (DBG_ENABLED(ETNA_DBG_NO_TS)) -+ screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; -+ if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) -+ screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; -+ if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) -+ screen->specs.can_supertile = 0; -+ - pscreen->destroy = etna_screen_destroy; - pscreen->get_param = etna_screen_get_param; - pscreen->get_paramf = etna_screen_get_paramf; -diff --git a/src/gallium/drivers/etnaviv/etnaviv_surface.c b/src/gallium/drivers/etnaviv/etnaviv_surface.c -index 1db9b40a51..4b95f6575a 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_surface.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_surface.c -@@ -66,7 +66,7 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, - - if (VIV_FEATURE(ctx->screen, chipFeatures, FAST_CLEAR) && - VIV_FEATURE(ctx->screen, chipMinorFeatures0, MC20) && -- !DBG_ENABLED(ETNA_DBG_NO_TS) && !rsc->ts_bo && -+ !rsc->ts_bo && - (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 && - (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0) { - etna_screen_resource_alloc_ts(pctx->screen, rsc); -diff --git a/src/gallium/drivers/etnaviv/etnaviv_zsa.c b/src/gallium/drivers/etnaviv/etnaviv_zsa.c -index 7caba279b3..22c2020fe5 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_zsa.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_zsa.c -@@ -27,13 +27,17 @@ - #include "etnaviv_zsa.h" - - #include "etnaviv_context.h" -+#include "etnaviv_screen.h" - #include "etnaviv_translate.h" - #include "util/u_memory.h" - -+#include "hw/common.xml.h" -+ - void * - etna_zsa_state_create(struct pipe_context *pctx, - const struct pipe_depth_stencil_alpha_state *so) - { -+ struct etna_context *ctx = etna_context(pctx); - struct etna_zsa_state *cs = CALLOC_STRUCT(etna_zsa_state); - - if (!cs) -@@ -42,7 +46,7 @@ etna_zsa_state_create(struct pipe_context *pctx, - cs->base = *so; - - /* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */ -- bool early_z = true; -+ bool early_z = !VIV_FEATURE(ctx->screen, chipFeatures, NO_EARLY_Z); - bool disable_zs = - (!so->depth.enabled || so->depth.func == PIPE_FUNC_ALWAYS) && - !so->depth.writemask; -@@ -88,9 +92,6 @@ etna_zsa_state_create(struct pipe_context *pctx, - if (so->depth.enabled == false || so->depth.func == PIPE_FUNC_ALWAYS) - early_z = false; - -- if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) -- early_z = false; -- - /* compare funcs have 1 to 1 mapping */ - cs->PE_DEPTH_CONFIG = - VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(so->depth.enabled ? so->depth.func --- -2.13.0 - -From ba0b7de7e36a5032c709ce1f9b36706bdbba5097 Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Wed, 10 May 2017 18:01:07 +0200 -Subject: [PATCH 0480/1430] etnaviv: clean up sampler view reference counting - -Use the proper pipe_resource_reference function instead of -rolling our own. - -Signed-off-by: Lucas Stach -Reviewed-by: Christian Gmeiner ---- - src/gallium/drivers/etnaviv/etnaviv_texture.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c b/src/gallium/drivers/etnaviv/etnaviv_texture.c -index 3a842381ac..6f77af286f 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_texture.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c -@@ -182,9 +182,9 @@ etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, - } - - sv->base = *so; -- pipe_reference(NULL, &prsc->reference); -- sv->base.texture = prsc; -- sv->base.reference.count = 1; -+ pipe_reference_init(&sv->base.reference, 1); -+ sv->base.texture = NULL; -+ pipe_resource_reference(&sv->base.texture, prsc); - sv->base.context = pctx; - - /* merged with sampler state */ --- -2.13.0 - -From cb16d9103480687c414519bed5256217c9e7aaad Mon Sep 17 00:00:00 2001 -From: Philipp Zabel -Date: Wed, 10 May 2017 18:01:08 +0200 -Subject: [PATCH 0481/1430] etnaviv: increment the resource seqno in - resource_changed - -Just increment the resource seqno instead of setting the texture -seqno to be lower by one than the resource seqno. - -Signed-off-by: Philipp Zabel -Signed-off-by: Lucas Stach -Reviewed-By: Wladimir J. van der Laan -Reviewed-by: Christian Gmeiner ---- - src/gallium/drivers/etnaviv/etnaviv_resource.c | 6 +----- - 1 file changed, 1 insertion(+), 5 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c -index 103b53c1c3..1341e1ea23 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_resource.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c -@@ -286,11 +286,7 @@ etna_resource_changed(struct pipe_screen *pscreen, struct pipe_resource *prsc) - { - struct etna_resource *res = etna_resource(prsc); - -- /* Make sure texture is older than the imported renderable buffer, -- * so etna_update_sampler_source will copy the pixel data again. -- */ -- if (res->texture) -- etna_resource(res->texture)->seqno = res->seqno - 1; -+ res->seqno++; - } - - static void --- -2.13.0 -From a276c32a08bd41ceb8fd9b604ba9ac8229d59b64 Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Thu, 18 May 2017 15:37:02 +0200 -Subject: [PATCH 1243/1430] etnaviv: slim down resource waiting - -cpu_prep() already does all the required waiting, so the only thing that -needs to be done is flushing the commandstream, if a GPU write is pending. - -Signed-off-by: Lucas Stach -Reviewed-by: Wladimir J. van der Laan ---- - src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 5 +++-- - src/gallium/drivers/etnaviv/etnaviv_resource.c | 16 ---------------- - src/gallium/drivers/etnaviv/etnaviv_resource.h | 3 --- - src/gallium/drivers/etnaviv/etnaviv_transfer.c | 5 +++-- - 4 files changed, 6 insertions(+), 23 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c -index ae1c586288..ea416bf192 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c -@@ -528,8 +528,9 @@ etna_try_rs_blit(struct pipe_context *pctx, - - manual: - if (src->layout == ETNA_LAYOUT_TILED && dst->layout == ETNA_LAYOUT_TILED) { -- etna_resource_wait(pctx, dst); -- etna_resource_wait(pctx, src); -+ if ((src->status & ETNA_PENDING_WRITE) || -+ (dst->status & ETNA_PENDING_WRITE)) -+ pctx->flush(pctx, NULL, 0); - return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, src_offset, blit_info); - } - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c -index 1341e1ea23..9aa1aa617a 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_resource.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c -@@ -429,22 +429,6 @@ etna_resource_used(struct etna_context *ctx, struct pipe_resource *prsc, - } - - void --etna_resource_wait(struct pipe_context *pctx, struct etna_resource *rsc) --{ -- if (rsc->status & ETNA_PENDING_WRITE) { -- struct pipe_fence_handle *fence; -- struct pipe_screen *pscreen = pctx->screen; -- -- pctx->flush(pctx, &fence, 0); -- -- if (!pscreen->fence_finish(pscreen, pctx, fence, 5000000000ULL)) -- BUG("fence timed out (hung GPU?)"); -- -- pscreen->fence_reference(pscreen, &fence, NULL); -- } --} -- --void - etna_resource_screen_init(struct pipe_screen *pscreen) - { - pscreen->can_create_resource = etna_screen_can_create_resource; -diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h b/src/gallium/drivers/etnaviv/etnaviv_resource.h -index a8d42ee1a0..913316f193 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_resource.h -+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h -@@ -124,9 +124,6 @@ void - etna_resource_used(struct etna_context *ctx, struct pipe_resource *prsc, - enum etna_resource_status status); - --void --etna_resource_wait(struct pipe_context *ctx, struct etna_resource *rsc); -- - static inline void - resource_read(struct etna_context *ctx, struct pipe_resource *prsc) - { -diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -index 4809b04ff9..269bd498f8 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -@@ -199,8 +199,9 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, - /* Always sync if we have the temporary resource. The PIPE_TRANSFER_READ - * case could be optimised if we knew whether the resource has outstanding - * rendering. */ -- if (usage & PIPE_TRANSFER_READ || trans->rsc) -- etna_resource_wait(pctx, rsc); -+ if ((usage & PIPE_TRANSFER_READ || trans->rsc) && -+ rsc->status & ETNA_PENDING_WRITE) -+ pctx->flush(pctx, NULL, 0); - - /* XXX we don't handle PIPE_TRANSFER_FLUSH_EXPLICIT; this flag can be ignored - * when mapping in-place, --- -2.13.0 - -From c3b2c7a75f1ef6306d0218d92564319d22cfc8fe Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Thu, 18 May 2017 18:20:12 +0200 -Subject: [PATCH 1244/1430] etnaviv: honor PIPE_TRANSFER_UNSYNCHRONIZED flag - -This gets rid of quite a bit of CPU/GPU sync on frequent vertex buffer -uploads and I haven't seen any of the issues mentioned in the comment, -so this one seems stale. - -Ignore the flag if there exists a temporary resource, as those ones are -never busy. - -Signed-off-by: Lucas Stach -Reviewed-by: Wladimir J. van der Laan ---- - src/gallium/drivers/etnaviv/etnaviv_transfer.c | 35 +++++++++++++++++--------- - 1 file changed, 23 insertions(+), 12 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -index 269bd498f8..4ead6dff7f 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -@@ -70,6 +70,10 @@ etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans) - if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture))) - rsc = etna_resource(rsc->texture); /* switch to using the texture resource */ - -+ /* -+ * Temporary resources are always pulled into the CPU domain, must push them -+ * back into GPU domain before the RS execs the blit to the base resource. -+ */ - if (trans->rsc) - etna_bo_cpu_fini(etna_resource(trans->rsc)->bo); - -@@ -114,7 +118,12 @@ etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans) - } - } - -- if (!trans->rsc) -+ /* -+ * Transfers without a temporary are only pulled into the CPU domain if they -+ * are not mapped unsynchronized. If they are, must push them back into GPU -+ * domain after CPU access is finished. -+ */ -+ if (!trans->rsc && !(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED)) - etna_bo_cpu_fini(rsc->bo); - - pipe_resource_reference(&trans->rsc, NULL); -@@ -260,19 +269,21 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, - (rsc->layout == ETNA_LAYOUT_TILED && - util_format_is_compressed(prsc->format)); - -- /* Ignore PIPE_TRANSFER_UNSYNCHRONIZED and PIPE_TRANSFER_DONTBLOCK here. -- * It appears that Gallium operates the index/vertex buffers in a -- * circular fashion, and the CPU can catch up with the GPU and starts -- * overwriting yet-to-be-processed entries, causing rendering corruption. */ -- uint32_t prep_flags = 0; -+ /* -+ * Pull resources into the CPU domain. Only skipped for unsynchronized -+ * transfers without a temporary resource. -+ */ -+ if (trans->rsc || !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { -+ uint32_t prep_flags = 0; - -- if (usage & PIPE_TRANSFER_READ) -- prep_flags |= DRM_ETNA_PREP_READ; -- if (usage & PIPE_TRANSFER_WRITE) -- prep_flags |= DRM_ETNA_PREP_WRITE; -+ if (usage & PIPE_TRANSFER_READ) -+ prep_flags |= DRM_ETNA_PREP_READ; -+ if (usage & PIPE_TRANSFER_WRITE) -+ prep_flags |= DRM_ETNA_PREP_WRITE; - -- if (etna_bo_cpu_prep(rsc->bo, prep_flags)) -- goto fail_prep; -+ if (etna_bo_cpu_prep(rsc->bo, prep_flags)) -+ goto fail_prep; -+ } - - /* map buffer object */ - void *mapped = etna_bo_map(rsc->bo); --- -2.13.0 - -From 6e628ee3f3cd250d58f1b49fc0b53db58cd8eeea Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Thu, 18 May 2017 16:30:02 +0200 -Subject: [PATCH 1245/1430] etnaviv: don't read back resource if transfer - discards contents - -Reduces bandwidth usage of transfers which discard the buffer contents, -as well as skipping unnecessary command stream flushes and CPU/GPU -synchronization. - -Signed-off-by: Lucas Stach -Reviewed-by: Wladimir J. van der Laan ---- - src/gallium/drivers/etnaviv/etnaviv_transfer.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -index 4ead6dff7f..707029865a 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -@@ -197,7 +197,9 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, - return NULL; - } - -- etna_copy_resource(pctx, trans->rsc, prsc, level, trans->rsc->last_level); -+ if (!(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)) -+ etna_copy_resource(pctx, trans->rsc, prsc, level, -+ trans->rsc->last_level); - - /* Switch to using the temporary resource instead */ - rsc = etna_resource(trans->rsc); --- -2.13.0 - -From d4e6de9e385579d49cd5f51e643d0141c81b5604 Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Thu, 18 May 2017 16:44:18 +0200 -Subject: [PATCH 1246/1430] etnaviv: simplify transfer tiling handling - -There is no need to special case compressed resources, as they are already -marked as linear on allocation. With that out of the way, there is room to -cut down on the number of if clauses used. - -Signed-off-by: Lucas Stach -Reviewed-by: Wladimir J. van der Laan ---- - src/gallium/drivers/etnaviv/etnaviv_transfer.c | 70 +++++++++++--------------- - 1 file changed, 29 insertions(+), 41 deletions(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -index 707029865a..8a18dbb8fc 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -@@ -89,21 +89,19 @@ etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans) - struct etna_resource_level *res_level = &rsc->levels[ptrans->level]; - void *mapped = etna_bo_map(rsc->bo) + res_level->offset; - -- if (rsc->layout == ETNA_LAYOUT_LINEAR || rsc->layout == ETNA_LAYOUT_TILED) { -- if (rsc->layout == ETNA_LAYOUT_TILED && !util_format_is_compressed(rsc->base.format)) { -- etna_texture_tile( -- mapped + ptrans->box.z * res_level->layer_stride, -- trans->staging, ptrans->box.x, ptrans->box.y, -- res_level->stride, ptrans->box.width, ptrans->box.height, -- ptrans->stride, util_format_get_blocksize(rsc->base.format)); -- } else { /* non-tiled or compressed format */ -- util_copy_box(mapped, rsc->base.format, res_level->stride, -- res_level->layer_stride, ptrans->box.x, -- ptrans->box.y, ptrans->box.z, ptrans->box.width, -- ptrans->box.height, ptrans->box.depth, -- trans->staging, ptrans->stride, -- ptrans->layer_stride, 0, 0, 0 /* src x,y,z */); -- } -+ if (rsc->layout == ETNA_LAYOUT_TILED) { -+ etna_texture_tile( -+ mapped + ptrans->box.z * res_level->layer_stride, -+ trans->staging, ptrans->box.x, ptrans->box.y, -+ res_level->stride, ptrans->box.width, ptrans->box.height, -+ ptrans->stride, util_format_get_blocksize(rsc->base.format)); -+ } else if (rsc->layout == ETNA_LAYOUT_LINEAR) { -+ util_copy_box(mapped, rsc->base.format, res_level->stride, -+ res_level->layer_stride, ptrans->box.x, -+ ptrans->box.y, ptrans->box.z, ptrans->box.width, -+ ptrans->box.height, ptrans->box.depth, -+ trans->staging, ptrans->stride, -+ ptrans->layer_stride, 0, 0, 0 /* src x,y,z */); - } else { - BUG("unsupported tiling %i", rsc->layout); - } -@@ -264,13 +262,6 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, - PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is set. - */ - -- /* No need to allocate a buffer for copying if the resource is not in use, -- * and no tiling is needed, can just return a direct pointer. -- */ -- bool in_place = rsc->layout == ETNA_LAYOUT_LINEAR || -- (rsc->layout == ETNA_LAYOUT_TILED && -- util_format_is_compressed(prsc->format)); -- - /* - * Pull resources into the CPU domain. Only skipped for unsynchronized - * transfers without a temporary resource. -@@ -294,7 +285,7 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, - - *out_transfer = ptrans; - -- if (in_place) { -+ if (rsc->layout == ETNA_LAYOUT_LINEAR) { - ptrans->stride = res_level->stride; - ptrans->layer_stride = res_level->layer_stride; - -@@ -321,24 +312,21 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, - goto fail; - - if (usage & PIPE_TRANSFER_READ) { -- /* untile or copy resource for reading */ -- if (rsc->layout == ETNA_LAYOUT_LINEAR || rsc->layout == ETNA_LAYOUT_TILED) { -- if (rsc->layout == ETNA_LAYOUT_TILED && !util_format_is_compressed(rsc->base.format)) { -- etna_texture_untile(trans->staging, -- mapped + ptrans->box.z * res_level->layer_stride, -- ptrans->box.x, ptrans->box.y, res_level->stride, -- ptrans->box.width, ptrans->box.height, ptrans->stride, -- util_format_get_blocksize(rsc->base.format)); -- } else { /* non-tiled or compressed format */ -- util_copy_box(trans->staging, rsc->base.format, ptrans->stride, -- ptrans->layer_stride, 0, 0, 0, /* dst x,y,z */ -- ptrans->box.width, ptrans->box.height, -- ptrans->box.depth, mapped, res_level->stride, -- res_level->layer_stride, ptrans->box.x, -- ptrans->box.y, ptrans->box.z); -- } -- } else /* TODO supertiling */ -- { -+ if (rsc->layout == ETNA_LAYOUT_TILED) { -+ etna_texture_untile(trans->staging, -+ mapped + ptrans->box.z * res_level->layer_stride, -+ ptrans->box.x, ptrans->box.y, res_level->stride, -+ ptrans->box.width, ptrans->box.height, ptrans->stride, -+ util_format_get_blocksize(rsc->base.format)); -+ } else if (rsc->layout == ETNA_LAYOUT_LINEAR) { -+ util_copy_box(trans->staging, rsc->base.format, ptrans->stride, -+ ptrans->layer_stride, 0, 0, 0, /* dst x,y,z */ -+ ptrans->box.width, ptrans->box.height, -+ ptrans->box.depth, mapped, res_level->stride, -+ res_level->layer_stride, ptrans->box.x, -+ ptrans->box.y, ptrans->box.z); -+ } else { -+ /* TODO supertiling */ - BUG("unsupported tiling %i for reading", rsc->layout); - } - } --- -2.13.0 - -From 0f888ad4be32d1c66e2749feacb8b88def03fac9 Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Thu, 18 May 2017 17:05:02 +0200 -Subject: [PATCH 1247/1430] etnaviv: upgrade DISCARD_RANGE to - DISCARD_WHOLE_RESOURCE if possible - -Stolen from VC4. As we don't do any fancy reallocation tricks yet, it's -possible to upgrade also coherent mappings and shared resources. - -Signed-off-by: Lucas Stach -Reviewed-by: Wladimir J. van der Laan ---- - src/gallium/drivers/etnaviv/etnaviv_transfer.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -index 8a18dbb8fc..27e1be1957 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c -@@ -157,6 +157,20 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, - - assert(level <= prsc->last_level); - -+ /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is -+ * being mapped. If we add buffer reallocation to avoid CPU/GPU sync this -+ * check needs to be extended to coherent mappings and shared resources. -+ */ -+ if ((usage & PIPE_TRANSFER_DISCARD_RANGE) && -+ !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) && -+ prsc->last_level == 0 && -+ prsc->width0 == box->width && -+ prsc->height0 == box->height && -+ prsc->depth0 == box->depth && -+ prsc->array_size == 1) { -+ usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE; -+ } -+ - if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture))) { - /* We have a texture resource which is the same age or newer than the - * render resource. Use the texture resource, which avoids bouncing --- -2.13.0 - -From f25390afa49f51fadaafed70a890093f96e7a02d Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Sun, 4 Jun 2017 06:24:20 +0200 -Subject: [PATCH 1248/1430] etnaviv: don't flush resource to self without TS - -A resolve to self is only necessary if the resource is fast cleared, so -there is never a need to do so if there is no TS allocated. - -Signed-off-by: Lucas Stach -Reviewed-by: Wladimir J. van der Laan ---- - src/gallium/drivers/etnaviv/etnaviv_resource.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h b/src/gallium/drivers/etnaviv/etnaviv_resource.h -index 913316f193..3507e5ccec 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_resource.h -+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h -@@ -102,7 +102,7 @@ etna_resource_older(struct etna_resource *a, struct etna_resource *b) - static inline bool - etna_resource_needs_flush(struct etna_resource *res) - { -- return (int)(res->seqno - res->flush_seqno) > 0; -+ return res->ts_bo && ((int)(res->seqno - res->flush_seqno) > 0); - } - - /* is the resource only used on the sampler? */ --- -2.13.0 - -From 978e6876f1cd8ccc8850a5665e9619a3e29b731e Mon Sep 17 00:00:00 2001 -From: Lucas Stach -Date: Mon, 15 May 2017 17:06:41 +0200 -Subject: [PATCH 1249/1430] etnaviv: flush resource when binding as sampler - view - -As TS is also allowed on sampler resources, we need to make sure to resolve -to self when binding the resource as a texture, to avoid stale content -being sampled. - -Signed-off-by: Lucas Stach ---- - src/gallium/drivers/etnaviv/etnaviv_texture.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c b/src/gallium/drivers/etnaviv/etnaviv_texture.c -index 6f77af286f..df77829078 100644 ---- a/src/gallium/drivers/etnaviv/etnaviv_texture.c -+++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c -@@ -120,6 +120,9 @@ etna_update_sampler_source(struct pipe_sampler_view *view) - etna_copy_resource(view->context, res->texture, view->texture, 0, - view->texture->last_level); - etna_resource(res->texture)->seqno = res->seqno; -+ } else if (etna_resource_needs_flush(res)) { -+ etna_copy_resource(view->context, view->texture, view->texture, 0, 0); -+ res->flush_seqno = res->seqno; - } - } - --- -2.13.0 - diff --git a/mesa.spec b/mesa.spec index 0426db2..8d6f113 100644 --- a/mesa.spec +++ b/mesa.spec @@ -54,12 +54,12 @@ %global sanitize 1 -#global rctag rc4 +%global rctag rc4 Name: mesa Summary: Mesa graphics libraries -Version: 17.1.5 -Release: 1%{?rctag:.%{rctag}}%{?dist}.2 +Version: 17.2.0 +Release: 0.1%{?rctag:.%{rctag}}%{?dist} License: MIT URL: http://www.mesa3d.org @@ -78,13 +78,10 @@ Patch4: 0004-bigendian-assert.patch # glvnd support patches # non-upstreamed ones -Patch13: glvnd-fix-gl-dot-pc.patch -Patch14: 0001-Fix-linkage-against-shared-glapi.patch +Patch10: glvnd-fix-gl-dot-pc.patch +Patch11: 0001-Fix-linkage-against-shared-glapi.patch # backport from upstream -Patch51: mesa-7.1.2-etnaviv-upstream-fixes.patch -Patch52: mesa-7.1.2-etnaviv-fixes.patch -Patch53: mesa-7.1-vc4-fixes.patch BuildRequires: gcc BuildRequires: gcc-c++ @@ -123,6 +120,7 @@ BuildRequires: bison flex %if %{with wayland} BuildRequires: pkgconfig(wayland-client) BuildRequires: pkgconfig(wayland-server) +BuildRequires: pkgconfig(wayland-protocols) %endif %if 0%{?with_vdpau} BuildRequires: libvdpau-devel @@ -683,6 +681,9 @@ popd %endif %changelog +* Sun Aug 13 2017 Peter Robinson 17.2.0-0.1.rc4 +- Update to 17.2.0-rc4 + * Thu Aug 03 2017 Fedora Release Engineering - 17.1.5-1.2 - Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Binutils_Mass_Rebuild diff --git a/sources b/sources index ef4b29c..3d77f4f 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (mesa-17.1.5.tar.xz) = a12671afd812b304e1db690b123a9de16332608541f71cc3ee9128a3630c81416d46255e5bdbf19e14e85716b218f447987b555e3bc0081b8b6f392556fa21e2 +SHA512 (mesa-17.2.0-rc4.tar.xz) = a5e2727bd91185db440d94b273cc32e9907d3a64b3f5ea33d5888f7aa2bfec54d7db57eeee6109a8dc28e9efec97ea23e895117ba52f1963cb2bc2b22b718595