From 07ce0166ac29aa395c56bb7e11e68a8a42060c97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Exp=C3=B3sito?= Date: Mon, 8 Jan 2024 10:59:58 +0100 Subject: [PATCH] Update patch "intel/compiler: reemit boolean resolve for inverted if on gen5" The patch has been accepted upstream with some minor changes. Update it to match the version upstream. --- ...eemit-boolean-resolve-for-inverted-i.patch | 25 +++++++++++-------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/0001-intel-compiler-reemit-boolean-resolve-for-inverted-i.patch b/0001-intel-compiler-reemit-boolean-resolve-for-inverted-i.patch index 43c1f5d..3544491 100644 --- a/0001-intel-compiler-reemit-boolean-resolve-for-inverted-i.patch +++ b/0001-intel-compiler-reemit-boolean-resolve-for-inverted-i.patch @@ -1,4 +1,4 @@ -From c59f3601b81bf38cbb7a2b77820f1d827f608339 Mon Sep 17 00:00:00 2001 +From 56a72e014fcda3c52cf119115cb71fce2fad86d8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 21 Dec 2023 10:39:08 +1000 Subject: [PATCH] intel/compiler: reemit boolean resolve for inverted if on @@ -8,30 +8,35 @@ Gen5 adds some boolean conversion instructions after nir emits, but that nir srcs don't line up with them, so reemit the boolean conversion if we reemit the inot. +Reviewed-by: Lionel Landwerlin Fixes: 31b5f5a51f3a ("nir/opt_if: Simplify if's with general conditions") +Part-of: --- - src/intel/compiler/brw_fs_nir.cpp | 8 ++++++++ - 1 file changed, 8 insertions(+) + src/intel/compiler/brw_fs_nir.cpp | 11 +++++++++++ + 1 file changed, 11 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp -index b9f7366763b..5a4ec96e93f 100644 +index 33f2a4046b2..ccdd0fe7db8 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp -@@ -361,6 +361,14 @@ fs_visitor::nir_emit_if(nir_if *if_stmt) +@@ -422,6 +422,17 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) invert = true; - cond_reg = get_nir_src(cond->src[0].src); + cond_reg = get_nir_src(ntb, cond->src[0].src); cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]); + -+ if (devinfo->ver <= 5) { ++ if (devinfo->ver <= 5 && ++ (cond->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { + /* redo boolean resolve on gen5 */ -+ fs_reg masked = bld.vgrf(BRW_REGISTER_TYPE_D); ++ fs_reg masked = ntb.s.vgrf(glsl_int_type()); + bld.AND(masked, cond_reg, brw_imm_d(1)); + masked.negate = true; -+ bld.MOV(retype(cond_reg, BRW_REGISTER_TYPE_D), masked); ++ fs_reg tmp = bld.vgrf(cond_reg.type); ++ bld.MOV(retype(tmp, BRW_REGISTER_TYPE_D), masked); ++ cond_reg = tmp; + } } else { invert = false; - cond_reg = get_nir_src(if_stmt->condition); + cond_reg = get_nir_src(ntb, if_stmt->condition); -- 2.43.0