forked from rpms/glibc
179 lines
7.7 KiB
Diff
179 lines
7.7 KiB
Diff
From 180897c161a171d8ef0faee1c6c9fd6b57d8b13b Mon Sep 17 00:00:00 2001
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From: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Wed, 7 Jun 2023 13:18:03 -0500
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Subject: [PATCH] x86: Make the divisor in setting `non_temporal_threshold` cpu
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specific
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Content-type: text/plain; charset=UTF-8
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Different systems prefer a different divisors.
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From benchmarks[1] so far the following divisors have been found:
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ICX : 2
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SKX : 2
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BWD : 8
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For Intel, we are generalizing that BWD and older prefers 8 as a
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divisor, and SKL and newer prefers 2. This number can be further tuned
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as benchmarks are run.
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[1]: https://github.com/goldsteinn/memcpy-nt-benchmarks
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Reviewed-by: DJ Delorie <dj@redhat.com>
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---
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sysdeps/x86/cpu-features.c | 31 ++++++++++++++++++++---------
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sysdeps/x86/dl-cacheinfo.h | 32 ++++++++++++++++++------------
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sysdeps/x86/dl-diagnostics-cpu.c | 11 ++++++----
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sysdeps/x86/include/cpu-features.h | 3 +++
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4 files changed, 51 insertions(+), 26 deletions(-)
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[DJ - edited for ABI compatibility]
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diff -rup a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
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--- a/sysdeps/x86/cpu-features.c 2023-07-26 17:56:19.679300711 -0400
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+++ b/sysdeps/x86/cpu-features.c 2023-07-28 15:27:00.336324265 -0400
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@@ -35,6 +35,9 @@ extern void TUNABLE_CALLBACK (set_x86_sh
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# endif
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#endif
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+unsigned long int __rtld_global_ro_cachesize_non_temporal_divisor
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+ attribute_hidden;
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+
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#if CET_ENABLED
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# include <dl-cet.h>
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#endif
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@@ -614,6 +617,7 @@ init_cpu_features (struct cpu_features *
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unsigned int stepping = 0;
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enum cpu_features_kind kind;
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+ __rtld_global_ro_cachesize_non_temporal_divisor = 4;
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#if !HAS_CPUID
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if (__get_cpuid_max (0, 0) == 0)
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{
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@@ -694,13 +698,13 @@ init_cpu_features (struct cpu_features *
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/* Bigcore/Default Tuning. */
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default:
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+ default_tuning:
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/* Unknown family 0x06 processors. Assuming this is one
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of Core i3/i5/i7 processors if AVX is available. */
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if (!CPU_FEATURES_CPU_P (cpu_features, AVX))
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break;
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- /* Fall through. */
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- case INTEL_BIGCORE_NEHALEM:
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- case INTEL_BIGCORE_WESTMERE:
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+
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+ enable_modern_features:
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/* Rep string instructions, unaligned load, unaligned copy,
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and pminub are fast on Intel Core i3, i5 and i7. */
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cpu_features->preferred[index_arch_Fast_Rep_String]
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@@ -710,12 +714,23 @@ init_cpu_features (struct cpu_features *
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| bit_arch_Prefer_PMINUB_for_stringop);
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break;
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- /*
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- Default tuned Bigcore microarch.
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+ case INTEL_BIGCORE_NEHALEM:
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+ case INTEL_BIGCORE_WESTMERE:
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+ /* Older CPUs prefer non-temporal stores at lower threshold. */
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+ __rtld_global_ro_cachesize_non_temporal_divisor = 8;
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+ goto enable_modern_features;
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+
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+ /* Older Bigcore microarch (smaller non-temporal store
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+ threshold). */
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case INTEL_BIGCORE_SANDYBRIDGE:
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case INTEL_BIGCORE_IVYBRIDGE:
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case INTEL_BIGCORE_HASWELL:
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case INTEL_BIGCORE_BROADWELL:
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+ __rtld_global_ro_cachesize_non_temporal_divisor = 8;
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+ goto default_tuning;
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+
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+ /* Newer Bigcore microarch (larger non-temporal store
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+ threshold). */
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case INTEL_BIGCORE_SKYLAKE:
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case INTEL_BIGCORE_KABYLAKE:
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case INTEL_BIGCORE_COMETLAKE:
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@@ -731,13 +746,14 @@ init_cpu_features (struct cpu_features *
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case INTEL_BIGCORE_SAPPHIRERAPIDS:
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case INTEL_BIGCORE_EMERALDRAPIDS:
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case INTEL_BIGCORE_GRANITERAPIDS:
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- */
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+ __rtld_global_ro_cachesize_non_temporal_divisor = 2;
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+ goto default_tuning;
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- /*
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- Default tuned Mixed (bigcore + atom SOC).
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+ /* Default tuned Mixed (bigcore + atom SOC). */
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case INTEL_MIXED_LAKEFIELD:
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case INTEL_MIXED_ALDERLAKE:
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- */
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+ __rtld_global_ro_cachesize_non_temporal_divisor = 2;
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+ goto default_tuning;
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}
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/* Disable TSX on some processors to avoid TSX on kernels that
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diff -rup a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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--- a/sysdeps/x86/dl-cacheinfo.h 2023-07-26 17:56:18.662261475 -0400
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+++ b/sysdeps/x86/dl-cacheinfo.h 2023-07-26 17:56:20.756342261 -0400
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@@ -744,19 +744,25 @@ dl_init_cacheinfo (struct cpu_features *
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cpu_features->level3_cache_linesize = level3_cache_linesize;
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cpu_features->level4_cache_size = level4_cache_size;
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- /* The default setting for the non_temporal threshold is 1/4 of size
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- of the chip's cache. For most Intel and AMD processors with an
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- initial release date between 2017 and 2023, a thread's typical
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- share of the cache is from 18-64MB. Using the 1/4 L3 is meant to
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- estimate the point where non-temporal stores begin out-competing
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- REP MOVSB. As well the point where the fact that non-temporal
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- stores are forced back to main memory would already occurred to the
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- majority of the lines in the copy. Note, concerns about the
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- entire L3 cache being evicted by the copy are mostly alleviated
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- by the fact that modern HW detects streaming patterns and
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- provides proper LRU hints so that the maximum thrashing
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- capped at 1/associativity. */
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- unsigned long int non_temporal_threshold = shared / 4;
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+ unsigned long int cachesize_non_temporal_divisor
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+ = __rtld_global_ro_cachesize_non_temporal_divisor;
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+ if (cachesize_non_temporal_divisor <= 0)
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+ cachesize_non_temporal_divisor = 4;
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+
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+ /* The default setting for the non_temporal threshold is [1/8, 1/2] of size
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+ of the chip's cache (depending on `cachesize_non_temporal_divisor` which
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+ is microarch specific. The defeault is 1/4). For most Intel and AMD
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+ processors with an initial release date between 2017 and 2023, a thread's
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+ typical share of the cache is from 18-64MB. Using a reasonable size
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+ fraction of L3 is meant to estimate the point where non-temporal stores
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+ begin out-competing REP MOVSB. As well the point where the fact that
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+ non-temporal stores are forced back to main memory would already occurred
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+ to the majority of the lines in the copy. Note, concerns about the entire
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+ L3 cache being evicted by the copy are mostly alleviated by the fact that
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+ modern HW detects streaming patterns and provides proper LRU hints so that
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+ the maximum thrashing capped at 1/associativity. */
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+ unsigned long int non_temporal_threshold
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+ = shared / cachesize_non_temporal_divisor;
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/* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
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a higher risk of actually thrashing the cache as they don't have a HW LRU
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hint. As well, their performance in highly parallel situations is
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diff -rup a/sysdeps/x86/dl-diagnostics-cpu.c b/sysdeps/x86/dl-diagnostics-cpu.c
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--- a/sysdeps/x86/dl-diagnostics-cpu.c 2021-08-01 21:33:43.000000000 -0400
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+++ b/sysdeps/x86/dl-diagnostics-cpu.c 2023-07-26 17:56:20.761342454 -0400
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@@ -117,4 +117,6 @@ _dl_diagnostics_cpu (void)
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+ sizeof (cpu_features->level4_cache_size)
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== sizeof (*cpu_features),
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"last cpu_features field has been printed");
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+ print_cpu_features_value ("cachesize_non_temporal_divisor",
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+ __rtld_global_ro_cachesize_non_temporal_divisor);
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}
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diff -rup a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
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--- a/sysdeps/x86/include/cpu-features.h 2021-08-01 21:33:43.000000000 -0400
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+++ b/sysdeps/x86/include/cpu-features.h 2023-07-27 13:51:52.081494751 -0400
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@@ -919,6 +919,10 @@ struct cpu_features
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unsigned long int level4_cache_size;
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};
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+/* When no user non_temporal_threshold is specified. We default to
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+ cachesize / cachesize_non_temporal_divisor. */
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+extern unsigned long int __rtld_global_ro_cachesize_non_temporal_divisor;
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+
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/* Get a pointer to the CPU features structure. */
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extern const struct cpu_features *_dl_x86_get_cpu_features (void)
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__attribute__ ((pure));
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