forked from rpms/glibc
112 lines
4.3 KiB
Diff
112 lines
4.3 KiB
Diff
commit 856bab7717ef6d1033fd7cbf7cfb2ddefbfffb07
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Author: Andreas Schwab <schwab@suse.de>
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Date: Thu Feb 9 14:56:21 2023 +0100
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x86/dl-cacheinfo: remove unsused parameter from handle_amd
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Also replace an unreachable assert with __builtin_unreachable.
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Conflicts:
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sysdeps/x86/dl-cacheinfo.h
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(different backport order downstream)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index 3408700fc0b06e5b..cc2f8862ce88f655 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -311,7 +311,7 @@ handle_intel (int name, const struct cpu_features *cpu_features)
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static long int __attribute__ ((noinline))
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-handle_amd (int name, const struct cpu_features *cpu_features)
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+handle_amd (int name)
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{
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unsigned int eax;
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unsigned int ebx;
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@@ -334,24 +334,23 @@ handle_amd (int name, const struct cpu_features *cpu_features)
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switch (name)
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{
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- case _SC_LEVEL1_ICACHE_ASSOC:
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- case _SC_LEVEL1_DCACHE_ASSOC:
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- case _SC_LEVEL2_CACHE_ASSOC:
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- case _SC_LEVEL3_CACHE_ASSOC:
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- return ecx?((ebx >> 22) & 0x3ff) + 1 : 0;
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- case _SC_LEVEL1_ICACHE_LINESIZE:
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- case _SC_LEVEL1_DCACHE_LINESIZE:
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- case _SC_LEVEL2_CACHE_LINESIZE:
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- case _SC_LEVEL3_CACHE_LINESIZE:
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- return ecx?(ebx & 0xfff) + 1 : 0;
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- case _SC_LEVEL1_ICACHE_SIZE:
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- case _SC_LEVEL1_DCACHE_SIZE:
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- case _SC_LEVEL2_CACHE_SIZE:
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- case _SC_LEVEL3_CACHE_SIZE:
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- return ecx?(((ebx >> 22) & 0x3ff) + 1)*((ebx & 0xfff) + 1)\
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- *(ecx + 1):0;
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- default:
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- assert (! "cannot happen");
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+ case _SC_LEVEL1_ICACHE_ASSOC:
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+ case _SC_LEVEL1_DCACHE_ASSOC:
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+ case _SC_LEVEL2_CACHE_ASSOC:
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+ case _SC_LEVEL3_CACHE_ASSOC:
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+ return ecx ? ((ebx >> 22) & 0x3ff) + 1 : 0;
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+ case _SC_LEVEL1_ICACHE_LINESIZE:
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+ case _SC_LEVEL1_DCACHE_LINESIZE:
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+ case _SC_LEVEL2_CACHE_LINESIZE:
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+ case _SC_LEVEL3_CACHE_LINESIZE:
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+ return ecx ? (ebx & 0xfff) + 1 : 0;
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+ case _SC_LEVEL1_ICACHE_SIZE:
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+ case _SC_LEVEL1_DCACHE_SIZE:
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+ case _SC_LEVEL2_CACHE_SIZE:
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+ case _SC_LEVEL3_CACHE_SIZE:
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+ return ecx ? (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1): 0;
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+ default:
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+ __builtin_unreachable ();
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}
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return -1;
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}
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@@ -701,31 +700,26 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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}
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else if (cpu_features->basic.kind == arch_kind_amd)
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{
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- data = handle_amd (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
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- core = handle_amd (_SC_LEVEL2_CACHE_SIZE, cpu_features);
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- shared = handle_amd (_SC_LEVEL3_CACHE_SIZE, cpu_features);
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+ data = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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+ core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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+ shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
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shared_per_thread = shared;
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- level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE, cpu_features);
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- level1_icache_linesize
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- = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE, cpu_features);
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+ level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE);
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+ level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE);
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level1_dcache_size = data;
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- level1_dcache_assoc
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- = handle_amd (_SC_LEVEL1_DCACHE_ASSOC, cpu_features);
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- level1_dcache_linesize
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- = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features);
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+ level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC);
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+ level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE);
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level2_cache_size = core;
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- level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC, cpu_features);
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- level2_cache_linesize
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- = handle_amd (_SC_LEVEL2_CACHE_LINESIZE, cpu_features);
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+ level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC);
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+ level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE);
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level3_cache_size = shared;
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- level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC, cpu_features);
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- level3_cache_linesize
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- = handle_amd (_SC_LEVEL3_CACHE_LINESIZE, cpu_features);
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+ level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC);
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+ level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE);
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if (shared <= 0)
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/* No shared L3 cache. All we have is the L2 cache. */
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- shared = core;
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+ shared = core;
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if (shared_per_thread <= 0)
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shared_per_thread = shared;
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