forked from rpms/glibc
57 lines
2.1 KiB
Diff
57 lines
2.1 KiB
Diff
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commit 1d401d1fccb85046402089268b94d86d822070e6
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Author: Aurelien Jarno <aurelien@aurel32.net>
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Date: Mon Jan 17 19:41:40 2022 +0100
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x86: use default cache size if it cannot be determined [BZ #28784]
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In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can
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not be retrieved and the corresponding values are set to 0.
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Commit 2d651eb9265d ("x86: Move x86 processor cache info to
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cpu_features") changed the behaviour in such case by defining the
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__x86_shared_cache_size and __x86_data_cache_size variables to 0 instead
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of using the default values. This cause an issue with the i686 SSE2
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optimized bzero/routine which assumes that the cache size is at least
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128 bytes, and otherwise tries to zero/set the whole address space minus
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128 bytes.
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Fix that by restoring the original code to only update
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__x86_shared_cache_size and __x86_data_cache_size variables if the
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corresponding cache sizes are not zero.
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Fixes bug 28784
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Fixes commit 2d651eb9265d
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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(cherry picked from commit c242fcce06e3102ca663b2f992611d0bda4f2668)
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diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h
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index 41d2c81369840ada..63f36877e3f35d99 100644
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--- a/sysdeps/x86/cacheinfo.h
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+++ b/sysdeps/x86/cacheinfo.h
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@@ -61,14 +61,20 @@ init_cacheinfo (void)
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long int data = cpu_features->data_cache_size;
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/* Round data cache size to multiple of 256 bytes. */
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data = data & ~255L;
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- __x86_data_cache_size_half = data / 2;
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- __x86_data_cache_size = data;
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+ if (data > 0)
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+ {
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+ __x86_data_cache_size_half = data / 2;
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+ __x86_data_cache_size = data;
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+ }
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long int shared = cpu_features->shared_cache_size;
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/* Round shared cache size to multiple of 256 bytes. */
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shared = shared & ~255L;
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- __x86_shared_cache_size_half = shared / 2;
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- __x86_shared_cache_size = shared;
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+ if (shared > 0)
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+ {
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+ __x86_shared_cache_size_half = shared / 2;
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+ __x86_shared_cache_size = shared;
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+ }
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__x86_shared_non_temporal_threshold
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= cpu_features->non_temporal_threshold;
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