forked from rpms/glibc
29 lines
993 B
Diff
29 lines
993 B
Diff
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commit d201c59177b98946d7f80145e7b4d02991d04805
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Author: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Fri Jun 24 09:42:12 2022 -0700
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x86: Align entry for memrchr to 64-bytes.
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The function was tuned around 64-byte entry alignment and performs
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better for all sizes with it.
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As well different code boths where explicitly written to touch the
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minimum number of cache line i.e sizes <= 32 touch only the entry
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cache line.
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(cherry picked from commit 227afaa67213efcdce6a870ef5086200f1076438)
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diff --git a/sysdeps/x86_64/multiarch/memrchr-avx2.S b/sysdeps/x86_64/multiarch/memrchr-avx2.S
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index 5f8e0be18cfe4fad..edd8180ba1ede9a5 100644
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--- a/sysdeps/x86_64/multiarch/memrchr-avx2.S
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+++ b/sysdeps/x86_64/multiarch/memrchr-avx2.S
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@@ -35,7 +35,7 @@
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# define VEC_SIZE 32
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# define PAGE_SIZE 4096
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.section SECTION(.text), "ax", @progbits
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-ENTRY(MEMRCHR)
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+ENTRY_P2ALIGN(MEMRCHR, 6)
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# ifdef __ILP32__
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/* Clear upper bits. */
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and %RDX_LP, %RDX_LP
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