forked from rpms/glibc
56 lines
3.0 KiB
Diff
56 lines
3.0 KiB
Diff
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From 8b9a0af8ca012217bf90d1dc0694f85b49ae09da Mon Sep 17 00:00:00 2001
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From: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Tue, 18 Jul 2023 10:27:59 -0500
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Subject: [PATCH] [PATCH v1] x86: Use `3/4*sizeof(per-thread-L3)` as low bound
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for NT threshold.
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Content-type: text/plain; charset=UTF-8
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On some machines we end up with incomplete cache information. This can
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make the new calculation of `sizeof(total-L3)/custom-divisor` end up
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lower than intended (and lower than the prior value). So reintroduce
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the old bound as a lower bound to avoid potentially regressing code
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where we don't have complete information to make the decision.
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Reviewed-by: DJ Delorie <dj@redhat.com>
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---
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sysdeps/x86/dl-cacheinfo.h | 15 ++++++++++++---
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1 file changed, 12 insertions(+), 3 deletions(-)
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[diff rebased by DJ]
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diff -rup a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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--- a/sysdeps/x86/dl-cacheinfo.h 2023-07-25 00:38:43.343986368 -0400
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+++ b/sysdeps/x86/dl-cacheinfo.h 2023-07-25 00:38:44.336025100 -0400
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@@ -751,8 +751,8 @@ dl_init_cacheinfo (struct cpu_features *
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/* The default setting for the non_temporal threshold is [1/8, 1/2] of size
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of the chip's cache (depending on `cachesize_non_temporal_divisor` which
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- is microarch specific. The defeault is 1/4). For most Intel and AMD
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- processors with an initial release date between 2017 and 2023, a thread's
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+ is microarch specific. The default is 1/4). For most Intel processors
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+ with an initial release date between 2017 and 2023, a thread's
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typical share of the cache is from 18-64MB. Using a reasonable size
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fraction of L3 is meant to estimate the point where non-temporal stores
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begin out-competing REP MOVSB. As well the point where the fact that
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@@ -763,12 +763,21 @@ dl_init_cacheinfo (struct cpu_features *
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the maximum thrashing capped at 1/associativity. */
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unsigned long int non_temporal_threshold
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= shared / cachesize_non_temporal_divisor;
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+
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+ /* If the computed non_temporal_threshold <= 3/4 * per-thread L3, we most
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+ likely have incorrect/incomplete cache info in which case, default to
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+ 3/4 * per-thread L3 to avoid regressions. */
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+ unsigned long int non_temporal_threshold_lowbound
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+ = shared_per_thread * 3 / 4;
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+ if (non_temporal_threshold < non_temporal_threshold_lowbound)
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+ non_temporal_threshold = non_temporal_threshold_lowbound;
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+
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/* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
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a higher risk of actually thrashing the cache as they don't have a HW LRU
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hint. As well, their performance in highly parallel situations is
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noticeably worse. */
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if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS))
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- non_temporal_threshold = shared_per_thread * 3 / 4;
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+ non_temporal_threshold = non_temporal_threshold_lowbound;
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/* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
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'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best
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if that operation cannot overflow. Minimum of 0x4040 (16448) because the
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