forked from rpms/glibc
47 lines
2.1 KiB
Diff
47 lines
2.1 KiB
Diff
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commit 691f70b84a1284f35c8cf9fbf3ef3b1cec41c234
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Author: Vladislav Khmelevsky <och95@yandex.ru>
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Date: Thu Nov 17 12:47:29 2022 +0400
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elf: Fix rtld-audit trampoline for aarch64
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This patch fixes two problems with audit:
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1. The DL_OFFSET_RV_VPCS offset was mixed up with DL_OFFSET_RG_VPCS,
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resulting in x2 register value nulling in RG structure.
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2. We need to preserve the x8 register before function call, but
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don't have to save it's new value and restore it before return.
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Anyway the final restore was using OFFSET_RV instead of OFFSET_RG value
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which is wrong (althoug doesn't affect anything).
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Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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(cherry picked from commit eb4181e9f4a512de37dad4ba623c921671584dea)
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diff --git a/sysdeps/aarch64/dl-trampoline.S b/sysdeps/aarch64/dl-trampoline.S
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index 457570e7df5148c0..b84c53d1a544c1b1 100644
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--- a/sysdeps/aarch64/dl-trampoline.S
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+++ b/sysdeps/aarch64/dl-trampoline.S
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@@ -298,12 +298,11 @@ _dl_runtime_profile:
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stp x2, x3, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*1]
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stp x4, x5, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*2]
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stp x6, x7, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*3]
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- str x8, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*4]
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stp q0, q1, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*0]
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stp q2, q3, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*1]
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stp q4, q5, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*2]
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stp q6, q7, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*3]
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- str xzr, [X29, #OFFSET_RV + DL_OFFSET_RG_VPCS]
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+ str xzr, [X29, #OFFSET_RV + DL_OFFSET_RV_VPCS]
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/* Setup call to pltexit */
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ldp x0, x1, [x29, #OFFSET_SAVED_CALL_X0]
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@@ -315,7 +314,6 @@ _dl_runtime_profile:
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ldp x2, x3, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*1]
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ldp x4, x5, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*2]
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ldp x6, x7, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*3]
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- ldr x8, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*4]
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ldp q0, q1, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*0]
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ldp q2, q3, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*1]
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ldp q4, q5, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*2]
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