forked from rpms/glibc
67 lines
3.4 KiB
Diff
67 lines
3.4 KiB
Diff
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commit 89c017de2f52d17862bda9a6f8382e913457bfbe
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Author: H.J. Lu <hjl.tools@gmail.com>
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Date: Tue Jan 3 13:06:48 2023 -0800
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x86: Check minimum/maximum of non_temporal_threshold [BZ #29953]
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The minimum non_temporal_threshold is 0x4040. non_temporal_threshold may
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be set to less than the minimum value when the shared cache size isn't
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available (e.g., in an emulator) or by the tunable. Add checks for
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minimum and maximum of non_temporal_threshold.
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This fixes BZ #29953.
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(cherry picked from commit 48b74865c63840b288bd85b4d8743533b73b339b)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index a7d2cc5fef03884b..f2d2de458db7358c 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -747,6 +747,18 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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share of the cache, it has a substantial risk of negatively
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impacting the performance of other threads running on the chip. */
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unsigned long int non_temporal_threshold = shared * 3 / 4;
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+ /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
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+ 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best
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+ if that operation cannot overflow. Minimum of 0x4040 (16448) because the
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+ L(large_memset_4x) loops need 64-byte to cache align and enough space for
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+ at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are
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+ reflected in the manual. */
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+ unsigned long int maximum_non_temporal_threshold = SIZE_MAX >> 4;
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+ unsigned long int minimum_non_temporal_threshold = 0x4040;
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+ if (non_temporal_threshold < minimum_non_temporal_threshold)
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+ non_temporal_threshold = minimum_non_temporal_threshold;
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+ else if (non_temporal_threshold > maximum_non_temporal_threshold)
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+ non_temporal_threshold = maximum_non_temporal_threshold;
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#if HAVE_TUNABLES
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/* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */
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@@ -801,8 +813,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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shared = tunable_size;
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tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL);
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- /* NB: Ignore the default value 0. */
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- if (tunable_size != 0)
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+ if (tunable_size > minimum_non_temporal_threshold
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+ && tunable_size <= maximum_non_temporal_threshold)
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non_temporal_threshold = tunable_size;
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tunable_size = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL);
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@@ -817,14 +829,9 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX);
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TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX);
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- /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
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- 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best
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- if that operation cannot overflow. Minimum of 0x4040 (16448) because the
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- L(large_memset_4x) loops need 64-byte to cache align and enough space for
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- at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are
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- reflected in the manual. */
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TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, non_temporal_threshold,
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- 0x4040, SIZE_MAX >> 4);
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+ minimum_non_temporal_threshold,
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+ maximum_non_temporal_threshold);
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TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, rep_movsb_threshold,
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minimum_rep_movsb_threshold, SIZE_MAX);
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TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, rep_stosb_threshold, 1,
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