forked from rpms/glibc
60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
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commit 76d5b2f002a1243ddba06bd646249553353f4322
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Author: H.J. Lu <hjl.tools@gmail.com>
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Date: Thu May 21 13:36:54 2020 -0700
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x86: Update Intel Atom processor family optimization
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Enable Intel Silvermont optimization for Intel Goldmont Plus. Detect more
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Intel Airmont processors. Optimize Intel Tremont like Intel Silvermont
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with rep string instructions.
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diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
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index c432d646ce6806a6..2a801e1856cfe1b3 100644
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--- a/sysdeps/x86/cpu-features.c
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+++ b/sysdeps/x86/cpu-features.c
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@@ -347,18 +347,23 @@ init_cpu_features (struct cpu_features *cpu_features)
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case 0x57:
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/* Knights Landing. Enable Silvermont optimizations. */
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+ case 0x7a:
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+ /* Unaligned load versions are faster than SSSE3
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+ on Goldmont Plus. */
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+
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case 0x5c:
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case 0x5f:
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/* Unaligned load versions are faster than SSSE3
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on Goldmont. */
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case 0x4c:
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+ case 0x5a:
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+ case 0x75:
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/* Airmont is a die shrink of Silvermont. */
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case 0x37:
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case 0x4a:
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case 0x4d:
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- case 0x5a:
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case 0x5d:
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/* Unaligned load versions are faster than SSSE3
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on Silvermont. */
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@@ -369,6 +374,19 @@ init_cpu_features (struct cpu_features *cpu_features)
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| bit_arch_Slow_SSE4_2);
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break;
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+ case 0x86:
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+ case 0x96:
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+ case 0x9c:
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+ /* Enable rep string instructions, unaligned load, unaligned
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+ copy, pminub and avoid SSE 4.2 on Tremont. */
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+ cpu_features->feature[index_arch_Fast_Rep_String]
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+ |= (bit_arch_Fast_Rep_String
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+ | bit_arch_Fast_Unaligned_Load
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+ | bit_arch_Fast_Unaligned_Copy
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+ | bit_arch_Prefer_PMINUB_for_stringop
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+ | bit_arch_Slow_SSE4_2);
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+ break;
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+
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default:
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/* Unknown family 0x06 processors. Assuming this is one
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of Core i3/i5/i7 processors if AVX is available. */
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