forked from rpms/glibc
129 lines
4.7 KiB
Diff
129 lines
4.7 KiB
Diff
commit f1c56cdff09f650ad721fae026eb6a3651631f3d
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Author: Paul A. Clarke <pc@us.ibm.com>
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Date: Thu Sep 19 08:35:16 2019 -0500
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[powerpc] SET_RESTORE_ROUND optimizations and bug fix
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SET_RESTORE_ROUND brackets a block of code, temporarily setting and
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restoring the rounding mode and letting everything else, including
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exceptions generated within the block, pass through.
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On powerpc, the current code clears the exception enables, which will hide
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exceptions generated within the block. This issue was introduced by me
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in commit e905212627350d54b58426214b5a54ddc852b0c9.
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Fix this by not clearing exception enable bits in the prologue.
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Also, since we are no longer changing the enable bits in either the
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prologue or the epilogue, there is no need to test for entering/exiting
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non-stop mode.
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Also, optimize the prologue get/save/set rounding mode operations for
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POWER9 and later by using 'mffscrn' when possible.
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Suggested-by: Paul E. Murphy <murphyp@linux.ibm.com>
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Reviewed-by: Paul E. Murphy <murphyp@linux.ibm.com>
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Fixes: e905212627350d54b58426214b5a54ddc852b0c9
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2019-09-19 Paul A. Clarke <pc@us.ibm.com>
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* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_and_set_rn): New.
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(__fe_mffscrn): New.
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* sysdeps/powerpc/fpu/fenv_private.h (libc_feholdsetround_ppc_ctx):
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Do not clear enable bits, remove obsolete code, use
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fegetenv_and_set_rn.
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(libc_feresetround_ppc): Remove obsolete code, use
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fegetenv_and_set_rn.
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diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
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index e8d40ea256b6c5bc..b10b6a141ded4bfd 100644
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--- a/sysdeps/powerpc/fpu/fenv_libc.h
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+++ b/sysdeps/powerpc/fpu/fenv_libc.h
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@@ -49,6 +49,38 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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__fr; \
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})
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+#define __fe_mffscrn(rn) \
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+ ({register fenv_union_t __fr; \
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+ if (__builtin_constant_p (rn)) \
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+ __asm__ __volatile__ ( \
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+ ".machine push; .machine \"power9\"; mffscrni %0,%1; .machine pop" \
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+ : "=f" (__fr.fenv) : "i" (rn)); \
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+ else \
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+ { \
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+ __fr.l = (rn); \
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+ __asm__ __volatile__ ( \
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+ ".machine push; .machine \"power9\"; mffscrn %0,%1; .machine pop" \
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+ : "=f" (__fr.fenv) : "f" (__fr.fenv)); \
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+ } \
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+ __fr.fenv; \
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+ })
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+
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+/* Like fegetenv_status, but also sets the rounding mode. */
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+#ifdef _ARCH_PWR9
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+#define fegetenv_and_set_rn(rn) __fe_mffscrn (rn)
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+#else
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+/* 'mffscrn' will decode to 'mffs' on ARCH < 3_00, which is still necessary
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+ but not sufficient, because it does not set the rounding mode.
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+ Explicitly set the rounding mode when 'mffscrn' actually doesn't. */
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+#define fegetenv_and_set_rn(rn) \
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+ ({register fenv_union_t __fr; \
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+ __fr.fenv = __fe_mffscrn (rn); \
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+ if (__glibc_unlikely (!(GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))) \
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+ __fesetround_inline (rn); \
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+ __fr.fenv; \
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+ })
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+#endif
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+
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/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
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#define fesetenv_register(env) \
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do { \
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diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h
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index b0149aa243e69f5a..30df92c9a4700dee 100644
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--- a/sysdeps/powerpc/fpu/fenv_private.h
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+++ b/sysdeps/powerpc/fpu/fenv_private.h
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@@ -133,16 +133,7 @@ static __always_inline void
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libc_feresetround_ppc (fenv_t *envp)
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{
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fenv_union_t new = { .fenv = *envp };
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-
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- /* If the old env has no enabled exceptions and the new env has any enabled
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- exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
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- hardware into "precise mode" and may cause the FPU to run slower on some
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- hardware. */
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- if ((new.l & _FPU_ALL_TRAPS) != 0)
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- (void) __fe_nomask_env_priv ();
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-
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- /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
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- fesetenv_mode (new.fenv);
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+ fegetenv_and_set_rn (new.l & FPSCR_RN_MASK);
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}
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static __always_inline int
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@@ -184,22 +175,10 @@ libc_feupdateenv_ppc (fenv_t *e)
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static __always_inline void
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libc_feholdsetround_ppc_ctx (struct rm_ctx *ctx, int r)
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{
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- fenv_union_t old, new;
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+ fenv_union_t old;
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- old.fenv = fegetenv_status ();
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-
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- new.l = (old.l & ~(FPSCR_ENABLES_MASK|FPSCR_RN_MASK)) | r;
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-
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- ctx->env = old.fenv;
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- if (__glibc_unlikely (new.l != old.l))
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- {
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- if ((old.l & _FPU_ALL_TRAPS) != 0)
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- (void) __fe_mask_env ();
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- fesetenv_mode (new.fenv);
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- ctx->updated_status = true;
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- }
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- else
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- ctx->updated_status = false;
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+ ctx->env = old.fenv = fegetenv_and_set_rn (r);
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+ ctx->updated_status = (r != (old.l & FPSCR_RN_MASK));
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}
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static __always_inline void
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