forked from rpms/glibc
59 lines
2.6 KiB
Diff
59 lines
2.6 KiB
Diff
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commit 7413c188c77adb26a15cf0e98e0a991d09d73c65
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Author: Paul A. Clarke <pc@us.ibm.com>
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Date: Thu Sep 19 11:18:33 2019 -0500
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[powerpc] libc_feupdateenv_test: optimize FPSCR access
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ROUND_TO_ODD and a couple of other places use libc_feupdateenv_test to
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restore the rounding mode and exception enables, preserve exception flags,
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and test whether given exception(s) were generated.
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If the exception flags haven't changed, then it is sufficient and a bit
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more efficient to just restore the rounding mode and enables, rather than
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writing the full Floating-Point Status and Control Register (FPSCR).
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Reviewed-by: Paul E. Murphy <murphyp@linux.ibm.com>
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diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
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index 36b639c3939586f6..86ae7fda016abd8b 100644
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--- a/sysdeps/powerpc/fpu/fenv_libc.h
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+++ b/sysdeps/powerpc/fpu/fenv_libc.h
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@@ -257,6 +257,10 @@ enum {
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(FPSCR_VE_MASK|FPSCR_OE_MASK|FPSCR_UE_MASK|FPSCR_ZE_MASK|FPSCR_XE_MASK)
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#define FPSCR_BASIC_EXCEPTIONS_MASK \
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(FPSCR_VX_MASK|FPSCR_OX_MASK|FPSCR_UX_MASK|FPSCR_ZX_MASK|FPSCR_XX_MASK)
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+#define FPSCR_EXCEPTIONS_MASK (FPSCR_BASIC_EXCEPTIONS_MASK| \
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+ FPSCR_VXSNAN_MASK|FPSCR_VXISI_MASK|FPSCR_VXIDI_MASK|FPSCR_VXZDZ_MASK| \
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+ FPSCR_VXIMZ_MASK|FPSCR_VXVC_MASK|FPSCR_VXSOFT_MASK|FPSCR_VXSQRT_MASK| \
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+ FPSCR_VXCVI_MASK)
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#define FPSCR_FPRF_MASK \
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(FPSCR_FPRF_C_MASK|FPSCR_FPRF_FL_MASK|FPSCR_FPRF_FG_MASK| \
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FPSCR_FPRF_FE_MASK|FPSCR_FPRF_FU_MASK)
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diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h
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index c236d45db2f399a4..86a3611b3ef41759 100644
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--- a/sysdeps/powerpc/fpu/fenv_private.h
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+++ b/sysdeps/powerpc/fpu/fenv_private.h
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@@ -52,8 +52,20 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
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__TEST_AND_EXIT_NON_STOP (old.l, new.l);
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__TEST_AND_ENTER_NON_STOP (old.l, new.l);
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- /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
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- fesetenv_register (new.fenv);
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+ /* If requesting to keep status, replace control, and merge exceptions,
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+ and exceptions haven't changed, we can just set new control instead
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+ of the whole FPSCR. */
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+ if ((old_mask & (FPSCR_CONTROL_MASK|FPSCR_STATUS_MASK|FPSCR_EXCEPTIONS_MASK))
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+ == (FPSCR_STATUS_MASK|FPSCR_EXCEPTIONS_MASK) &&
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+ (new_mask & (FPSCR_CONTROL_MASK|FPSCR_STATUS_MASK|FPSCR_EXCEPTIONS_MASK))
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+ == (FPSCR_CONTROL_MASK|FPSCR_EXCEPTIONS_MASK) &&
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+ (old.l & FPSCR_EXCEPTIONS_MASK) == (new.l & FPSCR_EXCEPTIONS_MASK))
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+ {
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+ fesetenv_mode (new.fenv);
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+ }
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+ else
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+ /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
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+ fesetenv_register (new.fenv);
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return old.l;
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}
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