74 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			74 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* Copyright 2012-15 Advanced Micro Devices, Inc.
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a
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|  * copy of this software and associated documentation files (the "Software"),
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|  * to deal in the Software without restriction, including without limitation
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|  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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|  * and/or sell copies of the Software, and to permit persons to whom the
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|  * Software is furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in
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|  * all copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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|  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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|  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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|  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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|  * OTHER DEALINGS IN THE SOFTWARE.
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|  *
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|  * Authors: AMD
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|  *
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|  */
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| 
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| #ifndef __DC_OPP_DCN201_H__
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| #define __DC_OPP_DCN201_H__
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| 
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| #include "dcn20/dcn20_opp.h"
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| 
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| #define TO_DCN201_OPP(opp)\
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| 	container_of(opp, struct dcn201_opp, base)
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| 
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| #define OPP_SF(reg_name, field_name, post_fix)\
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| 	.field_name = reg_name ## __ ## field_name ## post_fix
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| 
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| #define OPP_REG_LIST_DCN201(id) \
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| 	OPP_REG_LIST_DCN10(id), \
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| 	OPP_DPG_REG_LIST(id), \
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| 	SRI(FMT_422_CONTROL, FMT, id)
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| 
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| #define OPP_MASK_SH_LIST_DCN201(mask_sh) \
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| 	OPP_MASK_SH_LIST_DCN20(mask_sh)
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| 
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| #define OPP_DCN201_REG_FIELD_LIST(type) \
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| 	OPP_DCN20_REG_FIELD_LIST(type)
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| struct dcn201_opp_shift {
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| 	OPP_DCN201_REG_FIELD_LIST(uint8_t);
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| };
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| 
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| struct dcn201_opp_mask {
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| 	OPP_DCN201_REG_FIELD_LIST(uint32_t);
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| };
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| 
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| struct dcn201_opp_registers {
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| 	OPP_REG_VARIABLE_LIST_DCN2_0;
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| };
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| 
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| struct dcn201_opp {
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| 	struct output_pixel_processor base;
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| 	const struct  dcn201_opp_registers *regs;
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| 	const struct  dcn201_opp_shift *opp_shift;
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| 	const struct  dcn201_opp_mask *opp_mask;
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| 	bool is_write_to_ram_a_safe;
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| };
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| 
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| void dcn201_opp_construct(struct dcn201_opp *oppn201,
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| 	struct dc_context *ctx,
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| 	uint32_t inst,
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| 	const struct dcn201_opp_registers *regs,
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| 	const struct dcn201_opp_shift *opp_shift,
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| 	const struct dcn201_opp_mask *opp_mask);
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| 
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| #endif
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