87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_MPCC_DCN201_H__
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#define __DC_MPCC_DCN201_H__
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#include "dcn20/dcn20_mpc.h"
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#define TO_DCN201_MPC(mpc_base) \
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container_of(mpc_base, struct dcn201_mpc, base)
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#define MPC_REG_LIST_DCN201(inst) \
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MPC_REG_LIST_DCN2_0(inst)
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#define MPC_OUT_MUX_REG_LIST_DCN201(inst) \
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MPC_OUT_MUX_REG_LIST_DCN2_0(inst)
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#define MPC_REG_VARIABLE_LIST_DCN201 \
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MPC_REG_VARIABLE_LIST_DCN2_0
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#define MPC_COMMON_MASK_SH_LIST_DCN201(mask_sh) \
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MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
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SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
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SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
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SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
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SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\
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SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh)
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#define MPC_REG_FIELD_LIST_DCN201(type) \
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MPC_REG_FIELD_LIST_DCN2_0(type) \
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type MPC_OUT_RATE_CONTROL;\
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type MPC_OUT_RATE_CONTROL_DISABLE;\
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type MPC_OUT_FLOW_CONTROL_MODE;\
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type MPC_OUT_FLOW_CONTROL_COUNT0;\
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type MPC_OUT_FLOW_CONTROL_COUNT1;
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struct dcn201_mpc_registers {
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MPC_REG_VARIABLE_LIST_DCN201
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};
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struct dcn201_mpc_shift {
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MPC_REG_FIELD_LIST_DCN201(uint8_t)
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};
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struct dcn201_mpc_mask {
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MPC_REG_FIELD_LIST_DCN201(uint32_t)
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};
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struct dcn201_mpc {
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struct mpc base;
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int mpcc_in_use_mask;
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int num_mpcc;
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const struct dcn201_mpc_registers *mpc_regs;
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const struct dcn201_mpc_shift *mpc_shift;
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const struct dcn201_mpc_mask *mpc_mask;
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};
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void dcn201_mpc_construct(struct dcn201_mpc *mpc201,
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struct dc_context *ctx,
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const struct dcn201_mpc_registers *mpc_regs,
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const struct dcn201_mpc_shift *mpc_shift,
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const struct dcn201_mpc_mask *mpc_mask,
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int num_mpcc);
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#endif
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