266 lines
6.8 KiB
C
266 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell IPSEC offload driver
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*
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* Copyright (C) 2024 Marvell.
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*/
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#ifndef CN10K_IPSEC_H
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#define CN10K_IPSEC_H
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#include <linux/types.h>
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DECLARE_STATIC_KEY_FALSE(cn10k_ipsec_sa_enabled);
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/* CPT instruction size in bytes */
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#define CN10K_CPT_INST_SIZE 64
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/* CPT instruction (CPT_INST_S) queue length */
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#define CN10K_CPT_INST_QLEN 8200
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/* CPT instruction queue size passed to HW is in units of
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* 40*CPT_INST_S messages.
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*/
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#define CN10K_CPT_SIZE_DIV40 (CN10K_CPT_INST_QLEN / 40)
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/* CPT needs 320 free entries */
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#define CN10K_CPT_INST_QLEN_EXTRA_BYTES (320 * CN10K_CPT_INST_SIZE)
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#define CN10K_CPT_EXTRA_SIZE_DIV40 (320 / 40)
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/* CPT instruction queue length in bytes */
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#define CN10K_CPT_INST_QLEN_BYTES \
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((CN10K_CPT_SIZE_DIV40 * 40 * CN10K_CPT_INST_SIZE) + \
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CN10K_CPT_INST_QLEN_EXTRA_BYTES)
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/* CPT instruction group queue length in bytes */
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#define CN10K_CPT_INST_GRP_QLEN_BYTES \
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((CN10K_CPT_SIZE_DIV40 + CN10K_CPT_EXTRA_SIZE_DIV40) * 16)
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/* CPT FC length in bytes */
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#define CN10K_CPT_Q_FC_LEN 128
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/* Default CPT engine group for ipsec offload */
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#define CN10K_DEF_CPT_IPSEC_EGRP 1
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/* CN10K CPT LF registers */
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#define CPT_LFBASE (BLKTYPE_CPT << RVU_FUNC_BLKADDR_SHIFT)
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#define CN10K_CPT_LF_CTL (CPT_LFBASE | 0x10)
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#define CN10K_CPT_LF_INPROG (CPT_LFBASE | 0x40)
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#define CN10K_CPT_LF_Q_BASE (CPT_LFBASE | 0xf0)
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#define CN10K_CPT_LF_Q_SIZE (CPT_LFBASE | 0x100)
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#define CN10K_CPT_LF_Q_INST_PTR (CPT_LFBASE | 0x110)
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#define CN10K_CPT_LF_Q_GRP_PTR (CPT_LFBASE | 0x120)
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#define CN10K_CPT_LF_NQX(a) (CPT_LFBASE | 0x400 | (a) << 3)
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#define CN10K_CPT_LF_CTX_FLUSH (CPT_LFBASE | 0x510)
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/* IPSEC Instruction opcodes */
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#define CN10K_IPSEC_MAJOR_OP_WRITE_SA 0x01UL
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#define CN10K_IPSEC_MINOR_OP_WRITE_SA 0x09UL
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#define CN10K_IPSEC_MAJOR_OP_OUTB_IPSEC 0x2AUL
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enum cn10k_cpt_comp_e {
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CN10K_CPT_COMP_E_NOTDONE = 0x00,
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CN10K_CPT_COMP_E_GOOD = 0x01,
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CN10K_CPT_COMP_E_FAULT = 0x02,
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CN10K_CPT_COMP_E_HWERR = 0x04,
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CN10K_CPT_COMP_E_INSTERR = 0x05,
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CN10K_CPT_COMP_E_WARN = 0x06,
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CN10K_CPT_COMP_E_MASK = 0x3F
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};
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struct cn10k_cpt_inst_queue {
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u8 *vaddr;
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u8 *real_vaddr;
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dma_addr_t dma_addr;
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dma_addr_t real_dma_addr;
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u32 size;
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};
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enum cn10k_cpt_hw_state_e {
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CN10K_CPT_HW_UNAVAILABLE,
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CN10K_CPT_HW_AVAILABLE,
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CN10K_CPT_HW_IN_USE
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};
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struct cn10k_ipsec {
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/* Outbound CPT */
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u64 io_addr;
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atomic_t cpt_state;
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struct cn10k_cpt_inst_queue iq;
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/* SA info */
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u32 sa_size;
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u32 outb_sa_count;
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struct work_struct sa_work;
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struct workqueue_struct *sa_workq;
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};
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/* CN10K IPSEC Security Association (SA) */
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/* SA direction */
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#define CN10K_IPSEC_SA_DIR_INB 0
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#define CN10K_IPSEC_SA_DIR_OUTB 1
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/* SA protocol */
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#define CN10K_IPSEC_SA_IPSEC_PROTO_AH 0
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#define CN10K_IPSEC_SA_IPSEC_PROTO_ESP 1
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/* SA Encryption Type */
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#define CN10K_IPSEC_SA_ENCAP_TYPE_AES_GCM 5
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/* SA IPSEC mode Transport/Tunnel */
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#define CN10K_IPSEC_SA_IPSEC_MODE_TRANSPORT 0
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#define CN10K_IPSEC_SA_IPSEC_MODE_TUNNEL 1
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/* SA AES Key Length */
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#define CN10K_IPSEC_SA_AES_KEY_LEN_128 1
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#define CN10K_IPSEC_SA_AES_KEY_LEN_192 2
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#define CN10K_IPSEC_SA_AES_KEY_LEN_256 3
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/* IV Source */
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#define CN10K_IPSEC_SA_IV_SRC_COUNTER 0
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#define CN10K_IPSEC_SA_IV_SRC_PACKET 3
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struct cn10k_tx_sa_s {
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u64 esn_en : 1; /* W0 */
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u64 rsvd_w0_1_8 : 8;
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u64 hw_ctx_off : 7;
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u64 ctx_id : 16;
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u64 rsvd_w0_32_47 : 16;
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u64 ctx_push_size : 7;
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u64 rsvd_w0_55 : 1;
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u64 ctx_hdr_size : 2;
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u64 aop_valid : 1;
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u64 rsvd_w0_59 : 1;
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u64 ctx_size : 4;
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u64 w1; /* W1 */
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u64 sa_valid : 1; /* W2 */
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u64 sa_dir : 1;
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u64 rsvd_w2_2_3 : 2;
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u64 ipsec_mode : 1;
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u64 ipsec_protocol : 1;
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u64 aes_key_len : 2;
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u64 enc_type : 3;
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u64 rsvd_w2_11_19 : 9;
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u64 iv_src : 2;
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u64 rsvd_w2_22_31 : 10;
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u64 rsvd_w2_32_63 : 32;
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u64 w3; /* W3 */
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u8 cipher_key[32]; /* W4 - W7 */
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u32 rsvd_w8_0_31; /* W8 : IV */
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u32 iv_gcm_salt;
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u64 rsvd_w9_w30[22]; /* W9 - W30 */
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u64 hw_ctx[6]; /* W31 - W36 */
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};
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/* CPT instruction parameter-1 */
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#define CN10K_IPSEC_INST_PARAM1_DIS_L4_CSUM 0x1
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#define CN10K_IPSEC_INST_PARAM1_DIS_L3_CSUM 0x2
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#define CN10K_IPSEC_INST_PARAM1_CRYPTO_MODE 0x20
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#define CN10K_IPSEC_INST_PARAM1_IV_OFFSET_SHIFT 8
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/* CPT instruction parameter-2 */
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#define CN10K_IPSEC_INST_PARAM2_ENC_DATA_OFFSET_SHIFT 0
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#define CN10K_IPSEC_INST_PARAM2_AUTH_DATA_OFFSET_SHIFT 8
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/* CPT Instruction Structure */
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struct cpt_inst_s {
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u64 nixtxl : 3; /* W0 */
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u64 doneint : 1;
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u64 rsvd_w0_4_15 : 12;
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u64 dat_offset : 8;
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u64 ext_param1 : 8;
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u64 nixtx_offset : 20;
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u64 rsvd_w0_52_63 : 12;
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u64 res_addr; /* W1 */
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u64 tag : 32; /* W2 */
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u64 tt : 2;
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u64 grp : 10;
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u64 rsvd_w2_44_47 : 4;
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u64 rvu_pf_func : 16;
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u64 qord : 1; /* W3 */
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u64 rsvd_w3_1_2 : 2;
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u64 wqe_ptr : 61;
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u64 dlen : 16; /* W4 */
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u64 param2 : 16;
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u64 param1 : 16;
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u64 opcode_major : 8;
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u64 opcode_minor : 8;
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u64 dptr; /* W5 */
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u64 rptr; /* W6 */
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u64 cptr : 60; /* W7 */
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u64 ctx_val : 1;
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u64 egrp : 3;
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};
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/* CPT Instruction Result Structure */
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struct cpt_res_s {
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u64 compcode : 7; /* W0 */
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u64 doneint : 1;
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u64 uc_compcode : 8;
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u64 uc_info : 48;
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u64 esn; /* W1 */
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};
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/* CPT SG structure */
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struct cpt_sg_s {
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u64 seg1_size : 16;
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u64 seg2_size : 16;
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u64 seg3_size : 16;
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u64 segs : 2;
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u64 rsvd_63_50 : 14;
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};
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/* CPT LF_INPROG Register */
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#define CPT_LF_INPROG_INFLIGHT GENMASK_ULL(8, 0)
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#define CPT_LF_INPROG_GRB_CNT GENMASK_ULL(39, 32)
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#define CPT_LF_INPROG_GWB_CNT GENMASK_ULL(47, 40)
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/* CPT LF_Q_GRP_PTR Register */
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#define CPT_LF_Q_GRP_PTR_DQ_PTR GENMASK_ULL(14, 0)
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#define CPT_LF_Q_GRP_PTR_NQ_PTR GENMASK_ULL(46, 32)
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/* CPT LF_Q_SIZE Register */
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#define CPT_LF_Q_BASE_ADDR GENMASK_ULL(52, 7)
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/* CPT LF_Q_SIZE Register */
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#define CPT_LF_Q_SIZE_DIV40 GENMASK_ULL(14, 0)
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/* CPT LF CTX Flush Register */
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#define CPT_LF_CTX_FLUSH GENMASK_ULL(45, 0)
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#ifdef CONFIG_XFRM_OFFLOAD
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int cn10k_ipsec_init(struct net_device *netdev);
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void cn10k_ipsec_clean(struct otx2_nic *pf);
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int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable);
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bool otx2_sqe_add_sg_ipsec(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
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struct sk_buff *skb, int num_segs, int *offset);
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bool cn10k_ipsec_transmit(struct otx2_nic *pf, struct netdev_queue *txq,
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struct otx2_snd_queue *sq, struct sk_buff *skb,
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int num_segs, int size);
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#else
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static inline __maybe_unused int cn10k_ipsec_init(struct net_device *netdev)
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{
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return 0;
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}
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static inline __maybe_unused void cn10k_ipsec_clean(struct otx2_nic *pf)
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{
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}
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static inline __maybe_unused
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int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable)
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{
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return 0;
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}
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static inline bool __maybe_unused
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otx2_sqe_add_sg_ipsec(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
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struct sk_buff *skb, int num_segs, int *offset)
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{
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return true;
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}
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static inline bool __maybe_unused
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cn10k_ipsec_transmit(struct otx2_nic *pf, struct netdev_queue *txq,
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struct otx2_snd_queue *sq, struct sk_buff *skb,
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int num_segs, int size)
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{
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return true;
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}
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#endif
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#endif // CN10K_IPSEC_H
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